JP4982918B2 - Liquid crystal display substrate and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display substrate and a manufacturing method thereof, and more particularly to an active matrix liquid crystal display substrate in which a thin film transistor and a storage capacitor are formed on the same substrate and a manufacturing method thereof.
[0002]
[Prior art]
In recent years, with the miniaturization of a semiconductor device, the gate length of a MOS transistor is shortened, and there is a problem that the reliability of the transistor is lowered due to hot carrier injection and a short channel effect. Therefore, in order to prevent a decrease in device reliability in a high electric field region near the drain, an LDD (Lightly Doped Drain) structure having a gradient in impurity concentration is widely used. This LDD structure increases the punch-through voltage and hot carrier breakdown voltage by forming an offset gate layer having a low impurity concentration on the substrate surface between the gate and the source / drain.
[0003]
Here, a method of manufacturing a general LDD structure MOSFET formed on a Si substrate will be described with reference to FIG. First, as shown in FIG. 6A, an isolation oxide film 14 is formed on a Si substrate 13 by a LOCOS method, and a field region sandwiched between the isolation oxide films 14 is made of a silicon oxide film by a thermal oxidation method. After the gate insulating film 5 is formed, polysilicon is grown using a low pressure CVD method or the like, and the gate electrode 6 is formed using a photolithography technique and a dry etching technique. Thereafter, low concentration ions are implanted into the entire surface of the substrate by ion implantation using the gate electrode 6 as a mask, and annealing is performed under predetermined conditions to form the low concentration implanted regions 3a and 3b.
[0004]
Next, as shown in FIG. 6B, a silicon oxide film or the like is deposited on the entire surface of the substrate by a low pressure CVD method or the like, and the silicon oxide film is etched back by anisotropic dry etching. Sidewall oxide films 15 are formed. Then, as shown in FIG. 6C, high concentration ion implantation is performed using the gate electrode 6 and the sidewall oxide film 15 as a mask to form high concentration implantation regions 4a and 4b. As a result, the low concentration implantation regions 3a and 3b to be offset gate layers are formed directly below the sidewall oxide film 15, and the high concentration implantation regions 4a and 4b are formed in a self-aligned manner outside the low concentration implantation regions 3a and 3b.
[0005]
In such a MOSFET having an LDD structure, the punch-through voltage and the hot carrier breakdown voltage can be increased by the low-concentration implantation region 3 a on the drain side, but the offset layer immediately below the sidewall oxide film 15 is symmetric with respect to the gate electrode 6. Therefore, on the source side, the parasitic resistance is increased by the low concentration implantation region 3b, and the ON resistance of the transistor is increased.
[0006]
In order to solve this problem, Japanese Patent Application Laid-Open No. 10-70196, Japanese Patent Application Laid-Open No. 10-12881, etc. describe a method of forming the low concentration injection regions 3a and 3b asymmetrically with respect to the gate electrode 6. ing. The method for forming the MOSFET having the asymmetric LDD structure on the Si substrate will be described. First, after forming a silicon oxide film as the gate insulating film 5 on the Si substrate 13 as in the case of the symmetric LDD structure described above. Then, polysilicon is deposited using a low pressure CVD method or the like, and etched into a predetermined shape to form the gate electrode 6. Then, low concentration ions are implanted into the entire surface of the substrate by ion implantation using the gate electrode 6 as a mask, and annealing is performed under predetermined conditions to form the low concentration implanted regions 3a and 3b.
[0007]
Next, a silicon oxide film or the like is deposited on the entire surface of the substrate by low pressure CVD or the like, and the silicon oxide film is etched back by anisotropic dry etching. At this time, the ion implantation angle of plasma etching is changed from a vertical angle to a predetermined angle. The side wall oxide films 15a and 15b having asymmetrical thickness are formed on the side wall of the gate electrode 6 by performing dry etching while tilting only by this. Then, high concentration ion implantation is performed using the gate electrode 6 and the sidewall oxide films 15a and 15b as masks to form the high concentration implantation regions 4a and 4b, so that as shown in FIG. The asymmetric LDD structure in which the low concentration implantation region 3b is shorter than the low concentration implantation region 3a on the drain side is formed.
[0008]
[Problems to be solved by the invention]
Although the asymmetrical LDD structure formed by the above-described method can suppress hot carrier injection and reduce the ON resistance of the transistor in the source region, the above method is formed on the Si substrate 13. This is an effective manufacturing method for a MOS transistor, and it is difficult to apply it directly to a thin film transistor (TFT) formed on an active matrix substrate of a liquid crystal display device. The reason is that a glass substrate or the like is used as the liquid crystal display substrate, and therefore the glass substrate is also etched when the sidewall oxide film 15 made of a silicon oxide film is etched, and the heat resistant temperature of the glass substrate is taken into consideration. This is because the temperature during the manufacturing process must be suppressed to 550 ° C. or lower, and there is a problem that the semiconductor layer forming process is restricted.
[0009]
Therefore, for example, Japanese Patent Laid-Open No. 2-81439 describes a method of forming a silicide film on a gate electrode formed on a glass substrate via a gate insulating film and performing ion implantation using the silicide film as a mask. Yes. This method will be described with reference to FIG. 8. First, as shown in FIG. 8A, a semiconductor layer 2 is deposited on a glass substrate 1 by a low pressure CVD method or the like and processed into a predetermined shape by dry etching. Thereafter, a gate insulating film 5 is formed, and a gate electrode 6 made of polysilicon or the like is formed thereon. Thereafter, low concentration ions are implanted into the semiconductor layer 2 using the gate electrode 6 as a mask to form a low concentration implantation region 3.
[0010]
Next, as shown in FIG. 8B, after depositing a metal such as Ti on the surface of the gate electrode 6 by sputtering or the like, the metal film is silicided to form a sidewall made of the silicide film 16. . Thereafter, as shown in FIG. 8C, high concentration ion implantation is performed on the semiconductor layer 2 by using the gate electrode 6 and the silicide film 16 as a mask.
[0011]
However, in this method, the width of the offset region is determined by the silicide film 16 grown on the side wall of the gate electrode 6, but it is possible to accurately control the thickness of the metal film formed on the side wall of the gate electrode 6. In addition, since the silicide film 16 is formed symmetrically on both the left and right sides of the gate electrode 6, an asymmetric LDD structure cannot be formed. Further, when the method of forming the sidewalls by anisotropic etching after depositing the silicide film 16 is used instead of the method of forming the sidewalls by silicidation after depositing the metal film, it is anisotropic. Since the etching process is added, the manufacturing process becomes complicated.
[0012]
Further, when forming the storage capacitor portion together with the TFT on the active matrix substrate, high-concentration ion implantation must be performed also on the storage capacitor portion. It is necessary to add an injection process separately, which increases the number of processes.
[0013]
The present invention has been made in view of the above problems, and its main object is to provide an ion implantation process for forming a storage capacitor in a liquid crystal display substrate in which a TFT and a storage capacitor are formed on the same substrate. It is an object of the present invention to provide a liquid crystal display substrate having a TFT with an asymmetric LDD structure and a method of manufacturing the same, which can prevent a decrease in reliability due to carrier injection in the source region without adding a separate layer.
[0014]
[Means for solving problems]
In order to achieve the above object, the present invention includes a semiconductor layer in a thin film transistor region and a storage capacitor region provided on an insulating substrate, and the semiconductor layer of the thin film transistor region includes a low concentration injection region and a high concentration injection region. The source electrode side High-concentration region and the end of the gate electrode on the source electrode side Is the drain electrode side High-concentration region and the end of the gate electrode on the drain electrode side In the method of manufacturing a liquid crystal display substrate in which an asymmetric LDD structure shorter than the distance is formed and a high concentration injection region is formed in the semiconductor layer of the storage capacitor region, at least the semiconductor layer after the semiconductor layer is disposed High-concentration ion implantation into the thin film transistor region and the storage capacitor region at the same time using a resist pattern formed with a predetermined margin in the direction of both the source and drain electrodes in the gate electrode formation region as a mask through a sacrificial layer covering the gate electrode And removing the resist pattern and the sacrificial layer, and using the gate electrode formed through a gate insulating film covering at least the semiconductor layer as a mask, the thin film transistor with a higher implantation energy than the high concentration ion implantation Low concentration ion implantation is performed in a self-aligned manner in the region.
[0015]
The present invention also includes (a) a step of disposing a semiconductor layer made of low-temperature polysilicon in each of a thin film transistor region and a storage capacitor region on an insulating substrate, and (b) a sacrifice of a predetermined film thickness on the semiconductor layer. A step of depositing a layer; and (c) between a region for forming a gate electrode and a region for forming both source / drain electrodes in the thin film transistor region. Source electrode side is shorter than drain electrode side A step of forming a resist pattern that allows for a predetermined margin; and (d) using the resist pattern as a mask, high-concentration ion implantation is simultaneously performed on the thin film transistor region and the storage capacitor region, so that the semiconductor layer is shallow and high. A step of forming a concentration implantation region; (e) a step of depositing a gate insulating film having a predetermined thickness on the semiconductor layer after removing the resist pattern and the sacrificial layer; and (f) the thin film transistor region. Disposing a gate electrode on the gate insulating film and simultaneously disposing a counter electrode on the gate insulating film in the storage capacitor region; and (g) using the gate electrode as a mask, A low concentration ion implantation is performed in a self-aligned manner into the thin film transistor region at a higher energy than the implantation, and the semiconductor is covered so as to cover the high concentration implantation region. Forming a deep lightly doped implanted regions in the layer, the one having at least.
[0016]
In the present invention, when viewed from the normal direction of the insulating substrate, the margin expected in the resist pattern is the drain electrode direction. Desired low concentration implantation region distance In addition, the source electrode direction is preferably set equal to the lithography accuracy error.
[0017]
In the present invention, the sacrificial layer is formed with a thickness of 10 nm, the high-concentration ions are implanted from the surface of the semiconductor layer to a depth of 30 nm with an acceleration voltage of 10 keV to 30 keV, and the semiconductor layer is The low-concentration ions may be implanted to the bottom surface of the semiconductor layer with an acceleration voltage of 80 keV to 90 keV.
[0018]
The thin film transistor of the present invention includes a semiconductor layer on an insulating substrate, and a low concentration injection region and a high concentration injection region are formed in the semiconductor layer. , The distance of the low concentration implantation region on the source electrode side is shorter than the distance of the low concentration implantation region on the drain electrode side In the thin film transistor in which the LDD structure is formed, the semiconductor layer is formed with the high-concentration injection region shallowly spaced from the gate electrode by a predetermined distance in the source / drain electrode direction, and covers the high-concentration injection region. Thus, the low concentration implantation region is deep and formed so as not to overlap with the gate electrode.
[0019]
The liquid crystal display substrate of the present invention includes a semiconductor layer in a thin film transistor region and a storage capacitor region provided on an insulating substrate, and a low concentration injection region and a high concentration injection region are formed in the semiconductor layer. , The distance of the low concentration implantation region on the source electrode side is shorter than the distance of the low concentration implantation region on the drain electrode side In a liquid crystal display substrate having an LDD structure and having a high concentration injection region formed in the semiconductor layer of the storage capacitor region, the semiconductor layer of the thin film transistor region has a gate electrode extending from both the source and drain electrodes. The high concentration implantation region is shallowly spaced apart by a predetermined distance, the low concentration implantation region is deeply formed so as to cover the high concentration implantation region, and the high concentration implantation of the thin film transistor is formed in the storage capacitor region. A high concentration implantation region having the same ion implantation concentration and implantation depth as the region is formed.
[0020]
The liquid crystal display substrate of the present invention has a semiconductor layer made of low-temperature polysilicon in a thin film transistor region and a storage capacitor region provided on an insulating substrate, and the thin film transistor region and the semiconductor layer in the storage capacitor region have a semiconductor layer. Through the sacrificial layer in the direction of both the source and drain electrodes of the gate electrode formation region Source electrode side is shorter than drain electrode side Using a resist pattern formed with a predetermined margin as a mask, high-concentration implantation regions that are ion-implanted under the same conditions of ion implantation concentration and implantation depth are formed shallow, and are further formed in the semiconductor layer in the thin film transistor region. In this case, a low-concentration implantation region is formed deeply by ion implantation in a self-alignment manner with a higher energy than the high-concentration ion implantation, using a gate electrode formed through a gate insulating film as a mask.
[0021]
In the present invention, when viewed from the normal direction of the insulating substrate, the high concentration implantation region is a drain. electrode On the side Desired low concentration implantation region distance ± Lithography accuracy error is formed apart from the gate electrode, and the source electrode And does not overlap with the gate electrode, and the distance from the gate electrode is Shorter than the drain electrode side, It is preferably less than twice the accuracy error of lithography.
[0022]
In the present invention, the high concentration implantation region is formed to a depth of 30 nm from the surface of the semiconductor layer, and the low concentration implantation region covers the high concentration implantation region and reaches the bottom surface of the semiconductor layer. It can be configured.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
In a preferred embodiment of the method for manufacturing a liquid crystal display substrate according to the present invention, a semiconductor layer 2 made of low-temperature polysilicon is disposed in a thin film transistor region and a storage capacitor region provided on a glass substrate 1. Then, after depositing the sacrificial layer 7, a resist pattern 8 is formed in the gate electrode forming portion of the thin film transistor region so as to allow a predetermined margin on both sides of the source / drain of the gate electrode. After the high concentration ion implantation is simultaneously performed on the region and the storage capacitor region, the gate insulating film 5 and the gate electrode 6 are formed. By performing this ion implantation, it has an asymmetric LDD structure without adding an additional ion implantation step to the storage capacitor region. To form the FT.
[0024]
【Example】
In order to describe the above-described embodiment of the present invention in more detail, an example of the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional view showing a structure of a storage capacitor portion formed on the same substrate as a TFT in an active matrix substrate of a liquid crystal display device according to an embodiment of the present invention. 2 and 3 are plan views showing the layout of the TFT and the storage capacitor portion, FIG. 2 is an overall view of the pixel portion, FIG. 3A is a partially enlarged view of the pixel portion TFT, and FIG. ) Is a partially enlarged view of a circuit portion TFT formed around the pixel portion. FIG. 4 is a process cross-sectional view schematically showing a method for manufacturing an active matrix substrate, and FIG. 5 is a view showing the distribution of impurity concentration in the source / drain regions. In the following description, the pixel portion TFT shown in FIG. 3A is described, but a circuit portion TFT to which the storage capacitor portion 11 is not connected as shown in FIG. 3B is also formed using the same method. be able to.
[0025]
First, the structure of the TFT and the storage capacitor portion in the active matrix substrate of the liquid crystal display device of this embodiment will be described with reference to FIGS. 1 to 3. The active matrix substrate of this embodiment includes a gate line 9 and a drain line. Are formed so as to be orthogonal to each other, TFTs are arranged at the intersections, and each pixel surrounded by the gate line 9 and the drain line has a storage capacitor connected to the source / drain part 10 of the unit TFT. Part 11 is formed.
[0026]
Then, a semiconductor layer 2 made of low-temperature polysilicon is formed in the thin film transistor region and the storage capacitor region on the glass substrate 1, and a gate insulating film 5 made of a silicon oxide film or the like is deposited thereon so as to cover the semiconductor layer 2. Furthermore, a gate electrode 6 having a laminated structure of microcrystalline silicon 6a and tungsten silicide 6b is formed in the thin film transistor region, and a counter electrode 6c having the same structure is formed in the storage capacitor region. Here, low-temperature polysilicon is obtained by crystallizing Si by using a-Si as a precursor and applying crystallization energy by laser annealing, furnace annealing, or the like, and the final crystal structure becomes polycrystalline. By using this low-temperature polysilicon, the glass can be used in a temperature range (550 ° C. or lower) where glass can be used as a substrate throughout the entire process.
[0027]
The source / drain portion 10 of the TFT is provided with high concentration implantation regions 4a and 4b at the same time as the storage capacitor portion 11 at the same time as the storage capacitor portion 11, and the drain electrode side (right side in the figure) with the gate electrode 6 as the center. A low concentration implantation region 3a for forming LDD is formed on the source electrode side, and a low concentration implantation region 3b having a distance shorter than the LDD length is formed on the source electrode side (left side in the figure). The low concentration implantation regions 3a and 3b have a small concentration distribution in the depth direction and are deeply formed so as to cover the high concentration implantation regions 4a and 4b.
[0028]
A method of manufacturing a TFT having such an asymmetric LDD structure will be described with reference to FIG. First, as shown in FIG. 4A, a low-temperature polysilicon having a predetermined thickness is deposited on a glass substrate 1 by using a low pressure CVD method or the like, and a thin film transistor region is formed by using a known lithography technique and dry etching technique. The semiconductor layer 2 is formed in the storage capacitor region. If the semiconductor layer 2 is too thick, a leakage current due to light absorption increases, causing malfunction, and if it is too thin, it becomes difficult to activate a high concentration implantation region performed in a later step. However, in this embodiment, the film thickness is set to about 60 nm.
[0029]
Then, a silicon oxide film or the like to be the sacrificial layer 7 is deposited on the semiconductor layer 2 with a predetermined thickness by using a CVD method or the like. This sacrificial layer must be thinly formed so that the high concentration implantation regions 4a and 4b are formed only in the surface layer of the semiconductor layer 2 in the high concentration ion implantation performed in a later step. It is thinner than 5, for example, with a film thickness of about 10 nm.
[0030]
Next, as shown in FIG. 4B, using a known lithography technique, a photoresist pattern 8 larger than the gate electrode 6 is formed in a region where the gate electrode 6 is formed with a predetermined margin. Using the resist pattern 8 as a mask, high concentration ion implantation is performed on the source / drain portion 10 by an ion doping apparatus, and at the same time, high concentration ion implantation is performed on the storage capacitor portion 11. As described above, the process can be simplified by simultaneously performing the ion implantation for forming the source / drain regions of the TFT and the ion implantation for forming the storage capacitor.
[0031]
This high-concentration ion implantation is preferably performed as shallowly as possible in order to prevent activation failure due to the entire region of the semiconductor layer 2 becoming amorphous. For example, in this embodiment, the depth is About 20 to 30 nm. As ion implantation conditions in that case, for example, hydrogen diluted PH as impurity source gas _Three / (H ₂ + PH _Three ) = 0.05 to 0.15, acceleration voltage of about 10 to 30 keV, dose amount 1.0 × 10 ¹⁵ ~ 2.0 × 10 ¹⁵ / Cm ² It is preferable to carry out with.
[0032]
In addition, the resist pattern 8 formed in this step is larger than the gate electrode 6 to be formed later by an LDD length in order to form an LDD structure on the drain side, and the gate electrode 6 and the source side are formed on the source side. In order not to overlap with the high concentration implantation region 4b, it is formed with a margin so as to have an offset length that can absorb variations in lithography accuracy.
[0033]
For example, as shown in FIG. 1, the distance between the end portions of the high concentration implantation regions 4a and 4b of the source / drain portion 10 and the end portion of the gate electrode 6 is expressed as L on the source side. _S L on the drain side _D When the i-line is used as an exposure light source, the drain side margin of the resist pattern 8 is preferably set to 1.5 μm and the source side margin is preferably set to about 0.5 μm. _S , L _D Changes by the accuracy error of lithography (± 0.5 μm). _S = 0 to 1.0 μm, L _D = 1.0 μm to 2.0 μm.
[0034]
Then, after high-concentration ion implantation, the resist pattern 8 is removed by wet or dry etching, and the silicon oxide film used as the sacrificial layer 7 is etched using BHF or the like, as shown in FIG. A silicon oxide film or the like to be the gate insulating film 5 is deposited with a film thickness of about 90 nm using a CVD method or the like. Thereafter, microcrystalline silicon 6a and tungsten silicide 6b are deposited to a thickness of about 70 nm and 110 nm, respectively, using a low pressure CVD method or the like, and etched into a predetermined shape to form gate electrode 6 and counter electrode 6c.
[0035]
Next, as shown in FIG. 4D, low concentration ion implantation is performed in a self-aligned manner in the thin film transistor region using the gate electrode 6 as a mask. This low concentration ion implantation is performed, for example, with hydrogen diluted PH as an impurity source gas. _Three / (H ₂ + PH _Three ) = 0.15, acceleration voltage of about 80 to 90 keV, dose amount of 1.0 × 10 ¹³ ~ 1.5 × 10 ¹³ / Cm ² It is preferable to carry out under these conditions. Since the counter electrode 6 c is formed on the storage capacitor portion 11 with substantially the same width as that of the semiconductor layer 2, low concentration ion implantation is not performed on the storage capacitor portion 11.
[0036]
Here, it is important that this low concentration ion implantation is performed under a condition of higher energy than the high concentration ion implantation performed in the previous step, and thus, the low concentration implantation is also performed below the high concentration implantation regions 4a and 4b. Since the regions 3a and 3b are distributed and the distribution of the implanted impurity in the depth direction is broadened, variations in characteristics of the low-concentration implantation region 3b region and the LDD region on the source side can be suppressed. Reliability can be improved.
[0037]
Through the above steps, the low concentration implantation regions 3a and 3b are formed so as to cover the high concentration implantation regions 4a and 4b, and a TFT having the low concentration implantation regions 3a and 3b having asymmetric lengths at both ends of the gate electrode 6 is completed. To do. Here, the concentration of each impurity region is described as an example. In a TFT having a configuration in which the thickness of the semiconductor layer 2 is 60 nm and the thickness of the gate insulating film 5 is 90 nm, as shown in FIG. Region 4 is 5.0 × 10 5 at the interface between gate insulating film 5 and semiconductor layer 2. ²⁰ / Cm ² ~ 1.0 × 10 ^{twenty one} / Cm ² To the extent, 1.0 x 10 at 30 nm below the interface ¹⁷ / Cm ² Impurity concentration of about. On the other hand, the low concentration implantation region 3 is 6.0 × 10 6 at the interface between the gate insulating film 5 and the semiconductor layer 2. ¹⁷ / Cm ² ~ 9.0 × 10 ¹⁷ / Cm ² Degree, 5.0 × 10 at the interface with the glass substrate 1 ¹⁷ / Cm ² Impurity concentration of about.
[0038]
As described above, according to the manufacturing method of the TFT in the active matrix substrate of the liquid crystal display device of this embodiment, the manufacturing process is increased in order to simultaneously perform the high concentration ion implantation of the TFT and the high concentration ion implantation of the storage capacitor. Therefore, it is possible to form the LDD of the TFT and the storage capacitor.
[0039]
Further, when the low concentration implantation region 3b is formed on the source side, if the offset is not intentionally provided, the gate electrode 6 and the high concentration implantation region 4b overlap each other, so that the gate electrode 6 has a source side. Concentration of the electric field occurs, which causes deterioration of TFT characteristics, such as carrier injection into the oxide film. On the other hand, when the source side is simply offset, the ON resistance increases and the transistor performance also decreases. Resulting in. However, in this embodiment, the low-concentration implantation region 3b having a minimum length is provided in consideration of the lithography accuracy error, so that an increase in the ON resistance of the transistor is minimized and the electric field is reduced. Thus, deterioration of transistor characteristics can be suppressed.
[0040]
Furthermore, in this embodiment, since the low concentration ion implantation is performed with higher energy than the high concentration ion implantation, it is possible to reduce the variation of the impurity concentration distribution in the depth direction in both the low concentration implantation regions 3a and 3b. And variations in transistor characteristics can be suppressed.
[0041]
In the present embodiment, the manufacturing method of the pixel portion TFT in the active matrix substrate of the liquid crystal display device has been described as an example. However, the present invention is not limited to the above embodiment, and the high concentration implantation region 4 is shallow. Any MOS transistor in which the low-concentration implantation region 3 is deep and the concentration gradient is small, and the gate electrode 6 and the high-concentration implantation region 4b do not overlap on the source side and a minimum offset is formed, for example, FIG. It is clear that the present invention can be applied to a circuit part TFT to which the storage capacitor part 11 is not connected as shown in FIG. 5B and a MOS transistor formed on a semiconductor substrate. The material of the sacrificial layer 7 and the gate insulating film 5 is not limited to the silicon oxide film, and other materials such as a silicon nitride film that is usually used may be used.
[0042]
【Effect of the invention】
As described above, the liquid crystal display substrate and the manufacturing method thereof according to the present invention have the following effects.
[0043]
The first effect of the present invention is that a high-concentration ion implantation is performed first when forming an LDD structure of a TFT, and a high-concentration ion implantation of the TFT and an ion implantation for forming a storage capacitor portion are performed simultaneously. This means that the asymmetric LDD structure and the storage capacitor portion of the TFT can be formed without increasing the.
[0044]
The second effect of the present invention is that, at the stage of forming a high concentration implantation mask by photolithography, an offset capable of absorbing a lithography accuracy error is provided in advance, whereby the source end of the gate electrode and the high concentration implantation region are provided. Can be completely prevented, so that hot carrier injection in the source region can be suppressed, and low concentration ion implantation is also performed in the offset portion in a self-aligning manner using the gate electrode as a mask. That is, it is possible to minimize the deterioration of the transistor performance due to the low concentration implantation region and improve the reliability.
[0045]
The third effect of the present invention is that, by performing low concentration ion implantation under a high energy condition, the distribution of implanted impurities can be broadened, and variation in characteristics of the offset region can be suppressed. That is.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a structure of a TFT and a storage capacitor in an active matrix substrate of a liquid crystal display device according to an embodiment of the present invention.
FIG. 2 is an overall view showing a layout of TFTs and storage capacitors in an active matrix substrate of a liquid crystal display device according to an embodiment of the present invention.
FIG. 3 is a partially enlarged view showing a layout of TFTs and storage capacitors in an active matrix substrate of a liquid crystal display device according to an embodiment of the present invention.
FIG. 4 is a process cross-sectional view schematically showing a method for manufacturing a TFT on an active matrix substrate of a liquid crystal display device according to an embodiment of the present invention.
FIG. 5 is a diagram showing an impurity concentration in a depth direction in an LDD region of a TFT according to an embodiment of the present invention.
FIG. 6 is a diagram showing a structure of a MOSFET having a conventional symmetric LDD structure.
FIG. 7 is a diagram showing a structure of a MOSFET having a conventional asymmetric LDD structure.
FIG. 8 is a diagram showing a structure of a TFT having a symmetric LDD structure in an active matrix substrate of a conventional liquid crystal display device.
[Explanation of symbols]
1 Glass substrate
2 Semiconductor layer
3 Low concentration implantation region
3a Drain side low concentration implantation region
3b Source side low concentration implantation region
4 High concentration implantation area
4a Drain side high concentration implantation region
4b Source side high concentration implantation region
5 Gate insulation film
6 Gate electrode
6a Microcrystalline silicon
6b Tungsten silicide
6c Counter electrode
7 Sacrificial layer
8 resist pattern
9 Gate line
10 Source / drain section
11 Storage capacity section
12 channel section
13 Si substrate
14 Separation oxide membrane
15 Sidewall oxide film
15a Drain side sidewall oxide film
15b Source side sidewall oxide film
16 Silicide film

Claims (15)

A semiconductor layer is provided in a thin film transistor region and a storage capacitor region provided on an insulating substrate, and the semiconductor layer of the thin film transistor region includes a low concentration injection region and a high concentration injection region, and a high concentration region and a source on the source electrode side. An asymmetric LDD structure is formed in which the distance from the end of the gate electrode on the electrode side is shorter than the distance between the high concentration region on the drain electrode side and the end of the gate electrode on the drain electrode side, and the semiconductor layer in the storage capacitor region In a method for manufacturing a liquid crystal display substrate in which a high concentration injection region is formed,
After the semiconductor layer is disposed, the thin film transistor region and the thin film region are formed using, as a mask, a resist pattern formed with a predetermined margin in the source / drain electrode direction of the gate electrode formation region through at least a sacrificial layer covering the semiconductor layer. High concentration ion implantation is performed simultaneously with the storage capacitor region, and after removing the resist pattern and the sacrificial layer, using the gate electrode formed through a gate insulating film covering at least the semiconductor layer as a mask, the high concentration A method for manufacturing a substrate for a liquid crystal display, characterized in that low concentration ion implantation is performed in a self-aligned manner in the thin film transistor region with an implantation energy higher than that of ion implantation. (A) providing a semiconductor layer made of low-temperature polysilicon in each of the thin film transistor region and the storage capacitor region on the insulating substrate;
(B) depositing a sacrificial layer having a predetermined thickness on the semiconductor layer;
(C) forming a resist pattern between the region for forming the gate electrode of the thin film transistor region and the region for forming the source / drain electrodes, with a predetermined margin shorter on the source electrode side than on the drain electrode side;
(D) using the resist pattern as a mask, simultaneously performing high concentration ion implantation into the thin film transistor region and the storage capacitor region to form a shallow high concentration implantation region in the semiconductor layer;
(E) after removing the resist pattern and the sacrificial layer, depositing a gate insulating film having a predetermined thickness on the semiconductor layer;
(F) disposing a gate electrode on the gate insulating film in the thin film transistor region and simultaneously disposing a counter electrode on the gate insulating film in the storage capacitor region;
(G) Low-concentration ion implantation is performed in a self-aligned manner in the thin film transistor region with higher energy than the high-concentration ion implantation using the gate electrode as a mask, and the semiconductor layer is covered so as to cover the high-concentration implantation region. And a step of forming a low-concentration implantation region deeply in the substrate.   When viewed from the normal direction of the insulating substrate, the margin expected in the resist pattern is set such that the drain electrode direction is equal to the distance of the desired low concentration implantation region, and the source electrode direction is equal to the lithography accuracy error. A method for producing a liquid crystal display substrate according to claim 1.   4. The method of manufacturing a liquid crystal display substrate according to claim 3, wherein the margin in the drain electrode direction is set to 1.5 [mu] m and the margin in the source electrode direction is set to 0.5 [mu] m.   5. The sacrificial layer is formed with a thickness of 10 nm, and the high-concentration ions are implanted to a depth of 30 nm from the surface of the semiconductor layer with an acceleration voltage of 10 keV to 30 keV. A manufacturing method of a substrate for liquid crystal display given in one.   6. The semiconductor layer according to claim 1, wherein the semiconductor layer is formed to a thickness of 60 nm, and the low-concentration ions are implanted to the bottom surface of the semiconductor layer with an acceleration voltage of 80 keV to 90 keV. Manufacturing method of liquid crystal display substrate. The high concentration implantation region has a maximum impurity concentration of 10 ²¹ / cm ^{2 on} the surface of the semiconductor layer, an impurity concentration of 10 ¹⁶ / cm ² at a depth of 30 nm from the surface of the semiconductor layer, and the low concentration implantation region 7. The method according to claim 1, wherein ions are implanted under a condition that a difference in impurity concentration between the surface and the bottom surface of the semiconductor layer is 4.0 × 10 ¹⁷ / cm ² or less. The manufacturing method of the board | substrate for liquid crystal displays described in 2.   8. The method for manufacturing a liquid crystal display substrate according to claim 1, wherein the gate electrode is formed of a laminated film of microcrystalline silicon and tungsten silicide. A thin film transistor region and a storage capacitor region provided on an insulating substrate are provided with a semiconductor layer, and a low concentration injection region and a high concentration injection region are formed in the semiconductor layer, and the high concentration region on the source electrode side and the high concentration region on the source electrode side are formed. An asymmetric LDD structure in which the distance from the end of the gate electrode is shorter than the distance between the high concentration region on the drain electrode side and the end of the gate electrode on the drain electrode side, and the semiconductor layer in the storage capacitor region has a high concentration In a liquid crystal display substrate in which an injection region is formed,
In the semiconductor layer of the thin film transistor region, the high concentration implantation region is shallowly formed with a predetermined distance from the gate electrode in the source / drain electrode direction, and the low concentration implantation is formed so as to cover the high concentration implantation region. The region is deep and formed by ion implantation in a self-aligned manner using the gate electrode as a mask,
A substrate for liquid crystal display, wherein a high concentration implantation region having an ion implantation concentration and an implantation depth equal to those of the high concentration implantation region of the thin film transistor region is formed in the storage capacitor region. A thin film transistor region and a storage capacitor region provided on an insulating substrate have a semiconductor layer made of low-temperature polysilicon, and a gate electrode formation region is interposed in the semiconductor layer of the thin film transistor region and the storage capacitor region via a sacrificial layer High concentration implantation in which ions are implanted under the condition that the ion implantation concentration and the implantation depth are equal, using as a mask a resist pattern formed with a predetermined margin shorter on the source electrode side than the drain electrode side in both source / drain electrode directions Each region is formed shallower, and the semiconductor layer in the thin film transistor region has higher energy than ion implantation when forming the high concentration implantation region using a gate electrode formed through a gate insulating film as a mask. The low-concentration implantation region implanted in a self-aligned manner in FIG. Liquid crystal display substrate, characterized by being made. When viewed from the normal direction of the insulating substrate, the high concentration implantation region is formed on the drain electrode side so as to be separated from the gate electrode by a distance of a desired low concentration implantation region ± lithographic accuracy error, and on the source electrode side. 11. The liquid crystal according to claim 9, wherein the liquid crystal does not overlap with the gate electrode, and the distance from the gate electrode is shorter than the drain electrode side and is not more than twice the accuracy error of lithography. Display substrate. The distance between the high concentration implantation region on the drain side and the gate electrode is 1.0 μm to 2.0 μm, and the distance between the high concentration implantation region on the source side and the gate electrode is 1.0 μm or less. The substrate for liquid crystal display according to claim 11. The high concentration implantation region is formed to a depth of 30 nm from the surface of the semiconductor layer, and the low concentration implantation region covers the high concentration implantation region and reaches the bottom surface of the semiconductor layer. The liquid crystal display substrate according to any one of 9 to 12. The high concentration implantation region is 10 on the surface of the semiconductor layer. ^{twenty one} / Cm ² The maximum impurity concentration is 10 nm at a depth of 30 nm from the surface of the semiconductor layer. ¹⁶ / Cm ² The low-concentration implanted region has an impurity concentration difference of 4.0 × 10 4 between the surface and the bottom surface of the semiconductor layer. ¹⁷ / Cm ² The liquid crystal display substrate according to claim 9, wherein the substrate is a liquid crystal display substrate. 15. The liquid crystal display substrate according to claim 9, wherein the gate electrode includes a laminated film of microcrystalline silicon and tungsten silicide.

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