JP4718169B2 - CMOS imaging device circuit - Google Patents

Description

  The present invention relates to a CMOS imaging device circuit.

  Conventionally, MOS-type imaging devices have been used to acquire various image data. This type of imaging device reads out the electric charge accumulated in the pn junction capacitance of the photo diode through a MOS transistor (for example, a field effect transistor (FET)).

  In general, it is said that an imaging device such as a MOS type has a narrow latitude, that is, a dynamic range, compared to a negative film used for photographing. The narrow latitude means that the dark part of the image is recorded as black pixel data, and the bright part of the image is recorded as white pixel data.

As a technique for expanding the dynamic range, there is a logarithmic conversion type imaging device (see, for example, Patent Document 1 and Non-Patent Document 1). For example, in the image cell disclosed in Patent Document 1, a light receiving element is connected between one terminal of a first MOS transistor and a gate terminal of a second MOS transistor, and the other terminal of the first MOS transistor. Is connected to one electrode of a voltage supply source. Then, logarithmic conversion is performed in the image cell by the first MOS transistor operating in the sub-threshold region, and the conversion result is output.
US Pat. No. 5,608,204 The Journal of the Video Media Society, Vol. 54, no. 2, pp. 224, 2000

  However, in the imaging devices disclosed in Patent Document 1 and Non-Patent Document 1 described above, charges generated in the photo diode are accumulated, and the charges are generated in the photo diode of the image cell arranged adjacently. Crosstalk due to so-called charge interference that affects the charge is a problem. In particular, when there is a large difference in contrast (contrast) as in night photography, and the bright point moves, there is a problem that image resolution is deteriorated and image quality is lowered.

  An object of the present invention is to reduce charge interference between adjacent image cells.

A CMOS imaging device circuit according to the present invention is a CMOS imaging device circuit having an image cell connected to an intersection of a row selection line and a column signal line on the surface of a one-conductivity type semiconductor substrate, wherein the image cell is connected in series. A logarithmic conversion unit that generates a photoelectric conversion signal having a logarithmic characteristic according to the amount of incident light by operating the first transistor in a sub-threshold region. A signal amplifying unit that amplifies the converted signal and outputs the amplified signal to the column signal line, the signal amplifying unit having a gate terminal connected to a sense node between the light receiving element and the first transistor, and a source terminal Has a second transistor connected to the first power supply, a gate terminal connected to the row selection line, a first terminal connected to the second transistor, and a second terminal A third transistor connected to the column signal line and contacting and separating the second transistor and the column signal line in response to a drive signal supplied via the row selection line; Is constituted by a transistor having a reverse conductivity channel type with respect to the first transistor, the image cell is formed in a rectangular region, the light receiving element is provided in the center of the image cell, and any of the apexes of the image cell The first transistor is provided, and the second transistor and the third transistor are provided at the vertices of the vertices where the first transistor is provided, and the light receiving element and the first transistor are is formed on the first conductivity type semiconductor substrate opposite conductivity type in the well provided for each pixel, the well and the first transistor receiving element is formed is formed U Thereby forming a Le as a continuous one well, in the well are those transistors constituting the signal amplifying section is not formed. Note that the semiconductor substrate includes not only a single substrate but also a substrate in which an epitaxial layer or the like is formed on the surface, and a substrate in which a semiconductor layer such as a single crystal is formed on the surface of an insulating substrate.

  According to the present invention, since the light receiving element and the first transistor are formed in the reverse conductivity type well provided for each pixel in the one conductivity type semiconductor substrate, the accumulated charge generated by the received light is generated in the adjacent image cell. Since the effect on the stored charge is reduced, charge interference between adjacent image cells is reduced.

In addition, since the photoelectric conversion signal is amplified and output to the column signal line in the image cell, when the image cell is formed with a predetermined area, the area of the light receiving element increases as the number of transistors decreases. The ratio of the area of the light receiving element to the area of is increased. As a result, the amount of current (photocurrent) flowing through the light receiving element is increased with respect to the same amount of received light as compared with an image cell having a large number of transistors, and the S / N ratio (signal-to-noise ratio) at the sense node is increased. Improved. In the amplifier circuit that receives the output signal of the image cell, the amplification factor can be increased and the sensitivity can be increased.
Furthermore, since a well can be formed and a transistor constituting a signal amplifying portion can be formed in a region having a conductivity type opposite to that of the well, there is no need to form a well for the transistor, and the well is formed. In comparison, the area of the light receiving element can be increased to improve the sensitivity.

In one aspect of the present invention, the signal amplifier further includes a gate terminal connected to a reset line, a first terminal connected to the sense node, a second terminal connected to a second power source, and the reset And a fourth transistor for connecting and disconnecting the sense node and the second power source in response to a reset signal supplied via the line. The light receiving element generates a photocurrent when irradiated with light, and the impedance is lowered. However, when the photocurrent is low at a low illuminance, the sense node holds an intermediate potential and causes an afterimage. Since the fourth transistor resets the sense node to the level of the second power supply by the reset signal, the afterimage problem is solved and high-quality and high-sensitivity imaging is realized.
In one embodiment of the present invention, the semiconductor substrate has an epitaxial layer formed on a surface thereof, and between the adjacent wells, one conductivity type well having a reverse conductivity type with respect to the well is provided in the epitaxial substrate. It is provided to reach the layer.

  As described above, according to the present invention, charge interference between adjacent image cells can be reduced.

Hereinafter, an embodiment embodying the present invention will be described with reference to FIGS.
FIG. 5 is a schematic block circuit diagram of the solid-state imaging device.
The solid-state imaging device 10 includes an imaging unit 11, an internal clock generation circuit 12, a vertical scanning circuit 13, a horizontal scanning circuit 14, and an output circuit 15.

The imaging unit 11 includes a plurality of image cells Ca arranged in a matrix. FIG. 5 shows image cells Ca arranged in a matrix of m rows and n columns.
The internal clock generation circuit 12 receives the clock signal Φ0 and generates a vertical clock signal Φw and a horizontal clock signal Φt based on the clock signal Φ0.

  The vertical scanning circuit 13 is a vertical shift register, and is connected to row selection lines W1 to Wm and reset lines R1 to Rm that are paired with the row selection lines W1 to Wm. The horizontal scanning circuit 14 includes a plurality of (four in FIG. 5) amplifier circuits 16 and a shift register 17, to which column signal lines BL1 to BLn are connected. An image cell Ca is connected to intersections of the row selection lines W1 to Wm and the column signal lines BL1 to BLn. Each image cell Ca is connected to reset lines R1 to Rm that are paired with row selection lines W1 to Wm.

  The vertical scanning circuit 13 sequentially drives the row selection lines W1 to Wm based on the vertical clock signal Φw. The image cells Ca connected to the row selection lines W1 to Wm output photoelectric conversion signals to the column signal lines BL1 to BLn in response to drive signals supplied via the row selection lines W1 to Wm.

  Each of the column signal lines BL1 to BLn is connected to the amplifier circuit 16 constituting the horizontal scanning circuit 14. Each amplifying circuit 16 includes an amplifying unit that amplifies photoelectric conversion signals input via the column signal lines BL1 to BLn, and an analog-digital (A / D) converting unit that converts an output signal of the amplifying unit into a digital signal. including.

The shift register 17 constituting the horizontal scanning circuit 14 transfers the digital signal output from the amplifier circuit 16 to the output circuit 15 based on the horizontal clock signal Φt.
The output circuit 15 generates and outputs an output signal out obtained by extending the pulse width of the signal output from the horizontal scanning circuit 14.

Next, the configuration of the image cell will be described.
FIG. 1 shows an image cell Ca connected to the intersection of the row selection line W1 and the column signal line BL1.
The image cell Ca includes a logarithmic conversion unit 21 and a signal amplification unit 22. The logarithmic converter 21 includes a photodiode PD. The photodiode PD has an anode connected to the first transistor T1 having a one-conductive channel type and a cathode connected to the high potential power supply Vdd. In the present embodiment, the first transistor T1 is a P-channel MOS transistor. The first terminal (source terminal) is connected to the photodiode PD, and the second terminal (drain terminal) and the gate terminal are low-potential power supplies (mains). In the embodiment, it is connected to the ground GND). Further, the photodiode PD and the first transistor T1 are formed in a well 23 (n-well in this embodiment) having a conductivity type opposite to that of the first transistor T1.

  A sense node N1 that is a connection point between the photo diode PD and the first transistor T1 is connected to the signal amplifier 22. The signal amplifying unit 22 includes a plurality (three in this embodiment) of transistors T2, T3, and T4. Each of the transistors T2 to T4 is a reverse conductive channel type, that is, an N-channel type MOS transistor with respect to the first transistor T1. Therefore, the logarithmic conversion unit 21 including the photodiode PD and the first transistor T1 is formed in an n-well having the same conductivity type as the transistors T2 to T4 constituting the signal amplification unit 22.

  The second transistor T2 is an amplifying transistor, the gate terminal is connected to the sense node N1, the source terminal is connected to the ground GND as the first power supply, and the drain terminal is connected to the third transistor T3. The second transistor T2 outputs a signal obtained by amplifying the potential of the sense node N1.

  The third transistor T3 is a row selection transistor, and a first terminal (for example, a source terminal) is connected to the second transistor T2, and a second terminal (for example, a drain terminal) is connected to the column signal line BL1. The third transistor T3 has a gate terminal connected to the row selection line W1, and a drive signal Φw1 described later is applied to the gate terminal via the row selection line W1. The third transistor T3 is turned on / off in response to the drive signal Φw1 supplied via the row selection line W1, and connects and disconnects the second transistor T2 and the column signal line BL1. Therefore, when the third transistor T3 is turned on, a signal (photoelectric conversion signal) output from the second transistor T2 is output to the column signal line BL1.

  The fourth transistor T4 is a reset transistor for the sense node N1, the source terminal is connected to the ground GND as the second power supply, the drain terminal is connected to the sense node N1, and the back gate terminal is connected to the ground GND. Yes. The fourth transistor T4 has a gate terminal connected to the reset line R1, and a reset signal Φr1 described later is applied to the gate terminal via the reset line R1. The fourth transistor T4 connects and disconnects the sense node N1 and the ground GND in response to the reset signal Φr1.

The image cell Ca configured in this manner operates according to the potentials of the row selection line W1 and the reset line R1.
The potential of the row selection line W1 is supplied from the vertical scanning circuit 13, and the waveform thereof is substantially the same as that of the vertical clock signal Φw. Here, a signal having a potential supplied to the row selection line W1 is Φw1. As shown in FIG. 6, the drive signal Φw1 has a trapezoidal waveform in which a rising edge and a falling edge are smoothed by a predetermined time constant. For example, the vertical scanning circuit 13 generates the drive signal Φw1 so as to have a rising width tr and a falling width tf that are 10 to 20 percent of the pulse width tk. Further, the vertical scanning circuit 13 generates the drive signal Φw1 so that the L level is the ground GND level and the H level is the high potential power supply Vdd level. Further, the vertical scanning circuit 13 generates a reset signal Φr1 that is at the H level for a predetermined period tr after the drive signal Φw1 falls.

  The photo diode PD passes a photocurrent according to the amount of incident light, the first transistor T1 operates in the sub-threshold region by the photocurrent, and the logarithmically converted voltage is applied to the second transistor T2. Applied to the gate terminal. The fourth transistor T4 outputs a signal obtained by amplifying the voltage applied to the gate terminal. The third transistor T3 is turned on in response to the H-level drive signal Φw1, and a signal is output to the column signal line BL1 through the third transistor T3 that is turned on.

  After the drive signal Φw1 becomes L level and the third transistor T3 is turned off, the reset signal Φr1 rises to H level. Then, the fourth transistor T4 to which the reset signal Φr1 is supplied to the gate terminal is turned on. Since the fourth transistor T4 is an N-channel MOS transistor, the potential of the drain terminal can be made equal to the source terminal potential. That is, the fourth transistor T4 that is turned on sets the sense node N1 to which the drain terminal is connected to the potential of the ground GND. As a result, the potential of the sense node N1 is reset to the ground GND level (dark reset).

  Smoothing the waveform of the drive signal Φw1 prevents noise generation. That is, when the potential of the drive signal Φw1 is suddenly raised, the first transistor T1 operates suddenly, so that noise such as ringing occurs in the photocurrent. Similarly, noise is generated when the potential of the drive signal Φw1 is suddenly lowered. For this reason, the noise is suppressed by smoothing the rise and fall of the drive signal Φw1.

  The amplifier circuit 16 shown in FIG. 5 amplifies the signal read out to the column signal line BL1, samples it based on the horizontal clock signal Φt, and performs A / D conversion. As shown in FIG. 6, the timing of the horizontal clock signal Φt is set so as to be sampled when a sufficient photocurrent is generated in the photodiode PD.

  Then, the shift register 17 transfers the output signal of the amplifier circuit 16 to the output circuit 15, and the output circuit 15 expands the pulse width of the input signal to a predetermined pulse width (width tk in this embodiment). And output it.

FIG. 3 is a plan view showing a partial layout of the imaging unit 11.
The imaging unit 11 includes a plurality of image cells Ca arranged adjacent to each other. Each image cell Ca is formed in a rectangular area partitioned by a two-dot chain line in FIG. The plurality of image cells Ca are arranged at equal intervals in the vertical direction (vertical direction in the figure) and the horizontal direction (horizontal direction in the figure). That is, each image cell Ca is formed in a square area. Note that the image cells Ca may be formed in a rectangular area, that is, the arrangement intervals in the vertical direction and the horizontal direction may be different.

  On the boundary between adjacent image cells Ca, a power supply wiring is formed so as to extend along the boundary line. More specifically, every other plurality of first power supply wirings V1 extending along the horizontal direction are arranged on the boundary between the image cells Ca adjacent in the vertical direction. The first power supply wirings V1 are arranged in such a manner that the vertical intervals between the centers of the first power supply wirings V1 are the lengths of the image cells Ca. The first power supply wiring V1 is disposed on the boundary between two image cells Ca adjacent in the vertical direction.

  On the boundary between the image cells Ca adjacent in the horizontal direction, the second power supply wiring V2 and the third power supply wiring V3 extending along the vertical direction are alternately arranged in the horizontal direction. That is, the first power supply wiring V1 and the second power supply wiring V2 are formed so as to extend along directions orthogonal to each other. The first power supply wiring V1 and the third power supply wiring V3 are formed so as to extend along directions orthogonal to each other.

  The first power supply wiring V1 and the second power supply wiring V2 are wirings for supplying a low potential power supply (ground GND) to each image cell Ca, and the third power supply wiring V3 is a high potential power supply Vdd to each image cell Ca. It is wiring for supplying.

  On both sides (upper and lower sides in FIG. 3) of each first power supply line V1, reset lines R are formed so as to extend along each first power supply line V1. In the imaging unit 11, a row selection line W extending in the horizontal direction is formed along a boundary where the first power supply wiring V1 is not provided. That is, in the imaging unit 11, a first set including the first power supply wiring V <b> 1 and the two reset lines R and a second set including the two row selection lines W are alternately arranged in the vertical direction. Has been.

  Column signal lines BL are formed on both sides of each third power supply wiring V3 (on the left and right sides in FIG. 3) so as to extend along each second power supply wiring V2. That is, in the imaging unit 11, a third set of the second power supply wiring V2 and a fourth set of the third power supply wiring V3 and the two column signal lines BL are alternately arranged in the horizontal direction. ing.

  Each image cell Ca is connected to a reset line R, a row selection line W, and a column signal line BL arranged on each region. Further, each image cell Ca is connected to first to third power supply wirings V1 to V3 disposed on the respective boundaries.

FIG. 2 is a partially enlarged view of FIG. In FIG. 2, the power supply wirings V1 to V3, the row selection line W, the column signal line BL, and the reset line R shown in FIG. 3 are omitted.
For the image cell Ca constituting the imaging unit 11, an N well 31 is formed in the center of each image cell Ca, and a photodiode PD is formed in the N well 31.

The rectangular area in which the image cell Ca is formed has four vertices O1 to O4. In FIG. 2, O1, O2, O3, and O4 are clockwise from the top left vertex.
A substantially rectangular N well 32 centered on the vertex O1 is formed at the first vertex O1, and a first transistor T1 is formed in the N well 32. The first transistor T1 includes a drain region 41 and a source region 42 arranged along the row selection line W shown in FIG. 3 (along the horizontal direction in FIG. 2), and between the drain region 41 and the source region 42. The gate wiring 43 is formed and extends along a direction (vertical direction in FIG. 2) perpendicular to the row selection line W. The source region 42 is formed continuously with the source region 42 constituting the first transistor T1 of the image cell Ca adjacent in the horizontal direction, and is connected to the first power supply wiring V1. The four transistors T1 formed around the first vertex O1 are electrically connected to the gate wiring 43 and to the first power supply wiring V1.

  The first transistor T1 is formed so that a part of its drain region 41 overlaps with the photodiode PD. Therefore, the N wells 31 and 32 in which the photodiode PD and the first transistor T1 are respectively formed are continuously formed to constitute one N well.

  The second and fourth vertices O2 and O3 formed at both ends of one side are formed with second to fourth transistors T2 to T4, which are transistors of a reverse conductivity channel type with respect to the first transistor T1. More specifically, a fourth transistor T4 is formed at the second vertex O2, and a second transistor T2 and a third transistor T3 are formed at the third vertex O3.

  At the fourth vertex O4, a well region having the same conductivity type as the well in which the photodiode PD is formed, that is, an N well 33 is formed. The N well 33 is formed in an octagonal shape centered on the vertex O4. The N well 33 is formed continuously with the other N wells 31 and 32 to constitute one N well. The N well 33 is connected to the second power supply wiring V2. Accordingly, the voltage of the high potential power supply Vdd is applied to the N wells 31 and 32 in which the photodiode PD and the first transistor T1 are formed via the second power supply wiring V2.

  As shown in FIG. 3, adjacent image cells Ca are formed with line symmetry with the boundary line (horizontal direction, vertical direction) of each other as the axis of symmetry. Accordingly, four image cells Ca are formed around the first vertex O1, and the center point of the transistor group including the first transistors T1 included therein is formed so as to coincide with the first vertex O1. The four first transistors T1 thus formed are connected to one first power supply wiring V1 (or second power supply wiring V2). Accordingly, the four first transistors T1 are easily connected to one first power supply wiring V1.

  Similarly, the center point of the transistor group including the fourth transistors T4 included in the four image cells Ca formed around the second vertex O2 is formed so as to coincide with the second vertex O2, and the four fourth transistors T4 are formed. Are easily connected to the first power supply wiring V1. Further, the center point of the transistor group including the third and fourth transistors T3 and T4 included in the four image cells Ca formed around the third vertex O3 is formed so as to coincide with the third vertex O3. The transistor T2 is easily connected to the third power supply wiring V3.

  FIG. 4 is a cross-sectional view of a chip 50 that is the solid-state imaging device 10. A chip 50 as a one-conductivity type semiconductor substrate includes a P-type silicon substrate 51 and a P-type epitaxial layer 52 formed thereabove. An N well 53 is formed in the P type epitaxial layer 52. The N well 53 structurally shows the N wells 31, 32, 33 in FIG. 2, and the N well 23 in FIG. A P well 54 is formed between adjacent N wells 53. The P well 54 is formed so as to reach the P-type epitaxial layer 52 and reaches a deeper position than an element isolation region such as LOCOS generally used in the prior art.

  A P-type region 55 is formed in the N well 53 from its upper surface to a predetermined depth. An N-type region 56 is formed in the P-type region 55 so as to substantially cover the upper surface thereof, and the N-type region 56 is electrically connected to the N-well 53. The P-type region 55 and the N-type region 56 constitute a photodiode PD. The voltage of the high potential power supply Vdd is applied to the N well 53, that is, the N wells 31, 32, and 33 shown in FIG.

  Further, P-type regions 57 and 58 are formed in the N well 53 from the upper surface to a predetermined depth. A gate wiring 59 is formed above the P-type regions 57 and 58, and the gate transistor 59 and the P-type regions 57 and 58 constitute a first transistor T1. The P-type region (drain region) 58 constituting the first transistor T1 is formed so as to overlap with the P-type region 55 constituting the photodiode PD.

  When the charge generated at the PN junction of the photo diode PD flows as a photocurrent, each photo diode PD is formed in the N well 53, and therefore, between the photo diodes PD formed in each N well 53. Interference is prevented, that is, crosstalk is prevented. Further, since the P well 54 between the N wells 53 is formed deeper than the conventional element isolation, mutual interference between adjacent photodiodes PD is prevented as shown in FIG.

As described above, according to the present embodiment, the following effects can be obtained.
(1) The logarithmic conversion unit 21 of the image cell Ca includes a photodiode PD and a one-conductive channel type first transistor T1 connected in series, and the photodiode PD and the first transistor T1 are connected to the first transistor. It was formed in a well 23 having a conductivity type opposite to that of T1. Accordingly, since the accumulated charge generated by the received light is reduced from affecting the accumulated charge of the adjacent image cell Ca, the charge interference between the adjacent image cells can be reduced.

  (2) The signal amplifying unit 22 includes a second transistor T2 and a third transistor T3. The second transistor T2 has a gate terminal connected to the sense node N1, and a source terminal connected to the ground GND. The third transistor T3 has a gate terminal connected to the row selection line W1, a first terminal connected to the second transistor T2, a second terminal connected to the column signal line BL1, and is supplied via the row selection line W1. The second transistor T2 is connected to and separated from the column signal line BL1 in response to the drive signal Φw1. Therefore, since the photoelectric conversion signal is amplified and output to the column signal line BL1 in the image cell Ca, when the image cell Ca is formed with a predetermined area, the area of the photodiode PD increases as the number of transistors decreases. That is, the ratio of the area of the photodiode PD to the area of the image cell is increased. As a result, the amount of current (photocurrent) flowing through the photodiode PD is increased with respect to the same amount of received light as compared with an image cell having a large number of transistors, and the S / N ratio (signal-to-noise ratio) at the sense node is increased. ) Is improved. In the amplifier circuit that receives the output signal of the image cell, the amplification factor can be increased and the sensitivity can be increased.

  (3) The signal amplifier 22 further includes a fourth transistor T4 having a gate terminal connected to the reset line R1, a first terminal connected to the sense node N1, and a second terminal connected to the ground GND. The fourth transistor T4 connects and disconnects the sense node N1 and the ground GND in response to a reset signal Φr1 supplied via the reset line R1. The photo diode PD generates a photocurrent when irradiated with light and its impedance is lowered. However, when the photocurrent is low at low illuminance, the sense node N1 holds an intermediate potential and causes an afterimage. Since the fourth transistor T4 resets the sense node N1 to the ground GND level by the reset signal Φr1, the afterimage problem is solved and high-quality and high-sensitivity imaging is realized.

  (4) The signal amplifying unit 22 includes the first transistor T1 and the reverse conductivity channel type transistors T2 to T4. That is, the transistors T2 to T4 constituting the signal amplification unit 22 are transistors having the same conductivity type as the well 23 in which the photodiode PD and the first transistor T1 are formed. Therefore, since the well 23 is formed and the transistors T2 to T4 constituting the signal amplifying unit 22 can be formed in a region having a conductivity type opposite to that of the well 23, element isolation of each of the transistors T2 to T4 becomes unnecessary. It is not necessary to form wells for these transistors, and the area of the photodiode PD can be increased as compared with the case where the wells are formed, and sensitivity can be improved.

In addition, you may implement each said embodiment in the following aspects.
In the above embodiment, the first transistor T1 made of a P-channel MOS transistor is connected to the photo diode PD, and the photo diode PD and the first transistor T1 are formed in the N well 23 (53). This may be formed in a P-well by connecting an N-channel MOS transistor to the photodiode PD. In this case, the transistor is connected between the photodiode PD and the high potential power supply Vdd. Even if comprised in this way, the interference between image cells can be prevented.

  In the above embodiment, the so-called CMOS type image cell Ca in which the first transistor T1 of the logarithmic conversion unit 21 and the second to fourth transistors T2 to T4 constituting the signal amplification unit 22 are transistors of opposite conductivity type to each other. However, the image cell may be composed of transistors having the same conductivity type.

  In the above embodiment, the sense node N1 may be reset to the high potential power supply Vdd level. At this time, the fourth transistor T4 shown in FIG. 1 may be connected between the sense node N1 and the high potential power supply Vdd to reset the sense node N1. Alternatively, a P-channel MOS transistor may be connected between the high potential power supply Vdd and the sense node N1, and the transistor may be driven by a signal obtained by inverting the reset signal Φr1.

  In the above embodiment, the image cell Ca is formed on the chip 50 having the epitaxial layer 52 on the silicon substrate 51 as the one-conductivity type semiconductor substrate. However, the silicon substrate itself is formed as the semiconductor substrate, and a single crystal or the like is formed on the surface of the insulating substrate. A substrate that has been used may be used. Alternatively, a substrate formed by bonding may be used.

  In the above embodiment, the drive signal Φw1 of the image cell Ca is made to rise and fall, but at least the rise may be made slow.

It is a circuit diagram showing an image cell of one embodiment. It is a top view which shows the layout of an image cell. It is a top view which shows a part layout of an imaging part. It is a partial cross section figure of the chip in which the image cell was formed. It is a block circuit diagram of a solid-state imaging device. It is a wave form diagram which shows operation | movement of a solid-state imaging device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 21 ... Logarithmic conversion part, 22 ... Signal amplification part, 23 ... Well, 50 ... Chip | tip as a semiconductor substrate, Ca ... Image cell, R, R1-Rm ... Reset line, W, W1-Wm ... Row selection line, BL, BL1 to BLn ... column signal line, N1 ... sense node, T1 ... first transistor, T2 ... second transistor, T3 ... third transistor, T4 ... fourth transistor, [Phi] r1 ... reset signal, [Phi] w1 ... drive signal.

Claims (3)

A CMOS imaging device circuit comprising an image cell connected to the intersection of a row selection line and a column signal line on the surface of a one-conductive semiconductor substrate,
The image cell includes a light-receiving element connected in series and a first transistor of one conductivity channel type, and operates the first transistor in a sub-threshold region to generate a photoelectric conversion signal having logarithmic characteristics according to the amount of incident light. A logarithmic conversion unit, and a signal amplification unit that amplifies the photoelectric conversion signal and outputs the amplified signal to the column signal line,
The signal amplifier includes a second transistor having a gate terminal connected to a sense node between the light receiving element and the first transistor, a source terminal connected to a first power supply, and a gate terminal connected to the row selection line. , A first terminal connected to the second transistor, a second terminal connected to the column signal line, and in response to a drive signal supplied via the row selection line, the second transistor and the A third transistor for contacting and separating the column signal line,
The signal amplifying unit is composed of a transistor having a reverse conductivity channel type with respect to the first transistor,
The image cell is formed in a rectangular area,
The light receiving element is provided at the center of the image cell, the first transistor is provided at one of the apexes of the image cell, and the second transistor is provided at the apex of the diagonal of the apex provided with the first transistor. And the third transistor is provided,
The light receiving element and the first transistor are formed in a reverse conductivity type well provided for each pixel on the one conductivity type semiconductor substrate ,
The well in which the light receiving element is formed and the well in which the first transistor is formed are formed as one continuous well, and the transistor constituting the signal amplification unit is not formed in the well. A characteristic CMOS imaging device circuit. The signal amplifier further includes a gate terminal connected to a reset line, a first terminal connected to the sense node, a second terminal connected to a second power supply, and a reset supplied via the reset line. The CMOS imaging device circuit according to claim 1, further comprising a fourth transistor that connects and disconnects the sense node and the second power supply in response to a signal. The semiconductor substrate has an epitaxial layer formed on the surface thereof, and between the adjacent wells, one conductivity type well having a reverse conductivity type with respect to the well is provided so as to reach the epitaxial layer. The CMOS image pickup device circuit according to claim 1 , wherein the CMOS image pickup device circuit is provided.

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