JP4758871B2 - Wiring method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring method of a semiconductor device for automatically wiring a CoP (Chip on a Package) or a PoP (Package on a Package). <P>SOLUTION: The wiring method comprises: a first step for setting the positions of bond fingers 6b or terminals of a second semiconductor chip 6 on a sealing material 5, and the positions of holes penetrating from the top surface 5a of the sealing material 5 to the top surface 1b or the bottom surface 1a of a substrate 1; a second step for allocating a net between the bond fingers 6b or terminals and the through holes 9; a third step for changing the positions of the through holes 9 of one net allocated between the bond fingers 6b or terminals and the through holes 9 so as to be positions that do not intersect the other nets with respect to an intersection net; and a fourth step for setting a grid value from a start point to a target point by a maze method while defining the bond fingers 6b or terminals as the start point and a through hole 9 corresponding to the start point as the target point referring to the nets to perform backtrace processing to form the wiring path of the net. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

  The present invention relates to a wiring method of a semiconductor device, and more particularly, a system in a package (hereinafter referred to as SiP) in which a plurality of semiconductor chips and soldered parts are contained in a single package and sealed as a single system. Chip on package (hereinafter referred to as CoP) on which a circuit element or a semiconductor chip is mounted, or package on package (hereinafter referred to as CoP) on which another SiP is mounted. , Referred to as PoP).

In a conventional semiconductor integrated circuit device, an area array electrode is provided on the lower surface, a wiring board having an electrode pad electrically connected to the area array electrode on the upper surface, and flipped with respect to the electrode pad on the upper surface of the wiring board An RF chip connected by chip bonding, a semiconductor chip stacked on the RF chip and connected to the wiring board using an electrical connection means, the RF chip, the semiconductor chip, and the electrical connection And a sealing resin that seals the upper surface region of the wiring board including the means (see, for example, Patent Document 1).
JP 2005-303056 A (3rd page, 38th line-4th page, 27th line, FIG. 1)

  A conventional semiconductor integrated circuit device is not a device in which a circuit element or a semiconductor chip is mounted on a SiP (CoP), and does not effectively use a vacant space on the SiP. In particular, since there is no system that automatically performs optimum wiring design and layout design for CoP, the wiring designer examines the three-dimensional arrangement of circuit elements or semiconductor chips on the SiP and performs wiring manually. There is no effective means other than this, and this manual operation has a problem that it takes time and lacks accuracy and reliability.

  The present invention has been made to solve the above-described problems, and can automatically perform wiring in a PoP on which a circuit element or a semiconductor chip is mounted on a SiP or another SiP on a SiP. A wiring method of a semiconductor device is provided.

  In the wiring method of the semiconductor device according to the present invention, the substrate on which the external terminals are disposed, the first semiconductor chip mounted on the upper surface of the substrate, and sealing the first semiconductor chip on the substrate In the wiring method of the semiconductor device comprising the sealing material, the position of the connection terminal of the circuit element or the second semiconductor chip mounted on the sealing material and the top surface of the substrate from the top surface of the sealing material or A first step of setting a position of a through hole penetrating to the lower surface; and a connection terminal between the circuit element or the second semiconductor chip and the through hole, or a connection terminal of the circuit element and the second semiconductor chip. A second step of assigning nets between connection terminals, and a plurality of nets assigned in the second step, and there are crossing nets among the plurality of nets. Among the nets that intersect, at least one net is a net allocated between the connection terminal of the circuit element or the second semiconductor chip and the through hole, and the position of the through hole in the one net A third step of changing the net of the circuit so as not to cross the other net, and referring to the net, the connection terminal of the circuit element or the second semiconductor chip corresponds to the start point, and corresponds to the start point The through hole or the connection terminal of the circuit element or the second semiconductor chip as a target point, by setting the grid value from the start point to the target point by the maze method, by performing a backtrace process, And a fourth step as a net wiring route.

  Moreover, in the wiring method of the semiconductor device according to the present invention, the through hole for changing the position in the third step is formed with the second wiring pattern disposed on the upper surface of the sealing material as necessary. The first through hole connecting the first wiring pattern disposed on the upper surface of the substrate, and the position where the first through hole is changed is on the corresponding first wiring pattern. It is characterized by.

  In the wiring method for a semiconductor device according to the present invention, if necessary, one net in the third step has a wiring length longer than the other net in the third step. Is.

  Furthermore, in the wiring method of the semiconductor device according to the present invention, the substrate on which the external terminals are disposed, the first semiconductor chip mounted on the upper surface of the substrate, and the first semiconductor chip on the substrate. In a wiring method of a semiconductor device comprising a sealed encapsulant, a position of a connection element of a circuit element or a second semiconductor chip mounted on the encapsulant and an upper surface of the encapsulant from the top surface of the substrate A first step of setting a position of a through hole penetrating to the upper surface or the lower surface; and a connection terminal between the circuit element or the second semiconductor chip and the through hole, or a connection terminal of the circuit element and the second semiconductor. A second step of assigning nets between the connection terminals of the chip and a plurality of nets assigned in the second step, and there are intersecting nets among the plurality of nets A third step of changing one of the intersecting nets to a net that does not intersect the other net without changing the position of the through hole in the intersecting net; and Referring to the net, the connection point of the circuit element or the second semiconductor chip is a start point, the through hole corresponding to the start point or the connection terminal of the circuit element or the second semiconductor chip is a target point, and the maze And a fourth step of setting a grid value from the start point to the target point and performing a backtrace process to set the net wiring route.

  In the method of wiring a semiconductor device according to the present invention, if necessary, one net in the third step is the first net on the top surface of the sealing material and the first net on the side surface of the sealing material. The first net and the second net are connected via a virtual terminal at a boundary between the upper surface and the side surface of the sealing material, and the virtual terminal is the fourth step. It is a starting point or a target point in.

  In the wiring method of the semiconductor device according to the present invention, the second wiring pattern disposed on the upper surface of the sealing material, if necessary, in the net assigned in the second step Of the through holes, each through hole in a plurality of nets by each second wiring pattern connected to a connection terminal that can share the function of the connection terminals of the circuit element or the second semiconductor chip is defined as one through hole. And changing the plurality of nets having the through holes assigned in the second step as target points into nets having the unified through holes as target points, Between the step and the third step.

  Furthermore, in the wiring method of the semiconductor device according to the present invention, the same first wiring disposed on the upper surface of the substrate among the through holes in the net allocated in the second step, if necessary. In the case where there are a plurality of first through holes connected to a pattern, a net having a plurality of first through holes connected to the same first wiring pattern as a target point is defined as the same first first hole. The step of selecting one first through hole from among the plurality of first through holes connected to the wiring pattern and changing to the net having the selected first through hole as a target point, It is characterized by having between the step and the third step.

  Moreover, in the wiring method of the semiconductor device according to the present invention, the first wiring pattern disposed on the upper surface of the substrate and the second wiring pattern disposed on the upper surface of the sealing material as necessary. The through hole in the first step corresponds to the sealing corresponding to the first wiring pattern connected to the connection terminal that can share the function in the first semiconductor chip and the circuit element or the second semiconductor chip. Of the sealing material corresponding to the external terminal not conducting to the connection terminal of the first semiconductor chip among the external terminals in which the first through hole is located at the upper surface position of the stopper and the wiring pattern of the substrate does not exist above. The second through hole is set at the position of the upper surface.

  In the wiring method of the semiconductor device according to the present invention, the substrate on which the external terminals are disposed, the first semiconductor chip mounted on the upper surface of the substrate, and sealing the first semiconductor chip on the substrate In the wiring method of the semiconductor device comprising the sealing material, the position of the connection terminal of the circuit element or the second semiconductor chip mounted on the sealing material and the top surface of the substrate from the top surface of the sealing material or A first step of setting a position of a through hole penetrating to the lower surface; and a connection terminal between the circuit element or the second semiconductor chip and the through hole, or a connection terminal of the circuit element and the second semiconductor chip. A second step of assigning nets between connection terminals, and a plurality of nets assigned in the second step, and there are crossing nets among the plurality of nets. A third step of changing one of the intersecting nets to a net that does not intersect the other net without changing the position of the through hole in the intersecting net; and see the net Then, the connection terminal of the circuit element or the second semiconductor chip is a start point, the through hole corresponding to the start point or the connection terminal of the circuit element or the second semiconductor chip is a target point, and by a maze method, A grid value is set from the start point to the target point, and a back trace process is performed to form a wiring path for the net, thereby including a first semiconductor chip or an external terminal. The wiring length between the circuit element or the second semiconductor chip is minimized within the limit imposed by the through hole. Wiring can be performed automatically and efficiently.

  Moreover, in the wiring method of the semiconductor device according to the present invention, the through hole for changing the position in the third step is formed with the second wiring pattern disposed on the upper surface of the sealing material as necessary. The first through hole connecting the first wiring pattern disposed on the upper surface of the substrate, and the position where the first through hole is changed is on the corresponding first wiring pattern. Thus, the first wiring pattern and the first through hole can be connected without changing the arrangement of the first wiring pattern.

  In the wiring method for a semiconductor device according to the present invention, if necessary, one net in the third step is changed because the wiring length is longer than the other net in the third step. The wiring length of one net is shortened, signal delay can be suppressed, and the possibility of crossing with another wiring can be reduced.

  Furthermore, in the wiring method of the semiconductor device according to the present invention, the substrate on which the external terminals are disposed, the first semiconductor chip mounted on the upper surface of the substrate, and the first semiconductor chip on the substrate. In a wiring method of a semiconductor device comprising a sealed encapsulant, a position of a connection element of a circuit element or a second semiconductor chip mounted on the encapsulant and an upper surface of the encapsulant from the top surface of the substrate A first step of setting a position of a through hole penetrating to the upper surface or the lower surface; and a connection terminal between the circuit element or the second semiconductor chip and the through hole, or a connection terminal of the circuit element and the second semiconductor. A second step of assigning nets between the connection terminals of the chip and a plurality of nets assigned in the second step, and there are intersecting nets among the plurality of nets A third step of changing one of the intersecting nets to a net that does not intersect the other net without changing the position of the through hole in the intersecting net; and Referring to the net, the connection point of the circuit element or the second semiconductor chip is a start point, the through hole corresponding to the start point or the connection terminal of the circuit element or the second semiconductor chip is a target point, and the maze By setting the grid value from the start point to the target point by the method, and performing the back trace process, the fourth step of setting the wiring route of the net, the first semiconductor chip or The wiring length between the external terminal and the circuit element or the second semiconductor chip is within the limit due to the through hole. It can be carried out wires to short automatically and efficiently.

  In the method of wiring a semiconductor device according to the present invention, if necessary, one net in the third step is the first net on the top surface of the sealing material and the first net on the side surface of the sealing material. The first net and the second net are connected via a virtual terminal at a boundary between the upper surface and the side surface of the sealing material, and the virtual terminal is the fourth step. If there is no space on the top surface of the encapsulant that will cause one net to wrap around so that it does not cross the other net by becoming the start point or target point in, use the space on the side of the encapsulant Can do.

  In the wiring method of the semiconductor device according to the present invention, the second wiring pattern disposed on the upper surface of the sealing material, if necessary, in the net assigned in the second step Of the through holes, each through hole in a plurality of nets by each second wiring pattern connected to a connection terminal that can share the function of the connection terminals of the circuit element or the second semiconductor chip is defined as one through hole. And changing the plurality of nets having the through holes assigned in the second step as target points into nets having the unified through holes as target points, Between the step and the third step, the number of through holes can be reduced and the second wiring pattern can be disposed. Space can be widened in the upper surface of the wood.

  Furthermore, in the wiring method of the semiconductor device according to the present invention, the same first wiring disposed on the upper surface of the substrate among the through holes in the net allocated in the second step, if necessary. In the case where there are a plurality of first through holes connected to a pattern, a net having a plurality of first through holes connected to the same first wiring pattern as a target point is defined as the same first first hole. The step of selecting one first through hole from among the plurality of first through holes connected to the wiring pattern and changing to the net having the selected first through hole as a target point, An external wiring board is used to make the circuit element or the second semiconductor chip and the first semiconductor chip conductive by having it between the step and the third step. No necessity, reduces the number of through-holes, it is possible to widen the space in the upper surface of the sealing material can be disposed a second wiring pattern.

  Moreover, in the wiring method of the semiconductor device according to the present invention, the first wiring pattern disposed on the upper surface of the substrate and the second wiring pattern disposed on the upper surface of the sealing material as necessary. The through hole in the first step corresponds to the sealing corresponding to the first wiring pattern connected to the connection terminal that can share the function in the first semiconductor chip and the circuit element or the second semiconductor chip. Of the sealing material corresponding to the external terminal not conducting to the connection terminal of the first semiconductor chip among the external terminals in which the first through hole is located at the upper surface position of the stopper and the wiring pattern of the substrate does not exist above. By setting the second through hole at the position of the upper surface, the position of the through hole in the first step can be specified.

(First embodiment of the present invention)
FIG. 1 is a plan view showing an example of a semiconductor device according to a first embodiment for carrying out the present invention. FIG. 2 is a plan view showing a second semiconductor chip on a sealing material on a substrate through a first through hole. FIG. 3A is a cross-sectional view taken along the line AA of the semiconductor device shown in FIG. 1 when connected to the first wiring pattern, and FIG. 3A shows the second through-hole in the second semiconductor chip on the sealing material. FIG. 3B is a cross-sectional view taken along the line AA of the semiconductor device shown in FIG. 1 when connected to the external terminal via FIG. 3, and FIG. 3B is an explanatory view showing a state where the through hole is connected to the external terminal. ) Is a sectional view showing an example of PoP in which the semiconductor device shown in FIG. 1 is arranged on another package, and FIG. 4 is a plan view showing another example of the semiconductor device according to the first embodiment for carrying out the present invention. FIG. 5A shows that the second semiconductor chip on the sealing material has a third through hole and a second layer on the substrate layer. FIG. 5B is a cross-sectional view taken along the line BB of the semiconductor device shown in FIG. 4 when connected to the first semiconductor chip through the wiring pattern of FIG. 4, and FIG. 5B shows the second semiconductor chip on the sealing material. It is sectional drawing of the arrow CC line of the semiconductor device shown in FIG. 4 in the case of connecting to an external terminal via the 4th through-hole and the 4th wiring pattern on a board | substrate layer.

  1 to 5, a substrate 1 is a multilayer wiring board, an external terminal 2 is disposed on the lower surface 1a, an internal terminal (not shown) is disposed on the upper surface 1b, and the external terminal 2 and the internal terminal are connected to the substrate 1. These are electrically connected through wiring patterns and vias (not shown) formed on the respective substrate layers. Note that, as the external terminal 2, a ball 2a made of a conductive material such as solder is mounted on a bump 2b made of a conductive material such as Au.

  The first semiconductor chip 4 has a terminal (not shown) and an internal terminal disposed on the upper surface 1b of the substrate 1 mounted by a flip chip. The first semiconductor chip 4 may be mounted on the upper surface 1b of the substrate 1 by wire bonding. In the first embodiment, two first semiconductor chips 4 are mounted on the upper surface 1 b of the substrate 1, and one first semiconductor chip is mounted on one first semiconductor chip 4. However, the number and arrangement of the first semiconductor chips 4 are not limited, and one or a plurality of first semiconductor chips 4 having various functions are provided depending on the purpose of the SiP. One semiconductor chip 4 or a soldering part (not shown) is appropriately arranged.

  In the following, the connection part of the semiconductor chip when mounted by flip chip is referred to as a terminal, the connection destination of the wire of the semiconductor chip when mounted by wire bonding is referred to as a bond finger, and in order to eliminate duplication of explanation, In some cases, terminals and bond fingers are collectively referred to as connection terminals.

  The first semiconductor chip 4 is sealed on the substrate 1 with a sealing material 5 such as epoxy resin, polyimide resin, silicone, polyester resin, acrylic resin, phenol resin, or fluororesin, thereby forming SiP3. In the first embodiment, an epoxy resin is used as the sealing material 5 and SiP3 is a rectangular parallelepiped package. The sealing material 5 has an upper surface 5a and four side surfaces 5b.

  The second semiconductor chip 6 is mounted on the upper surface 5a of the sealing material 5 by wire bonding, and the bond finger 6b to which the wire 6a is connected on the upper surface 5a of the sealing material 5 is placed on the sealing material 5. Are connected to the second wiring pattern 7 disposed by soldering. The second semiconductor chip 6 may be mounted on the upper surface 5a of the sealing material 5 by flip chip.

  The first semiconductor chip 4 and the second semiconductor chip 6 are integrated circuits in which a plurality of circuit elements and wirings connecting them are integrated as a single unit, and are integrated. Depending on the number, it can be divided into IC (Integrated Circuit), LSI (Large Scale Integration), VLSI (Very Large Scale Integration), ULSI (Ultra Large Scale Integration) and the like.

  The circuit element 8 is mounted on the upper surface 5a of the sealing material 5 and connected to the second wiring pattern 7 disposed on the sealing material 5 by soldering. The circuit element 8 is a component such as a resistor or a capacitor, and is mounted on the SiP 3 as necessary.

  The through hole 9 includes a second wiring pattern 7 disposed on the sealing material 5, a first wiring pattern 10 disposed on the upper surface 1 b of the substrate 1, the upper surface 1 b of the substrate 1, or a plurality of substrates 1. A third wiring pattern 15 connected and disposed on a layer of the substrate 1 via a via (not shown), or a fourth wiring pattern 16 connected and disposed on a plurality of layers of the substrate 1 via a via (not shown). Or by connecting the external terminal 2 disposed on the lower surface 1a of the substrate 1 and filling the inside with a conductive material 11, so that the second wiring pattern 7, the first wiring pattern 10, and the third wiring The wiring pattern 15 or the fourth wiring pattern 16 or the external terminal 2 is electrically connected.

  2 shows an example of the first through hole 9a penetrating from the upper surface 5a of the sealing material 5 to the upper surface 1b of the substrate 1 in the through hole 9, and in FIG. 3A, the through hole is shown. 9 shows an example of a second through hole 9 b that penetrates from the upper surface 5 a of the sealing material 5 to the lower surface 1 a of the substrate 1.

  5A shows an example of a third through hole 9c penetrating from the upper surface 5a of the sealing material 5 to the upper surface 1b of the substrate 1 in the through hole 9, and in FIG. In the through hole 9, an example of a fourth through hole 9d penetrating from the upper surface 5a of the sealing material 5 to the upper surface 1b of the substrate 1 is shown.

  The third wiring pattern 15 is a wiring pattern that is connected and disposed on the upper surface 1b of the substrate 1 or a plurality of layers of the substrate 1 via vias (not shown), and the third through hole 9c and the substrate 1 are arranged. The first wiring pattern 10 disposed on the upper surface 1b of the first semiconductor chip 4 or the connection terminal of the first semiconductor chip 4 is connected.

  The fourth wiring pattern 16 is a wiring pattern that is connected and disposed on a plurality of layers of the substrate 1 via vias (not shown). The fourth wiring pattern 16 connects the fourth through-hole 9d and the external terminal 2. Yes.

  Further, the first through hole 9a is formed using a solvent or a laser that does not dissolve the substrate 1 and the first wiring pattern 10, but dissolves the sealing material 5. As a result, the first wiring pattern 10 is exposed at the portion of the first through hole 9a, and the conductive material 11 is filled in the first through hole 9a. The two wiring patterns 7 can be made conductive.

  The third through hole 9c and the fourth through hole 9d use a solvent or a laser that does not dissolve the substrate 1, the third wiring pattern 15, and the fourth wiring pattern 16, but dissolves the sealing material 5. Form. As a result, the third wiring pattern 15 is exposed at the portion of the third through hole 9c, and the fourth wiring pattern 16 is exposed at the portion of the fourth through hole 9d, so that the third through hole 9c is exposed. The third wiring pattern 15 or the fourth wiring pattern 16 and the second wiring pattern 7 can be electrically connected by filling the conductive material 11 in the fourth through hole 9d.

  That is, the connection terminal of the first wiring pattern 10 or the first semiconductor chip 4 disposed on the upper surface 1b of the substrate 1 and the second wiring pattern 7 disposed on the sealing material 5 are The third wiring pattern 15 and the third through hole 9c are electrically connected via the conductive material 11 filled therein. Further, the second wiring pattern 7 and the external terminal 2 arranged on the upper surface 5a of the sealing material 5 are interposed through the conductive material 11 filled in the fourth wiring pattern 16 and the third through hole 9c. Is conducting.

  The first through hole 9a serves as a connection terminal that can share a function with the connection terminal of the first semiconductor chip 4 among the connection terminals (bond fingers or terminals) of the circuit element 8 or the second semiconductor chip 6. On the other hand, it penetrates from the upper surface 5a of the sealing material 5 to the upper surface 1b of the substrate 1 so as to connect the first wiring pattern 10 and the second wiring pattern 7 respectively connected to the connection terminals that can share this function. Is. Here, the connection terminal that can share the function is a connection terminal that inputs and outputs a common signal, power supply, and ground.

  The third through hole 9c serves as a connection terminal that can share a function with the connection terminal of the first semiconductor chip 4 among the connection terminals (bond fingers or terminals) of the circuit element 8 or the second semiconductor chip 6. On the other hand, the first wiring pattern 10 and the second wiring pattern 7 respectively connected to connection terminals that can share this function are made conductive by using the third wiring pattern 15 together. Alternatively, the third through hole 9c serves as a connection terminal of the first semiconductor chip 4 and a connection terminal of the circuit element 8 or the second semiconductor chip 6 that can share the function with the connection terminal of the first semiconductor chip 4. The second wiring pattern 7 to be connected is made conductive by using the third wiring pattern 15 together.

  The fourth through hole 9d is connected to a connection terminal that cannot share a function with all the connection terminals of the first semiconductor chip 4 among the connection terminals of the circuit element 8 or the second semiconductor chip 6. The wiring pattern 7 is electrically connected to the external terminal 2 that is not electrically connected to the connection terminal of the first semiconductor chip 4 together with the fourth wiring pattern 16.

  Further, instead of the first through hole 9a filled with the conductive material 11, a conductive pole (such as a connection wiring material) is erected from the first wiring pattern 10 disposed on the upper surface 1b of the substrate 1. The first wiring pattern 10 is also formed through the conductive pole by sealing the upper surface of the substrate 1 with the sealing material 5 so that the tip of the pole is exposed with the pole standing upright. And the second wiring pattern 7 can be made conductive. That is, the conductive pole corresponds to the conductive material 11, and the inside surrounded by the sealing material 5 in contact with the side surface of the pole corresponds to the first through hole 9 a.

  Further, instead of the third through hole 9c and the fourth through hole 9d filled with the conductive material 11, from the third wiring pattern 15 or the fourth wiring pattern 16 provided on the upper surface 1b of the substrate 1. Also, a conductive pole (such as a connection wiring material) is formed upright, and the top surface of the substrate 1 is sealed with a sealing material 5 so that the tip of the pole is exposed with the pole upright. The third wiring pattern 15 or the fourth wiring pattern 16 and the second wiring pattern 7 can be conducted through the conductive pole. That is, the conductive pole corresponds to the conductive material 11, and the inside which is in contact with the side surface of the pole and surrounded by the sealing material 5 corresponds to the third through hole 9 c or the fourth through hole 9 d.

  The second through-hole 9b is formed using a solvent or laser that dissolves the substrate 1 and the sealing material 5, or a drilling tool such as a drill that can open a through-hole in the substrate 1 and the sealing material 5. To do.

  The second through hole 9b is connected to a connection terminal that cannot share a function with all the connection terminals of the first semiconductor chip 4 among the connection terminals of the circuit element 8 or the second semiconductor chip 4. The upper surface 5a of the encapsulant 5 is connected to connect the wiring pattern 7 to the external terminal 2 that is not electrically connected to the connection terminal of the first semiconductor chip 4 among the external terminals 2 on which the wiring pattern of the substrate 1 does not exist. To the bottom surface 1 a of the substrate 1.

  Further, as shown in FIG. 3A, by connecting the external terminal 2 to the external wiring pattern 12 on the board in an external device (not shown), the second semiconductor chip 6 becomes the second wiring pattern 7, The electrical connection is made to an external device through the conductive material 11 and the external terminal 2 in the two through holes 9b.

  Further, an external device (not shown) may be another SiP3 or CoP, and as shown in FIG. 3C, a PoP may be used in which a package is arranged and wired on the upper surface of another package. 3C shows an example in which the external terminal 2 connected to the external wiring pattern 12 is electrically connected to the second wiring pattern 7 via the conductive material 11 in the second through hole 9b. However, the configuration is not limited to this configuration, and the external wiring pattern 12 may be connected to the external terminal 2 connected to the first wiring pattern 10 or the fourth wiring pattern 16.

  In the first embodiment, the second semiconductor chip 6 is disposed at the position overlapping the first semiconductor chip 4 on the upper surface 5 a of the sealing material 5. If the space on the upper surface of the sealing material 5 for disposing the second semiconductor chip 6 or the circuit element 8 can be secured outside the region overlapping the first semiconductor chip 4 on the upper surface 5a, the sealing material 5 It is preferable that the second semiconductor chip 6 or the circuit element 8 be disposed outside the region overlapping the first semiconductor chip 4 on the upper surface. Thereby, it is possible to suppress the heat generated from the first semiconductor chip 4 from propagating to the second semiconductor chip 6 or the circuit element 8 through the sealing material 5, and the second semiconductor chip 6 due to heat. Or the influence of malfunction etc. of the circuit element 8 can be suppressed.

  Further, since the heat inside the sealing material 5 is likely to be generated, a heat dissipation via is formed around the first semiconductor chip 4 in order to efficiently dissipate the heat generated from the first semiconductor chip 4 to the outside of the SiP 3. It is preferable to do. In particular, by arranging the through hole 9 filled with the conductive material 11 around the first semiconductor chip 4, it can serve as a heat dissipation via.

  In the first embodiment, the second semiconductor chip 6 and the circuit element 8 are exposed on the sealing material 5. However, the second semiconductor chip 6 and the circuit element 8 are exposed on the sealing material 5. By sealing with a sealing material, the second semiconductor chip 6 and the circuit element 8 can be protected from external impact.

  Further, in the first embodiment, as shown in FIG. 3A, the second semiconductor chip 6 is interposed via the second wiring pattern 7 and the conductive material 11 in the second through hole 9b. Although an example of conducting to the external wiring pattern 12 on the board of an external device (not shown) has been shown, the second semiconductor chip 6 is connected to the second without passing through the conductive material 11 in the second through hole 9b. The wiring pattern 7 and the external wiring pattern 12 may be connected by a wire.

  Next, in the CoP in which the second semiconductor chip 6 or the circuit element 8 is mounted on the SiP3, the connection between the connection terminal of the second semiconductor chip 6 or the circuit element 8 on the SiP3 and the first semiconductor chip 4 in the SiP3. The wiring support apparatus 100 for wiring between the terminals or the external terminals 2 will be described.

  FIG. 6 is a diagram showing the configuration of the wiring support apparatus according to the first embodiment for carrying out the present invention. FIG. 7 is an example of wiring conditions stored in the wiring condition storage means in the wiring support apparatus shown in FIG. 4A is an explanatory diagram before avoiding the intersection of the second wiring patterns, FIG. 4B is an explanatory diagram showing a means for avoiding the intersection of the second wiring patterns, and FIG. FIG. 8 is an explanatory view showing another means for avoiding the intersection of the second wiring patterns, FIG. 8 is an explanatory view for explaining the maze method used for the detailed automatic wiring processing means in the wiring support apparatus shown in FIG. 6, and FIG. FIG. 10 is an explanatory diagram for explaining the continuation of the maze method shown in FIG. 9, and FIG. 11 is an explanatory diagram for explaining the continuation of the maze method shown in FIG. It is explanatory drawing of.

  In FIG. 6, the layout information storage unit 21 includes the shape data and layer number data of the substrate 1, the wiring prohibited area data, and the first data arranged on the upper surface 1 b of the substrate 1 in the SiP 3 that has already been designed for wiring. The arrangement data and shape data of the semiconductor chip 4, the arrangement data and terminal attribute data of the connection terminals (terminals or bond fingers) of each first semiconductor chip 4, and the external terminals 2 arranged on the lower surface 1 a of the substrate 1. Arrangement data and terminal attribute data, arrangement data of the third through hole 9c and the fourth through hole 9d (when the user specifies the position of the third through hole 9c or the fourth through hole 9d), and the substrate 1 stores wiring data of wiring patterns (including the first wiring pattern 10) arranged on each substrate layer.

  In addition, the placement data and shape data of each second semiconductor chip 6 arranged on the upper surface 5a of the sealing material 5 on the SiP 3 to be designed for wiring, the placement data and shape data of each circuit element 8, Arrangement data and terminal attribute data of connection terminals (bond fingers 6b or terminals) of the semiconductor chip 6 and each circuit element 8, wiring data of the second wiring pattern 7 disposed on the upper surface 5a of the sealing material 5, Arrangement data of the through holes 9 (the first through hole 9a and the second through hole 9b) (when the user does not specify the position of the third through hole 9c or the fourth through hole 9d), the upper surface 1b of the substrate 1 Alternatively, the wiring data of the third wiring pattern 15 and the fourth wiring pattern 16 disposed on the plurality of layers of the substrate 1 (the user sets the position of the third through hole 9c or the fourth through hole 9d). If there boss), and is for storing or wiring prohibition area data.

  Here, the shape data of the substrate 1 is data indicating what shape the substrate 1 has. For example, a rectangular substrate may have vertical and horizontal dimensions. The number-of-layers data of the substrate 1 is data indicating how many layers the substrate 1 is formed. Further, the wiring prohibition area data is data related to a prohibition area in which wiring cannot be arranged on each substrate layer.

  Furthermore, the arrangement data of the first semiconductor chip 4 (second semiconductor chip 6, circuit element 8) is data relating to the arrangement coordinates of each first semiconductor chip 4 (second semiconductor chip 6, circuit element 8). It is. Specifically, the point representing the position of the first semiconductor chip 4 (second semiconductor chip 6, circuit element 8) (for example, the first semiconductor chip 4 (second semiconductor chip 6, circuit element 8)) Coordinate data of one of the vertices below. The shape data of the first semiconductor chip 4 (second semiconductor chip 6, circuit element 8) is data relating to the shape of each first semiconductor chip 4 (second semiconductor chip 6, circuit element 8). is there. Specifically, in the case of the first semiconductor chip 4 (second semiconductor chip 6 and circuit element 8) having a rectangular parallelepiped shape, the data is vertical, horizontal, and height data.

  Furthermore, the arrangement data of the connection terminals of the first semiconductor chip 4 is the arrangement data of the terminals for the flip chip in the first semiconductor chip 4 in the first embodiment. The connection terminal arrangement in the connection terminal arrangement data indicates relative coordinates with respect to a representative point of the first semiconductor chip 4. In addition, in the first embodiment, the arrangement data of the connection terminals of the second semiconductor chip 6 (circuit element 8) is the bond data for wire bonding in the second semiconductor chip 6 (circuit element 8). This is data of the arrangement of the fingers 6b (terminals not shown of the circuit element 8).

  The terminal attribute data of the first semiconductor chip 4 (second semiconductor chip 6, circuit element 8, external terminal 2) is the first semiconductor chip 4 (second semiconductor chip 6, circuit element 8, substrate). 1) terminals (bond finger 6b, terminal of circuit element 8, external terminal 2), and which terminals (bond finger 6b, terminal of circuit element 8, external terminal 2) each input / output is It is data indicating whether it is being performed.

  In addition, the arrangement of the third through hole 9c and the fourth through hole 9d is a fixed arrangement specified in advance before the user performs the automatic wiring process, and the arrangement data is generated by the arrangement design CAD device 200. The

  Further, the shape data and layer number data of the substrate 1, the arrangement data and shape data of each first semiconductor chip 4 disposed on the upper surface 1 b of the substrate 1, and the connection terminals (terminals or bonds) of each first semiconductor chip 4 Finger arrangement data and terminal attribute data, external terminal 2 arrangement data and terminal attribute data arranged on the lower surface 1 a of the substrate 1, wiring patterns arranged on each substrate layer of the substrate 1 (first The wiring data (including the wiring pattern 10), the wiring prohibited area data, and the like are generated by the layout design CAD device 200.

The wiring condition storage means 22 stores wiring conditions for wiring. As a special wiring condition in the CoP according to the present invention, the first through hole 9 a is generated from the first wiring pattern 10, and the second through hole 9 b is generated from the bump 2 b which is the external terminal 2.
Further, as shown in FIG. 3B, the position (contact area) on the bump 2b by the second through hole 9b is designated as an offset. Moreover, the minimum value of the space | interval between adjacent through-holes 9 is designated.

  In addition, when there is a connection terminal (for example, a power supply terminal) that can share the function among the connection terminals of the circuit element 8 or the second semiconductor chip 6, each of the first connection terminals connected to the connection terminal that can share this function. The through holes 9 in the plurality of nets by the two wiring patterns 7 are unified into the through holes 9 in the optimum place. In addition, by integrating the through hole 9, the net connected to the changed through hole 9 may be longer than the original wiring length. Therefore, it is preferable to unify the through holes 9 in consideration of an allowable range with respect to a signal delay or the like when wiring the second wiring pattern 7.

  Furthermore, there is a restriction that the wiring pattern that connects the second semiconductor chip 7 or the circuit element 8 and the through hole 9 must be provided only by the surface layer of the sealing material 5. For this reason, when performing a rough automatic wiring process to be described later, as shown in FIG. 7A, the second finger for connecting the bond finger 6b (or terminal) of the second semiconductor chip 6 and the through hole 9 is connected. In the net in the wiring pattern 7, when the wiring pattern 7a of the net A and the wiring pattern 7b of the net B intersect, as a means for avoiding the intersection, the position of the through hole 9 in one of the intersecting nets Is changed so that one net does not cross the other net.

  Specifically, as shown in FIG. 7B, the through holes 9 whose positions are changed are arranged on the second wiring pattern 7 a disposed on the upper surface 5 a of the sealing material 5 and on the upper surface 1 b of the substrate 1. The first through hole 9a is connected to the first wiring pattern 10a provided, and the position of the first through hole 9a is on the corresponding first wiring pattern 10a, considering other wiring patterns. To change to the optimal position. In addition, it is preferable to change the position of the first through hole 9a in the net A having a longer wiring length than the net B.

  As another means for avoiding the intersection, one of the intersecting nets is changed to a net that wraps around so as not to intersect the other net. Specifically, as shown in FIG. 7C, one net (net A) includes a first net A1 on the upper surface 5a of the sealing material 5 and a second net A2 on the side surface 5b of the sealing material. The first net A1 and the second net A2 are connected via the virtual terminal 13 at the boundary between the upper surface 5a and the side surface 5b of the sealing material 5. Thereby, when there is no space on the upper surface 5a of the sealing material 5 so that one of the nets does not cross the other net (net B), the space on the side surface 5b of the sealing material 5 is used. Can do.

  The external terminal identification unit 23 stores the terminal attribute data of the external terminal 2, the terminal attribute data of the first semiconductor chip 4, and the terminal attribute of the second semiconductor chip 6 or the circuit element 8 stored in the layout information storage unit 21. Based on the data, the external terminal 2 that conducts with the connection terminal of the first semiconductor chip 4 that can share the function, the external terminal 2 that conducts with the connection terminal of the first semiconductor chip 4 that cannot share the function, and the first The external terminals 2 that are not electrically connected to the connection terminals of the semiconductor chip 4 are classified. Further, the data of the external terminal 2 that is electrically connected to the connection terminal of the first semiconductor chip 4 that can share the function is output to the first through-hole generating means 24 and the detailed automatic rewiring processing means 30b in the package, and the first semiconductor The data of the external terminal 2 that is not electrically connected to the connection terminal of the chip 4 is output to the second through hole generating means 25 and the detailed automatic rewiring processing means 30b in the package.

  The first through hole generating means 24 functions according to the rules stored in the wiring condition storage means 22 based on the data stored in the layout information storage means 21 and the data obtained from the external terminal identification means 23. On the first wiring pattern 10 that is electrically connected to the external terminal 2 that is electrically connected to the connection terminal of the first semiconductor chip 4 that can be shared, the first through-hole 9 a is provided at a position that does not overlap the second semiconductor chip 4 and the circuit element 8. Is generated. The arrangement data of the first through hole 9a is output to the general automatic wiring processing means 26.

  Based on the data stored in the layout information storage means 21 and the data obtained from the external terminal identification means 23, the second through-hole generating means 25 follows the rules stored in the wiring condition storage means 22 in accordance with the rules stored in the wiring condition storage means 22. Of the external terminals 2 that do not overlap with the semiconductor chip 4 and the circuit element 8 and do not have the wiring pattern of the substrate 1 on the upper side, they are connected to the external terminals 2 that are not electrically connected to the connection terminals of the first semiconductor chip 4. Then, the second through hole 9b is generated. The arrangement data of the second through hole 9 b is output to the general automatic wiring processing means 26.

  The parameter setting unit 27 has a rule file such as designation of the upper surface 5a or the side surface 5b of the sealing material 5 to be wired and setting of a wiring prohibited area, the SiP information file or the layout information storage unit 21 and the wiring condition storage unit 22. Enter the board information file. Specifically, for example, the parameter setting means 27 displays an input dialog on the display device 28 such as a CRT or a liquid crystal display, prompts the user to input wiring conditions, SiP information or board information, A program module that saves the rule file, SiP information file, or board information file input from the input device 29 such as a keyboard in the layout information storage means 21 and the wiring condition storage means 22 can be used.

  The rough automatic wiring processing means 26 includes the data stored in the layout information storage means 21 such as the arrangement data of the third through holes 9c and the fourth through holes 9d, the first through hole generating means 24 and the second through holes 9c. The connection terminal of the first semiconductor chip 7 or the circuit element 8 and the first through hole 9a, according to the rules stored in the wiring condition storage unit 22, based on the data obtained by the through hole generation unit 25 A net is allocated between the second through hole 9b, the third through hole 9c, or the fourth through hole 9d.

The detailed automatic wiring processing unit 30a on the package refers to the net obtained by the general automatic wiring processing unit 26, and the rules stored in the wiring condition storage unit 22 based on the data stored in the layout information storage unit 21. In accordance with the above, the net wiring route is processed by the maze method.
Here, the maze method used in the on-package detailed automatic wiring processing means 30a will be described with reference to FIGS.

First, as shown in FIG. 8A, the entire wiring region is gridded.
Next, as shown in FIG. 8B, the start point S and the target point T are set on the grid. In this case, the upper surface 5a or the side surface 5b of the sealing material 5 is a target range using the maze method, and each connection terminal of the second semiconductor chip 6 or each connection terminal of the circuit element 8 on the upper surface 5a of the sealing material 5 is used. One of them is a start point S, a first through hole 9a, a second through hole 9b, a third through hole 9c, a fourth through hole 9d, a virtual terminal 13 and a second terminal corresponding to the start point S. A connection terminal of the semiconductor chip 6 or a connection terminal of the circuit element 8 is defined as a target point T. One of the virtual terminals 13 on the side surface 5b of the sealing material 5 is a start point S, and the virtual terminal 13 corresponding to the start point S is a target point T.

  That is, when there is no space for arranging the second wiring pattern on the upper surface 5a of the sealing material 5, the virtual terminal 13 is used as the start point S or the target point T in order to use the side surface 5b of the sealing material 5. It becomes. Further, the wiring prohibited area 14 is set on the grid. The wiring prohibited area 14 includes a zone of a chip instance and an existing wiring figure (a figure obtained by sizing the outline of a wiring figure by a spacing rule).

Next, as shown in FIG. 9A, a value of “0” is set in the grid at the start point S. Then, a value of “1” (the grid value of the start point S is 0 + 1 = 1) is set to the grid that is obliquely adjacent to the grid of the start point S. It should be noted that no value is set for the portion that is the wiring prohibited area 14.
Also, as shown in FIG. 9B, a value of “2” (1 + 1 = 2) is set in a grid that is diagonally adjacent to the grid in which the value of “1” is set.

  Next, as shown in FIG. 10A, “3” is set around the grid where the value “2” is set, and “4” is set around the grid where the value “3” is set. ”Is set, and the process is repeated in the same manner, and the process is stopped when the target point T is reached. If a value cannot be set for the target point T even if values are set for all the grids traced from the start point S, it is determined that there is no wiring route.

  Next, as shown in FIG. 10 (b), the grid advances from the target point T to the start point S in the direction in which the grid value decreases (back trace processing is performed). In this backtrace process, there is no redundant bending.

As shown in FIG. 11, when reaching the start point S, the route traced by the backtrace process is registered as a wiring figure as a net wiring route.
The in-package detailed automatic rewiring processing means 30b functions according to the rules stored in the wiring condition storage means 22 based on the data stored in the layout information storage means 21 and the data obtained from the external terminal identification means 23. The first wiring pattern 10 that is electrically connected to the connection terminal of the first semiconductor chip 4 that can share the same or the connection terminal of the first semiconductor chip 4 and the third through hole 9c are connected via the third wiring pattern 15. In order to connect the external terminal 2 that is not connected to the connection terminal of the first semiconductor chip 4 among the external terminals 2 and the fourth through-hole 9d through the fourth wiring pattern 16, the labyrinth method is used. Processing to make a net wiring route in the package is performed.

Here, the maze method used in the in-package detailed automatic rewiring processing means 30b will be described with reference to FIGS.
First, as shown in FIG. 8A, the entire wiring region is gridded. In the first embodiment, a 45/90 degree multi-layer maze method is used. The wiring is in the data acquisition order. Hereinafter, application of the maze method when the substrate layer is one layer will be described.
First, as shown in FIG. 8A, grid formation is performed on the entire wiring region (all substrate layers).

  Next, as shown in FIG. 8B, the start point S and the target point T are set on the grid. In this case, each layer of the substrate 1 is a target range using the maze method, and one of the third through hole 9c and the fourth through hole 9d on the upper surface 1b of the substrate 1 is set as the start point S and the start point S. The corresponding first wiring pattern 10, the connection terminal of the first semiconductor chip 4 or the external terminal 2 is defined as a target point T.

  Further, the wiring prohibited area 14 is set on the grid. The wiring prohibited area 14 includes a chip instance zone, an existing wiring figure (a figure obtained by sizing the outline of the wiring figure by a spacing rule), and a rect figure in which a Z coordinate is set (a figure Z1 coordinate <= Z2 of the substrate). Coordinates <only the substrate corresponding to the Z2 coordinate of the figure).

  Next, as shown in FIG. 9A, a value of “0” is set in the grid at the start point S. Then, a value of “1” (the grid value of the start point S is 0 + 1 = 1) is set to the grid that is obliquely adjacent to the grid of the start point S. In addition, the value specified by the via cost value in the rule file is set in the grid adjacent to the start point S in the vertical direction with respect to the Z direction (perpendicular to the page) (for example, 0 + 3 when the via cost value is “3”). = 3). It should be noted that no value is set for the portion that is the wiring prohibited area 14.

  Also, as shown in FIG. 9B, a value of “2” (1 + 1 = 2) is set in a grid that is diagonally adjacent to the grid in which the value of “1” is set. Also, the value specified by the via cost value in the rule file is set to the grid that is in contact with the grid in which the value of “1” is set in the upper and lower directions in the Z direction (vertical direction with respect to the page) (for example, the via cost). When the value is “3”, 1 + 3 = 4). In this case, if a value has already been set in the grid, overwriting is not performed.

  Next, as shown in FIG. 10A, “3” is set around the grid where the value “2” is set, and “4” is set around the grid where the value “3” is set. ”Is set, and the process is repeated in the same manner, and the process is stopped when the target point T is reached. If a value cannot be set for the target point T even if values are set for all the grids traced from the start point S, it is determined that there is no wiring route.

  Next, as shown in FIG. 10 (b), the grid advances from the target point T to the start point S in the direction in which the grid value decreases (back trace processing is performed). In this backtrace process, there is no redundant bending.

As shown in FIG. 11, when reaching the start point S, the route traced by the backtrace process is registered as a wiring figure as a net wiring route. When the substrate layer changes, a via cell is disposed at that position.
The output unit 31 outputs the wiring processing result obtained by the on-package detailed automatic wiring processing unit 30 a and the in-package detailed automatic rewiring processing unit 30 b to a file or the display device 28.

  Next, a wiring method of the semiconductor device in the first embodiment for carrying out the present invention will be described. FIG. 12 is a flowchart showing the overall flow of the wiring method according to the first embodiment for carrying out the present invention. FIG. 13 shows the overall flow of the schematic automatic wiring process in the overall flow of the wiring method shown in FIG. FIG. 14 is a flowchart showing a continuation of the flowchart shown in FIG. 13, FIG. 15 is a flowchart showing the flow of detailed automatic wiring processing on the package in the overall flow of the wiring method shown in FIG. 12, and FIG. 16 is a package shown in FIG. FIG. 17 is a flowchart showing the continuation of the flowchart shown in FIG. 16, FIG. 18 is a flowchart showing the continuation of the flowchart shown in FIG. 17, and FIG. 19 is a flowchart showing the continuation of the flowchart shown in FIG. 12 shows the flow of the detailed automatic rewiring process in the package in the overall flow of the wiring method shown in Fig. FIG. 20 is a flowchart showing the flow of the maze method in the entire flow of the detailed automatic rewiring process in the package shown in FIG. 19, FIG. 21 is a flowchart showing the continuation of the flowchart shown in FIG. 20, and FIG. It is a flowchart which shows the continuation of a flowchart.

  First, the layout design CAD apparatus 200 is used to design the shape of the first semiconductor chip 4, the arrangement of the first semiconductor chip 4 on the substrate 1, the connection terminals (terminals or bond fingers) of the first semiconductor chip 4, and Arrangement of the external terminals 2 and wiring of wiring patterns (including the first wiring pattern 7) disposed on each substrate layer of the substrate 1 are performed (step S1). Further, the design of the shape of the circuit element 8 and the second semiconductor chip 6, the arrangement of the circuit element 8 and the second semiconductor chip 6 on the sealing material 5, and the connection terminals of the circuit element 8 and the second semiconductor chip 6 (Terminal or bond finger) is arranged (step S2). Since this operation is the same as that of a conventional CAD apparatus, detailed description thereof is omitted. Position information of each first semiconductor chip 4 arranged on the substrate 1 created here, shape information of each first semiconductor chip 4, positions of connection terminals and external terminals 2 of each first semiconductor chip 4 Information, wiring information of each substrate layer of the substrate 1, position information of each circuit element 8 and the second semiconductor chip 6 disposed on the sealing material 5, shapes of each circuit element 8 and the second semiconductor chip 6 Information, position information of each circuit element 8 and connection terminals of the second semiconductor chip 6 and the like are stored in the layout information storage means 21.

  The third through hole 9c and the fourth through hole 9d are arranged at positions specified in advance before the user performs the automatic wiring process, and the user can use the third through hole 9c or the fourth through hole. When the position of the hole 9d is designated, the third through hole 9c or the fourth through hole 9d is arranged by the layout design CAD device 200, and the first through hole 9a and the second through hole are processed by automatic wiring processing. 9b is not arranged. Conversely, when the first through hole 9a and the second through hole 9b are arranged by automatic wiring processing (when the user does not specify the positions of the third through hole 9c and the fourth through hole 9d), The third through hole 9c and the fourth through hole 9d are not arranged.

  Next, when the third through hole 9c or the fourth through hole 9d is not arranged by the layout design CAD device 200, the first through hole 9a or the second through hole is used by using the wiring support device 100 described above. The arrangement of the holes 9b is automatically determined. Then, initial arrangement of the through-holes 9 (the first through-hole 9a or the second through-hole 9b, or the third through-hole 9c or the fourth through-hole 9d) that passes through the sealing material 5 is performed (Step S3). ), A schematic automatic wiring process for assigning a net by the second wiring pattern 7 for connecting the connection terminal of the second semiconductor chip 6 or the circuit element 8 and the through hole 9 is executed (step S4). The detailed operation of this general automatic wiring process will be described later.

Here, it is determined whether there is a wiring path for other nets other than the net to which the through hole 9 is assigned (step S5), and if there is no wiring path, the position of the through hole 9 can be moved. It is determined whether it is possible (step S6).
When it is determined in step S6 that the position of the through hole 9 can be moved, the through hole through which the net wiring to which the through hole 9 is assigned passes is changed (step S7), and the net wiring is changed. Is automatically determined, and the process returns to step S4 again to execute a general automatic wiring process.

  If it is determined in step S6 that the position of the through-hole 9 cannot be moved, another net is routed so that the through-hole 9 does not cross the assigned net (step S8), and the step is again performed. Returning to S4, the general automatic wiring process is executed.

  When it is determined in step S5 that there are wiring paths for all the nets, the wiring support apparatus 100 calculates the net wiring path for the upper surface 5a or the side surface 5b of the sealing material 5 and performs wiring processing. Automatic wiring processing is executed (step S9). The detailed operation of the detailed automatic wiring process on the package will be described later.

Next, it is determined whether the through hole 9 is the third through hole 9c or the fourth through hole 9d (step S10).
If it is determined in step S10 that the through-hole 9 is the third through-hole 9c or the fourth through-hole 9d, the wiring support device 100 calculates a net wiring route on the layer of the substrate 1. The detailed automatic rewiring process in the package for performing the wiring process is executed (step S11), and the wiring process is terminated. The detailed operation of the in-package detailed automatic rewiring process will be described later.
If it is determined in step S10 that the through hole 9 is not the third through hole 9c or the fourth through hole 9d, the wiring process is terminated.

First, the wiring process in the schematic automatic wiring process will be described with reference to FIGS.
As an initial state, the SiP information is stored in the layout information storage unit 21. Therefore, first, the general automatic wiring processing means 26 reads this SiP information from the layout information storage means 21. When the user does not specify the positions of the third through hole 9c and the fourth through hole 9d, the through hole 9 (the first through hole 9a, the first through hole 9a, The position and net of the second through hole 9b) are generated (step S12).

Next, it is determined whether the second semiconductor chip 4 or the circuit element 8 is mounted on the sealing material 5 by flip chip (step S13).
If it is determined in step S13 to be mounted on the sealing material 5 by flip chip, the terminal of the second semiconductor chip 4 or the circuit element 8 is connected to the through hole 9 (first through hole 9a or second through hole 9b. Or, schematic wiring is performed up to the third through hole 9c or the fourth through hole 9d) (step S14). Note that the intersection of nets is ignored in rough wiring.

  Further, when it is determined in step S13 that it is not mounted on the sealing material 5 by flip chip, it is mounted by wire bonding and penetrates from the bond finger (BF) of the second semiconductor chip 4 or circuit element 8. Schematic wiring is performed up to the hole 9 (the first through hole 9a or the second through hole 9b, or the third through hole 9c or the fourth through hole 9d) (step S15). Note that the intersection of nets is ignored in rough wiring.

  Next, when there are a plurality of first through holes 9a that are respectively connected to terminals that can share the functions of the second semiconductor chip 6 and the circuit element 8, or a plurality of first through holes 9a connected to the same first wiring pattern 10. When one through hole 9a exists, the first through hole 9a is thinned out according to the unification rule so as to reduce the number of the plurality of first through holes 9a (step S16).

Next, it is determined whether or not there is an outline wiring that intersects (step S17). If it is determined in step S17 that there is no intersecting schematic wiring, the schematic automatic wiring process is terminated.
Further, when it is determined in step S17 that crossing schematic wiring exists, the movement of the first through hole 9a connected to the crossing schematic wiring (for the third through hole 9c or the fourth through hole 9d, It is determined whether it can be changed to the position of another unused through-hole 9 (step S18). If any of the through holes 9 connected to the intersecting schematic wirings is the second through hole 9b, it is determined that the movement is not possible.

  When it is determined in step S18 that the first through hole 9a can be moved (the third through hole 9c or the fourth through hole 9d is changed to the position of another unused through hole 9). Moves to the position where the first through-hole 9a (the third through-hole 9c, the fourth through-hole 9d) connected to the schematic wiring having a long wiring pattern among the crossed schematic wirings does not intersect (other By changing the position of the through hole 9 to be used, a new schematic wiring is obtained (step S19), and the process returns to step S17. If only one of the intersecting schematic wirings is connected to the first through hole 9a, the first through hole 9a is moved.

  If it is determined in step S18 that the through hole 9 cannot be moved (the third through hole 9c or the fourth through hole 9d is changed to the position of another unused through hole 9). Then, it is determined whether there is a space that can be arranged on the upper surface 5a of the sealing material 5 by changing the position of the intersecting schematic wiring (step S20). If it is determined in step S20 that there is a space that can be disposed on the upper surface 5a of the sealing material 5, one outline of the intersecting outline wiring is made to wrap around the other outline wiring to obtain a new outline. Wiring is performed (step S21), and the process returns to step S17.

  When it is determined in step S20 that there is no space that can be disposed on the upper surface 5a of the sealing material 5, the side surface 5b located closest to the through hole 9 connected to the intersecting schematic wiring is set as a new wiring region. Then, one outline wiring of the intersecting outline wiring is made to wrap around the other outline wiring to form a new outline wiring (step S22), and the process returns to step S17. In addition, the virtual terminal 13 is generated at a boundary portion between the side surface 5b of the sealing material 5 and the upper surface 5a of the sealing material 5, which is a new wiring region.

  Next, the wiring process in the detailed automatic wiring process on the package will be described with reference to FIGS. First, the detailed automatic wiring processing unit 30a on the package reads SiP information from the layout information storage unit 21, forms a grid on the upper surface 5a and the side surface 5b of the sealing material 5 based on the SiP information (step S23), and prohibits wiring. An area is set (step S24).

Next, the net acquired by the above-described general automatic wiring process is wired by the maze method (step S25). The maze method in step S25 will be described later.
Next, it is determined whether the result obtained in step S25 can be wired (step S26). If it is determined in step S26 that wiring cannot be performed, “Warning: NetXXX cannot be wired” is displayed (step S27), and the process returns to step S25 to perform wiring processing for the next net (step S28).

  If it is determined in step S25 that the next net is routed by the maze method and it is determined in step S26 that all nets have been routed (step S29), it is determined whether all nets have been routed. When the wiring process is completed, the wiring process is terminated. If all the nets have not been routed, the process returns to step S25 to perform the next net routing process (step S28).

Next, the maze method in step S25 will be described with reference to FIGS.
First, a connection terminal (BF or terminal) of the second semiconductor chip 6 or the circuit element 8 is set as a start point. In addition, when the virtual terminal 13 is set by the general automatic wiring process described above, a part of the virtual terminal 13 is also set as the start point (step S30).

  Next, the target point is a through hole 9 (first through hole 9a or second through hole 9b, or third through hole 9c or fourth through the upper surface 5a of the sealing material 5 corresponding to the start point. Through holes 9d) (there may be a plurality of target points). In addition, when the virtual terminal 13 is set by the schematic wiring process mentioned above, in the side surface 5b of the sealing material 5, the virtual terminal 13 corresponding to the start point is set as the target point (step S31).

All grid values are initialized (step S32). Further, the grid value at the start point is set to “0” (step S33), and the current number is set to 0 (step S34).
A value of current number +1 is set in a grid adjacent to the acquired grid (step S35). Note that grids that already have values are not overwritten.

  Next, it is determined whether a value has been set for the grid at the target point (step S36). If it is determined in step S36 that a value has been set for the grid at the target location, the backtrace process in the maze method described above is performed so that the distance from the target location to the start location is reduced. (Step S37). Note that backtrace processing is performed so that the number of bends in the path is reduced. The route acquired in step S37 is set as the wiring route of the net (step S38).

  Next, it is determined whether another target point exists (step S39). If it is determined in step S39 that another target point exists, the next target point is acquired (step S40). Next, all the grids of the wiring route previously wired are set as start points (step S41), and the process returns to step S32.

If it is determined in step S36 that no value is set for the grid at the target location, it is further determined whether a value could not be set for any grid (step S42).
If it is determined in step S42 that no value can be set for any grid, the current current number is set to +1 (step S43), and the process returns to step S35.
If no value can be set for any grid in step S42, "Error: Net xxx cannot be wired" is displayed (step S44), and it is determined whether wiring to all targets has been completed normally. (Step S45).

In step S45, if the wiring to all the targets is not completed normally, the maze method is terminated. Further, when the wiring to all the targets is completed normally, the obtained wiring path is made into a line figure (step S46). Further, regarding the grid of the wiring path, the surrounding n grid is set as a wiring prohibited area (step S47), and the maze method is terminated.
If it is determined in step S39 that no other target point exists, the process proceeds to step S45.

  Next, the wiring process in the detailed automatic rewiring process in the package will be described with reference to FIGS. First, the detailed automatic rewiring processing means 30b in the package reads the board information from the layout information storage means 21, grids all the board layers based on the board information (step S48), and sets a wiring prohibited area (step S48). S49).

  Next, based on the data stored in the layout information storage means 21 and the data obtained from the external terminal identification means 23, the first semiconductor chip capable of sharing functions according to the rules stored in the wiring condition storage means 22 The first wiring pattern 10 that is electrically connected to the connection terminal 4 or the connection terminal of the first semiconductor chip 4 and the third through hole 9c are connected via the third wiring pattern 15 and A net is acquired such that the external terminal 2 that is not electrically connected to the connection terminal of the first semiconductor chip 4 and the fourth through hole 9d are connected via the fourth wiring pattern 16, and the acquired net is wired by the maze method. (Step S50). The maze method in step S50 will be described later.

  Next, it is determined whether the result obtained in step S50 can be wired (step S51). If it is determined in step S51 that wiring cannot be performed, “Warning: NetXXX cannot be wired” is displayed (step S52), and the process returns to step S50 to perform wiring processing for the next net (step S53).

  If it is determined in step S50 that the next net is routed by the maze method and it is determined in step S51 that routing can be performed, it is further determined whether all nets have been routed (step S54). When the wiring process is completed, the wiring process is terminated. If all the nets have not been routed, the process returns to step S50 to perform the next net routing process (step S53).

Next, the maze method in step S50 will be described with reference to FIGS.
First, the third through hole 9c or the fourth through hole 9d is set as a start point (step S55).

Next, the target point is the first wiring pattern 10 corresponding to the third through hole 9c or the fourth through hole 9d that is the start point, the connection terminal of the first semiconductor chip 4, or the external terminal 2. (Step S56). There may be a plurality of target points.
All grid values are initialized (step S57). Further, the grid value at the start point is set to “0” (step S58), and the current number is set to 0 (step S59).

  A value of current number + 1 is set in an adjacent grid in the same layer as the acquired grid (step S60), and a current number + via cost value is set in a grid that is in contact with the acquired grid across the layer (step S61). . Note that grids that already have values are not overwritten.

  Next, it is determined whether a value has been set for the grid at the target location (step S62). If it is determined in step S62 that a value has been set for the grid at the target location, the backtrace processing in the maze method described above is performed so that the distance from the target location to the start location is reduced. (Step S63). Note that backtrace processing is performed so that the number of bends in the path is reduced. The route acquired in step S63 is set as the wiring route of the net (step S64).

  Next, it is determined whether another target point exists (step S65). If it is determined in step S65 that another target point exists, the next target point is acquired (step S66). Next, all grids of the wiring route previously wired are set as start points (step S67), and the process returns to step S57.

If it is determined in step S62 that no value is set for the grid at the target location, it is further determined whether a value could not be set for any grid (step S68).
If it is determined in step S68 that no value can be set for any grid, the current current number is set to +1 (step S69), and the process returns to step S60.

  If no value can be set for any grid in step S68, “Error: Net xxx cannot be wired” is displayed (step S70), and it is determined whether wiring to all targets has been completed normally. (Step S71).

In step S71, if the wiring to all the targets is not completed normally, the maze method is terminated. Further, when the wiring to all the targets is completed normally, the obtained wiring path is made into a line figure (step S72). In addition, when there is a wiring route straddling a plurality of substrate layers, a via cell is arranged at a straddling location. Further, regarding the grid of the wiring path, the surrounding n grid is set as a wiring prohibited area (step S73), and the maze method is terminated.
If it is determined in step S65 that no other target point exists, the process proceeds to step S71.

It is a top view which shows an example of the semiconductor device in 1st Embodiment for implementing this invention. It is sectional drawing of the arrow AA of the semiconductor device shown in FIG. 1 in case the 2nd semiconductor chip on a sealing material connects to the 1st wiring pattern on a board | substrate through a 1st through-hole. . (A) is sectional drawing of the arrow AA of the semiconductor device shown in FIG. 1 in case the 2nd semiconductor chip on a sealing material connects to an external terminal via a 2nd through-hole, (b). Is an explanatory view showing a state in which the through hole is connected to an external terminal, and (c) is a cross-sectional view showing an example of PoP in which the semiconductor device shown in FIG. 1 is arranged on another package. It is a top view which shows the other example of the semiconductor device in 1st Embodiment for implementing this invention. 4A shows the semiconductor device shown in FIG. 4 when the second semiconductor chip on the sealing material is connected to the first semiconductor chip via the third through hole and the third wiring pattern on the substrate layer. A cross-sectional view taken along the line B-B in FIG. 5B shows a case where the second semiconductor chip on the sealing material is connected to the external terminal through the fourth through hole and the fourth wiring pattern on the substrate layer. FIG. 5 is a cross-sectional view taken along line CC of the semiconductor device shown in FIG. 4. It is a figure which shows the structure of the wiring assistance apparatus in 1st Embodiment for implementing this invention. FIG. 7 is an explanatory view showing an example of wiring conditions stored in the wiring condition storage means in the wiring support apparatus shown in FIG. 6, (a) is an explanatory view before avoiding the intersection of the second wiring patterns; ) Is an explanatory diagram showing a means for avoiding the intersection of the second wiring patterns, and (c) is an explanatory diagram showing another means for avoiding the intersection of the second wiring patterns. It is explanatory drawing for demonstrating the maze method used for a detailed automatic wiring process means among the wiring assistance apparatuses shown in FIG. It is explanatory drawing for demonstrating the continuation of the maze method shown in FIG. It is explanatory drawing for demonstrating the continuation of the maze method shown in FIG. It is explanatory drawing for demonstrating the continuation of the maze method shown in FIG. It is a flowchart which shows the whole flow of the wiring method in 1st Embodiment for implementing this invention. It is a flowchart which shows the flow of the whole of an outline automatic wiring process among the whole flows of the wiring method shown in FIG. 12 is a flowchart showing a continuation of the flowchart shown in FIG. 11. It is a flowchart which shows the flow of a detailed automatic wiring process on a package among the whole flows of the wiring method shown in FIG. It is a flowchart which shows the flow of a maze method among the whole flows of the detailed automatic wiring process on a package shown in FIG. It is a flowchart which shows the continuation of the flowchart shown in FIG. It is a flowchart which shows the continuation of the flowchart shown in FIG. It is a flowchart which shows the flow of the package detailed automatic rewiring process among the whole flows of the wiring method shown in FIG. It is a flowchart which shows the flow of a maze method among the whole flows of the detailed automatic rewiring process in a package shown in FIG. FIG. 21 is a flowchart showing a continuation of the flowchart shown in FIG. 20. FIG. It is a flowchart which shows the continuation of the flowchart shown in FIG.

Explanation of symbols

1 Substrate
1a Bottom surface
1b Top surface
2 External terminal
2a ball
2b Bump
3 SiP
4 First semiconductor chip
5 Sealing material
5a Top surface
5b side view
6 Second semiconductor chip
6a wire
6b Bond Finger
7 Second wiring pattern
8 Circuit elements
9 Through hole
9a First through hole
9b Second through hole
9c 3rd through hole
9d 4th through hole
10 First wiring pattern
11 Conductive material
12 External wiring pattern
13 Virtual terminal
14 Wiring prohibited area
15 Third wiring pattern
16 Fourth wiring pattern
21 Layout information storage means
22 Wiring condition storage means
23 External terminal identification means
24 First through hole generating means
25 Second through hole generating means
26 Outline automatic wiring processing means
27 Parameter setting means
28 Display device
29 Input device
30 Detailed automatic wiring processing means
31 Output means 100 Wiring support device 200 Wiring design CAD device

Claims (8)

A wiring method for a semiconductor device, comprising: a substrate on which external terminals are disposed; a first semiconductor chip mounted on an upper surface of the substrate; and a sealing material that seals the first semiconductor chip on the substrate. In
A first position for setting a position of a connection terminal of a circuit element or a second semiconductor chip mounted on the sealing material and a position of a through hole penetrating from an upper surface of the sealing material to an upper surface or a lower surface of the substrate. Steps,
A second step of assigning a net between the connection terminal of the circuit element or the second semiconductor chip and the through hole, or between the connection terminal of the circuit element and the connection terminal of the second semiconductor chip;
There are a plurality of nets assigned in the second step, and there are intersecting nets among the plurality of nets, and at least one of the intersecting nets is the circuit element or the second net. A net allocated between the connection terminal of the semiconductor chip and the through hole, and the position of the through hole in the one net is changed so that the one net does not cross the other net. And the steps
With reference to the net, the connection terminal of the circuit element or the second semiconductor chip is a start point, the through hole corresponding to the start point or the connection terminal of the circuit element or the second semiconductor chip is a target point, A fourth step of setting the grid value from the start point to the target point by the maze method, and performing the backtrace process to set the net wiring route,
A method for wiring a semiconductor device, comprising: In the semiconductor device wiring method according to claim 1,
The through hole that changes the position in the third step connects the second wiring pattern disposed on the top surface of the sealing material and the first wiring pattern disposed on the top surface of the substrate. A wiring method of a semiconductor device, wherein the position of the first through hole is on the corresponding first wiring pattern. In the wiring method of the semiconductor device according to claim 2,
A wiring method of a semiconductor device, wherein one net in the third step has a wiring length longer than that of the other net in the third step. A wiring method for a semiconductor device, comprising: a substrate on which external terminals are disposed; a first semiconductor chip mounted on an upper surface of the substrate; and a sealing material that seals the first semiconductor chip on the substrate. In
A first position for setting a position of a connection terminal of a circuit element or a second semiconductor chip mounted on the sealing material and a position of a through hole penetrating from an upper surface of the sealing material to an upper surface or a lower surface of the substrate. Steps,
A second step of assigning a net between the connection terminal of the circuit element or the second semiconductor chip and the through hole, or between the connection terminal of the circuit element and the connection terminal of the second semiconductor chip;
A plurality of nets allocated in the second step, and there are crossing nets among the plurality of nets, and the crossing is performed without changing a position of a through hole in the crossing nets. A third step of changing one of the nets to a net that wraps around so as not to cross the other net;
With reference to the net, the connection terminal of the circuit element or the second semiconductor chip is a start point, the through hole corresponding to the start point or the connection terminal of the circuit element or the second semiconductor chip is a target point, A fourth step of setting the grid value from the start point to the target point by the maze method, and performing the backtrace process to set the net wiring route,
A method for wiring a semiconductor device, comprising: In the wiring method of the semiconductor device according to claim 4,
One net in the third step consists of a first net on the top surface of the sealing material and a second net on the side surface of the sealing material,
The first net and the second net are connected via virtual terminals at the boundary between the upper surface and the side surface of the sealing material,
The method of wiring a semiconductor device, wherein the virtual terminal is a start point or a target point in the fourth step. In the wiring method of the semiconductor device according to any one of claims 1 to 5,
A second wiring pattern disposed on an upper surface of the sealing material,
Among the through holes in the net assigned in the second step, a plurality of second wiring patterns respectively connected to connection terminals that can share the function of the connection elements of the circuit element or the second semiconductor chip. Unify each through hole in the net into one through hole,
The step of changing the plurality of nets having the respective through holes assigned in the second step as target points to the nets having the unified through holes as target points is the second step and the first step. A wiring method for a semiconductor device, comprising: In the wiring method of the semiconductor device according to claim 6,
Of the through holes in the net assigned in the second step, there are a plurality of first through holes connected to the same first wiring pattern disposed on the upper surface of the substrate,
A first one of the plurality of first through holes connected to the same first wiring pattern is a net having a plurality of first through holes connected to the same first wiring pattern as a target point. A step of selecting a through hole and changing to a net having the selected first through hole as a target point, between the second step and the third step. Wiring method. In the wiring method of the semiconductor device according to any one of claims 1 to 7,
A first wiring pattern disposed on the top surface of the substrate, a second wiring pattern disposed on the top surface of the sealing material,
The through hole in the first step is
A first through hole at a position on the upper surface of the sealing material corresponding to the first wiring pattern connected to a connection terminal that can share the functions of the first semiconductor chip and the circuit element or the second semiconductor chip;
A second through hole at a position on the upper surface of the sealing material corresponding to an external terminal not conducting to the connection terminal of the first semiconductor chip among the external terminals having no wiring pattern on the substrate above;
A wiring method for a semiconductor device, characterized in that: