JP4747015B2 - COMMUNICATION TERMINAL DEVICE AND ITS CONTROL METHOD - Google Patents

Description

  The present invention relates to a communication terminal device and a control method thereof, and more particularly to a communication terminal device that performs communication with a center side device via a control channel and a control method of such a communication terminal device. .

  Communication terminal devices include modem devices that modulate / demodulate signals. FIG. 6 shows a configuration of a conventional modem device. This modem device is configured as an xDSL modem 50, and includes an xDSL device 52, a CPU 53, a FLASH ROM 54, a RAM 55, a CPU peripheral device 56, an FPGA 57, a PHY device 58, and a serial / parallel converter 59. The CPU 53 is connected to each unit in the xDSL modem 50 via the CPU bus 223, and controls each unit and sets a device.

  The FPGA 57 has a CPU interface and is connected to the CPU 53 via the CPU bus 223. The FLASH ROM 54 stores data for programming the FPGA and embedded software of the CPU 53. In the xDSL modem 50, the program of the FPGA 57 when the apparatus is activated is configured to be executed by the CPU 53. The PHY device 58 has an MDIO interface 220 that is a serial interface, and is connected to the CPU bus 223 via the serial / parallel conversion unit 59. Settings and control of the PHY device 58 are executed by the CPU 53. The

  The xDSL device 52 performs control data communication performed with the center side device. Processing of control data received by the xDSL device 52 is executed by the CPU 53. For example, when the program data of the FPGA 57 stored in the FLASH ROM 54 is updated according to the data transmitted from the center side device, the CPU 53 extracts the ROM data included in the control data, and the extracted ROM data is Write to the FLASH ROM 54 via the CPU bus 223.

  Control of an xDSL modem using a CPU as described above is relatively easy to implement and has been widely adopted (see, for example, Patent Document 1 and Patent Document 2). However, when controlling the FLASH ROM 54 and the like by processing the CPU 53 with embedded software, there is a problem that the number of parts increases due to the CPU and its peripheral devices, leading to an increase in cost. In addition, it is necessary to develop software for operating the CPU 53, and this part also has a problem that the cost increases.

  For xDSL modems, devices that do not require CPU control have been developed. In such a type of xDSL modem, the xDSL device has an MDIO interface, and the xDSL device can be directly controlled from the center side apparatus using the eoc control channel of the xDSL line. However, even in this case, in order to transfer a large amount of data from the center side device, such as FPGA program data used by the modem, to the modem and execute the update process of the ROM data, a CPU is still necessary. There was a problem that peripheral devices could not be reduced.

  As an xDSL modem capable of updating FPGA program data without mounting a CPU, there is an xDSL modem 50a configured as shown in FIG. The xDSL modem 50 a includes a FLASH ROM control circuit 60 that controls the FLASH ROM 54 via the FLASH ROM interface 221. The FLASH ROM control circuit 60 is connected to the FPGA 57 via the FPGA interface 222, and programs the FPGA 57 in accordance with the program data of the FPGA 57 read from the FLASH ROM 54. The FLASH ROM control circuit 60 has a serial port 224 for connecting to the external terminal 61, and can update program data stored in the FLASH ROM 54 in accordance with the ROM data transferred from the external terminal 61.

JP 2000-155684 A JP 2003-37685 A

  In the xDSL modem 50a having the configuration shown in FIG. 7, the cost is reduced by not requiring a CPU. However, when updating the data in the FLASH ROM 54, the user needs to download and prepare ROM update data in advance. There is a problem that the procedure is complicated. In addition, whether or not to update the FLASH ROM of the modem delivered to the user and installed in the home depends on the user, and there is a problem that the FLASH ROM update cannot be controlled by the center side device. is there.

  The present invention provides a communication terminal device and a control method therefor that can solve the above-mentioned problems of the prior art and can control a nonvolatile memory in the communication terminal device from a center side device without requiring a CPU.

To achieve the above object, the communication terminal apparatus of the present invention is a communication communication terminal apparatus that performs using the control channel between the center side device, based on the signal received using the control channel Generating an internal signal of a predetermined format including the address of the device to be accessed , outputting the generated internal signal, and first and second addresses are set, and the internal signal generator outputs When the internal signal is received and the address included in the internal signal is the first address, the nonvolatile memory is controlled based on the internal signal, and the address included in the internal signal is the first address. If a second address, characterized by comprising a memory control means for controlling the data registers held under the internal signal.

  In the communication terminal device of the present invention, the memory control means interprets a control instruction for the nonvolatile memory transmitted from the center side device via the control channel, and controls the nonvolatile memory. In this way, the non-volatile memory in the communication terminal device can be controlled from the center side device without using the CPU, and the number of parts can be reduced and the cost can be reduced as compared with the case where the CPU is used. Can be suppressed.

  In the communication terminal device according to the present invention, the memory control means can employ a configuration in which the nonvolatile memory is rewritten in accordance with data included in the internal signal. In this case, for example, the data in the nonvolatile memory can be updated to the latest data by transmitting update data of the data in the nonvolatile memory from the center side device and rewriting the nonvolatile memory.

  In the communication terminal device according to the present invention, the nonvolatile memory has a first block used for operation and a second block for backup, and the memory control means stores the data included in the internal signal. A configuration may be employed in which data is written to the second block, data is written to the second block, and then data of the second block is copied to the first block. In this case, even if a power interruption or a line interruption occurs during rewriting of the nonvolatile memory, there is no influence on the data of the first block, so there is no problem in operation.

  In the communication terminal device of the present invention, a configuration in which the center side device can refer to a register in the communication terminal device via the control channel and the internal signal generation unit can be adopted. When controlling the nonvolatile memory from the center side device, it is possible to control the nonvolatile memory in the communication terminal device from the center side device by transmitting a command to the memory control means in the same procedure as the register access. .

  In the communication terminal device of the present invention, the internal signal is a signal for register access in the communication terminal device, and the memory control means receives the internal signal via a communication line for register access. Can be adopted. In many cases, the communication terminal device is configured to be able to access the registers of each unit in the communication terminal device from the center side device via a control channel. By inputting a control command for the nonvolatile memory using such a communication line for register access to the memory control means, the nonvolatile memory in the communication terminal device can be controlled from the center side device.

  In the communication terminal device of the present invention, the internal signal is an access target among a read or write access type, an address part that specifies an address of a device to be accessed in the communication terminal device, and a register held by the device. It is possible to adopt a configuration including a register designating unit that designates the register to be. For example, the MDIO signal format defined in IEEE 802.3 can be used as the internal signal.

  In the communication terminal apparatus according to the present invention, the memory control means may employ a configuration for determining control of the nonvolatile memory based on data included in the register designating unit. In this case, the center side device inputs an internal signal including a desired control command to the register designating unit via the control channel and the internal signal generating unit to the memory control unit, so that the nonvolatile memory has a desired value. Control can be executed.

The communication terminal apparatus of the present invention, prior SL memory control means, when the address portion of the internal signal received designating the first address, based on the data contained in the register specifying portion, the non-volatile When the control for the memory is determined and the address designating unit designates the second address, based on the data contained in the register designating unit, the data of the register held is read or the data is written to the register Configuration can be adopted. In this case, both the control of the nonvolatile memory and the access to the register in the memory control means can be realized by properly using the first address and the second address.

  In the communication terminal device of the present invention, the memory control means decodes the internal signal, interprets a command for the nonvolatile memory issued by the center side device, and according to a decoding result of the decoder circuit, A command sequence control circuit for determining a control command for the nonvolatile memory, a control command generation circuit for outputting the control command determined by the command sequence control circuit to the nonvolatile memory, and the command sequence control circuit for writing data When a control command to be indicated is determined, a configuration including a data write control circuit for writing update data included in the internal signal into the nonvolatile memory can be employed.

  In the communication terminal device of the present invention, the memory control means further includes a command register that stores a command interpreted by the decoder circuit and a completion flag indicating that the command is completed, and the command sequence control circuit includes: A configuration in which the completion flag is set when the output of the control command by the control command generation circuit or the data writing by the data write control circuit is completed can be employed. In this case, the center side device can confirm the completion of the issued control command by referring to the command register.

  In the communication terminal apparatus according to the present invention, the memory control unit may further include a checksum calculation unit that calculates a checksum of the update data and a data register that holds a checksum calculation result. In this case, the center side device can confirm whether or not the data has been correctly updated by referring to the data register.

  In the communication terminal device of the present invention, the nonvolatile memory can employ a configuration for storing data for programming an FPGA that performs communication control processing. In this case, when the data for programming the FPGA is updated, the update data is transmitted from the center side device, and the content of the nonvolatile memory is rewritten, whereby the program data of the FPGA can be updated to the latest data. .

Control method of a communication terminal of the present invention is a method for controlling a communication terminal apparatus that performs communication using a control channel between the center side device, from the center side device, the communication via the control channel comprising the steps of: issuing a command for controlling the non-volatile memory or register in the terminal device, in accordance with the command, the step of generating an internal signal of a predetermined format including an address of the device to be accessed, and outputs the generated the internal signals When the internal signal is received and the address included in the internal signal is a first address, the nonvolatile memory is controlled based on the internal signal, and the address included in the internal signal is a second address If an address, especially in that it comprises the steps of: controlling the data registers held under the internal signal To.

  In the communication terminal device control method of the present invention, the nonvolatile memory in the communication terminal device is controlled based on a command from the center side device. For the transmission of the command from the center side device, a signal used when referring to the register from the center side device in the communication terminal device can be used. By controlling the non-volatile memory from the center side device, the communication terminal device does not need to have a CPU, and the cost is reduced by reducing the number of parts of the communication terminal device compared to the prior art that requires a CPU. Can do.

In the communication terminal device control method of the present invention, the center side device refers to a register in the communication terminal device through the control channel after issuing a command for controlling the nonvolatile memory, and issues the issued command. It is possible to adopt a configuration for confirming the completion of. In this case, after confirming the completion of the command, the center side device may issue the next command.

  In the control method for a communication terminal device according to the present invention, the center side device transmits the update data of the nonvolatile memory via the control channel, and the transmitted update data is written to the nonvolatile memory. Can be adopted. In this case, the non-volatile memory in the communication terminal device can be rewritten with the update data by the center side device.

  In the communication terminal control method of the present invention, the non-volatile memory includes a first block for operation and a second block for backup, and the center side device includes the second block. After the update data is written into the second block, the second block data can be copied to the first block. In this case, even if a power interruption or line interruption occurs during rewriting to the nonvolatile memory, there is no effect on the data in the first block, so there is no problem in the operation of the communication terminal apparatus.

  In the communication terminal control method of the present invention, the center side apparatus correctly transmits the update data by referring to the checksum calculation result of the update data calculated in the communication terminal apparatus via the control channel. It is possible to adopt a configuration for determining whether or not it has been completed.

  In the communication terminal device of the present invention, the memory control means interprets a control instruction for the nonvolatile memory transmitted from the center side device via the control channel, and controls the nonvolatile memory. In the communication terminal device control method of the present invention, the nonvolatile memory in the communication terminal device is controlled based on a command from the center side device. In this way, the non-volatile memory in the communication terminal device can be controlled from the center side device without using the CPU, and the number of parts can be reduced and the cost can be reduced as compared with the case where the CPU is used. Can be suppressed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows the configuration of a communication apparatus according to an embodiment of the present invention. This communication apparatus is configured as an xDSL modem 10 and includes an xDSL device 12, an FPGA 13, a PHY device 14, a FLASH ROM 15, and a FLASH ROM control circuit 16. In xDSL lines such as ADSL and VDSL, a control channel called eoc (embedded operating channel) is prepared in addition to a communication channel for user data (user packets). User data and control data can be communicated simultaneously. Control data communication by eoc is used in data communication between the center side device and the modem device using a unique protocol in the standard specifications of ANSI and ITU-T. can do.

  The xDSL device 12 includes an xDSL termination unit 101 that terminates an xDSL line, and a MAC unit 102 that terminates a user packet communicated on the xDSL line. Further, the xDSL device 12 has an MDIO interface 120 as a control system interface for controlling the FPGA 13 and the PHY device 14 in the subsequent stage. The MAC unit 102 (internal signal generation unit) of the xDSL device 12 converts a signal received via the eoc control channel into an MDIO signal (internal signal) of a predetermined format, and the converted MDIO signal is transmitted via the MDIO interface 120. Input to each part in the modem device. With this mechanism, each unit in the modem device can be directly controlled from the center side device using the eoc control channel without requiring CPU control.

  An FPGA (Field Programmable Gate Array) 13 is a circuit that realizes functions required for a modem device, such as QoS processing for user packet transmission priority control, and settings required for operation include the eoc control channel and the MDIO of the xDSL device 12. This is performed by the center side device via the interface 120. The PHY device 14 realizes an Ethernet (registered trademark) layer 1 function. Settings necessary for the operation of the PHY device 14 are also performed by the center side device via the eoc control channel and the MDIO interface 120 of the xDSL device 12. The xDSL device 12, the FPGA 13, and the PHY device 14 have main signal system interfaces 111 and 112 for transferring user packets communicated with the center side device to subsequent devices, respectively.

  The FLASH ROM 15 stores data for programming the FPGA 13. The FLASH ROM control circuit 16 is connected to the FPGA 13 via the FPGA interface 122 and is connected to the FLASH ROM 15 via the FLASH ROM interface 121. The FLASH ROM control circuit 16 has a function of reading data from the FLASH ROM 15 and programming the FPGA 13 when the apparatus is activated. The FLSAH ROM control circuit 16 includes an MDIO interface 120, and has a function of rewriting data in the FLASH ROM 15 with commands and data received from the MDIO interface 120.

  The programming method of the FPGA 13 by the eoc control channel, the MDIO interface 120 of the xDSL device, and the FLASH ROM control circuit 16 is well known and is not directly related to the present invention.

  FIG. 2 shows an MDIO signal format defined in IEEE 802.3. The MDIO interface 120 is configured as a serial interface for reading / writing the registers of each unit in the modem device from the MAC unit 102 of the xDSL device 12. For the MDIO signal format, an OP code 201 for designating a read operation or a write operation, a PHY address 202 for designating each unit in the modem device connected to the MAC unit 102, and a register number included in each unit in the modem device are designated. Register address 203 to be used, a turnaround 204 for securing processing time for each unit in the modem device to output register data to the MDIO interface 120 in the case of a read operation, and a data area 205 for a register read / write operation Consists of.

  Here, in order to update the data in the FLASH ROM 15 via the MDIO interface 120, it is necessary to transfer a large amount of ROM data from the MAC unit 102 to the FLASH ROM control circuit 16, and after erasing the FLASH ROM 15 or updating the data. It is difficult to update ROM data via MDIO with a simple register access method, such as requiring reprogramming of the FPGA 13. Therefore, in this embodiment, the register address 203 in the MDIO signal format of the write operation for the FLASH ROM control circuit 16 is used as an instruction code for a command from the MAC unit 102 to the FLASH ROM control circuit 16. Further, a part of the 16-bit data area 205 may be used for transferring parameters necessary for the instruction code and for extending the instruction code. In this case, since the register address 203 is 5 bits, only a maximum of 32 types of instruction codes can be specified. However, by using the upper several bits of the data area 205 as a part of the instruction code, more than 32 types of instruction codes can be specified. , And can be transferred to the FLASH ROM control circuit 16.

  Further, two PHY addresses are assigned to the FLASH ROM control circuit 16. One of the PHY addresses to be assigned is used for transferring an instruction code. The other PHY address is used to designate a register that can be read / written from the MAC unit 102 included in the FLASH ROM control circuit 16 by a normal MDIO register access operation. In this case, the FLASH ROM control circuit 16 refers to the PHY address 202 included in the MDIO signal, so that the received MDIO signal is a signal for transferring the instruction code or the read / write of the register is performed. It is possible to determine whether the signal is for the purpose.

  FIG. 3 shows a detailed configuration of the FALSH ROM control circuit 16. The FLASH ROM control circuit 16 includes an MDIO termination circuit 301, a decoder circuit 302, an MDIO data register 303, an MDIO command register 304, an MDIO command sequence control circuit 305, a checksum operation circuit 306, a ROM data program control circuit 307, and a FLASH ROM control command. A generation circuit 308, an FPGA program control circuit 309, a FLASH ROM interface circuit 310, and an FPGA interface circuit 311 are provided.

  The MDIO termination circuit 301 terminates the MDIO interface 120. The decoder circuit 302 decodes the received MDIO signal. At this time, referring to the PHY address 202 (FIG. 2), it is identified whether the operation is a normal register access operation or a command operation. The MDIO data register 303 and the MDIO command register 304 are registers that can be referred to by the center side device by the MDIO register read operation. The MDIO data register 303 holds information that needs to be notified to the center side device. The MDIO command register 304 holds a command issued by the center side device and a flag indicating whether or not the command is completed.

  The MDIO command sequence control circuit 305 performs execution management of commands received via the MDIO interface 120. The checksum calculation circuit 306 calculates the checksum of the ROM data received via the MDIO interface 120. The FLASH ROM control command generation circuit 308 generates ROM control commands necessary for actually controlling the FLASH ROM 15 such as a sector erase command of the FLASH ROM 15 and a continuous program command. The ROM data program control circuit 307 writes ROM data to the FLASH ROM 15. The FPGA program control circuit 309 reads the data in the FLASH ROM 15 and programs the FPGA 13. The FLASH ROM interface circuit 310 implements an interface 121 with the FLASH ROM 15. The FPGA interface circuit 311 implements an interface 122 with the FPGA 13.

  FIG. 4 shows an operation procedure when the FLASH ROM 15 of the xDSL modem 10 is rewritten. When updating the ROM data, the center side device issues an update start command to the xDSL modem 10 via the control channel (step S1). This update start command is converted into an MDIO format signal by the MAC unit 102 and input to the FLASH ROM control circuit 16 via the MDIO interface 120. The FLASH ROM control circuit 16 uses the decoder circuit 302 to decode the received MDIO signal. The decoder circuit 302 interprets it as an update start command based on the PHY address 202 and the register address 203 (FIG. 2) of the received MDIO signal, and transfers the update start command to the MDIO command sequence control circuit 305 (step S2).

  When the update start command is transferred, the MDIO command sequence control circuit 305 clears the command completion flag in the MDIO command register 304 and writes the transferred update start command in the MDIO command register 304 (step S3). Further, the FLASH ROM control command generation circuit 308 is instructed to output to the FLASH ROM 15 a sequence (sequence) of ROM control commands necessary for starting update, such as ROM data erasure and continuous program (step S4). . When the output of the ROM control command by the FLASH ROM control command generation circuit 308 is completed, the MDIO command sequence control circuit 305 sets a flag indicating completion of processing in the MDIO command register 304 (step S5).

  The center side device reads the value of the MDIO command register 304 by the read operation of the MDIO register, checks whether the command completion flag is set, and confirms the completion of the update start command. When the center side device confirms the completion of the command, it issues a ROM data transmission command via the control channel (step S6). The ROM data transmission command is converted into an MDIO format signal by the MAC unit 102 and input to the FLASH ROM control circuit 16 via the MDIO interface 120. At this time, an instruction code (command) indicating transmission of ROM data is given to the register address 203 of the MDIO signal received by the FLASH ROM control circuit 16, and update data is given to the data area 205.

  The MDIO command sequence control circuit 305 resets the command completion flag of the MDIO command register 304, and writes the ROM data transmission command received via the decoder circuit 302 into the MDIO command register 304 (step S7). Thereafter, since the received command is ROM data transmission, the ROM data program control circuit 307 is instructed to write the ROM update data transmitted together with the command (step S8). The ROM data program control circuit 307 programs update data in the FLASH ROM 15 (step S9). At this time, the checksum calculation circuit 306 calculates the checksum of the ROM update data, and stores the checksum calculation result in the MDIO data register 303 (step S10).

  FIG. 5 shows an image diagram of ROM data of the FLASH ROM 15. In the FLASH ROM 15, program data of the FPGA 13 is stored in each of the two blocks 501 and 502. Among these, the data stored in the block 501 is data used when the FPGA 13 is programmed, and the block 502 corresponds to backup data. The update data program in step S10 is performed for the backup block 502. In this way, the backup block 502 is used for data communication using the control channel between the center side device and the modem device, and protects against an error during communication by a communication protocol such as retransmission processing when an error is detected. This is because, however, it is not possible to cope with a situation such as the modem being turned off during the ROM data update, and therefore it is necessary to backup and hold the ROM data on the modem device side.

  The center side device and the FLASH ROM control circuit 16 execute the ROM data transfer by repeating the processes from the transmission of the ROM update data to the FLASH ROM 15 program and the checksum calculation. The center side device can determine the checksum calculation result and the execution state of the update data transfer by checking the MDIO data register 303 and the MDIO command register 304 by the read operation of the MDIO register. When the transmission of all ROM data is completed and the program of the FLASH ROM 15 is successful, the center side device issues a transmission completion command (step S11). This transmission completion command is converted into an MDIO format signal and input to the FLASH ROM control circuit 16.

  If the ROM data has not been updated correctly, the center device issues an update failure command and instructs the FLASH ROM control circuit 16 to interrupt the data update. If the MDIO command sequence control circuit 305 does not receive the ROM data transmission command or the update completion command within a predetermined time after the ROM data update is started, the data update process is interrupted. The data update interruption process is executed when the MDIO command sequence control circuit 305 causes the FLASH ROM control command generation circuit 308 to output a program end command to the FLASH ROM 15.

  When the MDIO command sequence control circuit 305 receives the update completion command via the decoder circuit 302, the ROM data program control circuit 307 copies the ROM data programmed in the backup block 502 (FIG. 5) to the block 501. (Step S12). In accordance with this instruction, the ROM data program control circuit 307 copies the data in the block 502 to the block 501 (step S13). Thereafter, the FPGA 13 is reprogrammed using the data stored in the block 501.

  In this embodiment, the update data of the FLASH ROM 15 is transmitted from the center side device to the xDSL modem 10 using the control channel of the xDSL line. In the xDSL modem 10, the received update data is converted into the MDIO signal format by the xDSL device 12 and then transferred to the FLASH ROM control circuit 16. By doing so, it is possible to execute ROM data rewriting of the FLASH ROM 15 in the modem device from the center device side without using the CPU.

  In this embodiment, the register address 203 (FIG. 2) in the MDIO signal format is used as an instruction code area from the MAC unit 102 toward the PHY device 14. Thereby, a large amount of data can be transferred from the center side apparatus to the xDSL modem 10, and other accompanying processing can be instructed. In this embodiment, the checksum operation circuit 306 checks whether the ROM update has been performed correctly, and stores the check result in the MDIO data register 303. The center side device can confirm the checksum calculation result by the MDIO register read operation, and can make the updated data valid in the FLASH ROM 15 only when the update is performed correctly.

  Although the present invention has been described based on the preferred embodiments, the communication terminal device and the control method of the present invention are not limited to the above embodiments, and various modifications can be made from the configuration of the above embodiments. Further, modifications and changes are also included in the scope of the present invention.

The block diagram which shows the structure of the communication apparatus of one Embodiment of this invention. The figure which shows the signal format of MDIO. The block diagram which shows the detailed structure of a FALSE ROM control circuit. The flowchart which shows the operation | movement procedure at the time of rewriting of FLASH ROM of a xDSL modem. The figure which shows the image of ROM data of FLASH ROM. The block diagram which shows the structure of the conventional modem apparatus which has CPU. The block diagram which shows the structure of the conventional modem apparatus which does not have CPU.

Explanation of symbols

10: Communication device (xDSL modem)
12: xDSL device 13: FPGA
14: PHY device 15: FLASH ROM
16: FLASH ROM control circuit 101: xDSL termination unit 102: MAC unit 111, 112: main signal interface 120: MDIO interface 121: FLASH ROM interface 122: FPGA interface 301: MDIO termination circuit 302: decoder circuit 303: MDIO data register 304: MDIO command register 305: MDIO command sequence control circuit 306: checksum operation circuit 307: ROM data program control circuit 308: FLASH ROM control command generation circuit 309: FPGA program control circuit 310: FLASH ROM interface circuit 311: FPGA interface circuit

Claims (17)

A communication communication terminal apparatus that performs using the control channel between the center side device,
An internal signal generation unit that generates an internal signal of a predetermined format including an address of a device to be accessed based on a signal received using the control channel, and outputs the generated internal signal;
When the first and second addresses are set, the internal signal output from the internal signal generation unit is received, and the address included in the internal signal is the first address, based on the internal signal Memory control means for controlling a nonvolatile memory and , when the address included in the internal signal is the second address, controlling data of a register held based on the internal signal. A communication terminal device.   The communication terminal apparatus according to claim 1, wherein the memory control unit rewrites the nonvolatile memory according to data included in the internal signal.   The nonvolatile memory has a first block used for operation and a second block for backup, and the memory control means writes the data included in the internal signal to the second block, The communication terminal device according to claim 2, wherein after the data is written to the second block, the data of the second block is copied to the first block.   The communication terminal device according to claim 1, wherein the center side device can refer to a register in the communication terminal device via the control channel and the internal signal generation unit.   The internal signal is a signal for register access in a communication terminal device, and the internal signal is input to the memory control unit via a communication line for register access. The communication terminal device according to any one of the above.   The internal signal is a read or write access type, an address part that specifies the address of the device to be accessed in the communication terminal device, and a register specification that specifies a register to be accessed among the registers held by the device The communication terminal device according to claim 5, further comprising:   The communication terminal apparatus according to claim 6, wherein the memory control unit determines control of the nonvolatile memory based on data included in the register specifying unit. Before SL memory control means, when the address portion of the internal signal received designating the first address, based on the data contained in the register designating unit determines a control for said non-volatile memory, wherein 7. The communication according to claim 6, wherein when the address designating unit designates the second address, based on the data contained in the register designating unit, the data of the register held is read or the data is written to the register. Terminal device. The memory control means;
A decoder circuit for decoding the internal signal and interpreting a command for the nonvolatile memory issued by the center side device;
A command sequence control circuit for determining a control command for the nonvolatile memory according to a decoding result of the decoder circuit;
A control command generation circuit for outputting a control command determined by the command sequence control circuit to the nonvolatile memory;
9. The data write control circuit according to claim 1, further comprising: a data write control circuit that writes update data included in the internal signal to the nonvolatile memory when the command sequence control circuit determines a control command indicating data write. The communication terminal device described.   The memory control means further includes a command register for storing a command interpreted by the decoder circuit and a completion flag indicating that the command is completed, and the command sequence control circuit includes a control command generated by the control command generation circuit. The communication terminal device according to claim 9, wherein the completion flag is set when the data output or the data writing by the data writing control circuit is completed.   The communication terminal apparatus according to claim 9 or 10, wherein the memory control unit further includes a checksum calculation unit that calculates a checksum of the update data, and a data register that holds a calculation result of the checksum.   The communication terminal device according to claim 1, wherein the nonvolatile memory stores data for programming an FPGA that performs communication control processing. A method of controlling a communication terminal apparatus that performs communication using a control channel between the center side device,
Issuing a command for controlling a non-volatile memory or a register in the communication terminal device from the center side device via the control channel;
Generating an internal signal of a predetermined format including an address of a device to be accessed according to the command, and outputting the generated internal signal;
When the internal signal is received and the address included in the internal signal is a first address, the nonvolatile memory is controlled based on the internal signal, and the address included in the internal signal is a second address. If it is, control method of a communication terminal apparatus characterized by comprising the steps of: controlling the data registers held under the internal signal. The center side apparatus, after issuing the command for controlling the non-volatile memory, a register in said communication terminal device with reference via the control channel, to confirm the completion of the command the issued claim 13 Method for controlling the communication terminal apparatus of the present invention.   The method of controlling a communication terminal device according to claim 13, wherein the center side device transmits update data of the nonvolatile memory via the control channel, and causes the transmitted update data to be written to the nonvolatile memory. .   The non-volatile memory has a first block for operation and a second block for backup, and the center side device writes the update data in the second block, The communication terminal apparatus control method according to claim 15, wherein the data of the second block is copied to the first block.   The center side device refers to a checksum calculation result of the update data calculated in the communication terminal device, and determines whether or not the update data has been correctly transmitted with reference to the control channel. The control method of the communication terminal device of 15 or 16.

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