JP4523351B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a dry etching method and a semiconductor device manufacturing method, and more particularly, a dry etching method and a semiconductor device manufacturing method in which a resist mask has less etching roughness and a pattern transfer of a fine resist pattern onto a workpiece material is easy. Regarding the method.

  In recent years, the speed of semiconductor devices has been remarkably increased, and transmission delay due to a decrease in signal propagation speed due to wiring resistance and parasitic capacitance between wirings has become a problem. Such a problem tends to become more prominent because the wiring resistance increases and the parasitic capacitance increases as the wiring width and the wiring interval become finer due to higher integration of semiconductor devices.

  In order to prevent signal delay due to an increase in wiring resistance and parasitic capacitance, copper wiring has been introduced instead of aluminum wiring, and an insulating film having a low dielectric constant (hereinafter referred to as a low-k film) is used as an interlayer insulating film. Has been tried to use. As a method for forming a copper wiring using a low-k film, there is a damascene method. This is known as a technique for forming a wiring without etching copper, considering that it is difficult to control the etching rate of copper compared to aluminum.

  Specifically, in the damascene method, for example, an SiC (silicon carbide) film, a low-k film, and a cap film are sequentially formed as an etching stopper layer or an insulating barrier layer on a lower layer wiring, and then a resist film is formed. Wiring grooves are formed by dry etching using a mask, the resist film is removed by ashing, the etching stopper layer is etched, and a wiring material film made of a barrier metal, copper or copper alloy material is embedded in the wiring grooves. This is a method of forming a trench wiring. The wiring material film is embedded by CMP (Chemical Mechanical Polishing) so as to leave the wiring material film only inside the wiring groove after the wiring material film is formed by embedding the wiring groove by CVD method, plating method or the like. It can be realized by planarizing the surface using a mechanical polishing method.

  In the formation of groove wirings of 130 nm node to 65 nm node, a resist pattern is mainly formed by ArF excimer laser (wavelength; about 193 nm) exposure, and a resist (film) corresponding to ArF excimer laser exposure is used as a mask. When the low-k film is dry-etched, the resist surface becomes rough. This resist roughness is transferred to the low-k film of the material to be processed on the pattern side wall, and a so-called striation occurs in which the pattern side wall (wiring groove side wall) of the low-k film becomes jagged. Along with miniaturization, in the case of wiring, the wiring interval is narrowed, and at the 65 nm node, the first layer wiring is expected to have a pitch of 180 nm to 200 nm. That is, the line / space (L / S) is 90 nm / 90 nm to 100 nm / 100 nm. Expressing the striation value as the difference between the maximum and minimum wiring dimensions, even if the value is about 10 nm, it accounts for about 10% of the wiring width dimension, and the effect is negligible for trench wiring that has a very long wiring length. become unable. As an influence of this striation, an increase in leakage current and a short circuit between wirings can be mentioned. Furthermore, voids in the Cu film due to Cu plating, which are generated due to defective film formation of the barrier metal provided under the wiring material film, are likely to occur. The same problem occurs when a via plug is formed by embedding a conductor material such as a copper material in a connection hole (via hole) for connecting between wiring layers.

  The present invention has been made in view of the above circumstances, and it is an object of the present invention to suppress the resist film from being roughened and to reduce the striations generated on the pattern side walls when dry etching a material to be processed using the resist film as a mask. To do.

  In order to solve the above-mentioned problems, an invention relating to a dry etching method is directed to dry etching in which a gas containing at least carbon and fluorine is plasma-excited and the work material is selectively etched using a resist film on the work material as a mask. In the method, the atomic ratio of fluorine to carbon contained in the gas is 4 or more.

In the above invention, the gas contains a fluorocarbon gas. Alternatively, HF gas, F ₂ gas, SF ₆ gas, or NF ₃ gas is added to the gas.

  The invention according to the method for manufacturing a semiconductor device includes a step of forming an interlayer insulating film on a semiconductor substrate, a step of forming a resist film having a wiring groove pattern on the interlayer insulating film, and at least carbon and fluorine A gas having a fluorine atomic ratio of 4 or more with respect to carbon is plasma-excited, and the interlayer insulating film is dry-etched using the resist film as a mask to form a wiring groove in the interlayer insulating film. And a step of forming a wiring layer by embedding a wiring material film in the wiring groove after removing the resist film.

  According to the configuration of the present invention, in dry etching of a material to be processed using a resist film as a mask, resist mask roughness is suppressed, striations on the pattern side walls are reduced, and a fine etching process that makes the pattern shape elongated is performed. It becomes possible.

  Hereinafter, as an example of a method of manufacturing a semiconductor device according to the present invention, a method of dry etching a low dielectric constant interlayer insulating film, which is a material to be processed, to form a copper wiring by a single damascene method will be described with reference to FIGS. I will explain. And in that, the dry etching method of this invention is demonstrated collectively. 1 to 3 are element sectional views in the order of the manufacturing process of the wiring.

  First, as shown in FIG. 1A, a first etching stopper layer 2 is formed on a lower wiring 1 formed on a silicon substrate. The first etching stopper layer 2 is composed of, for example, a SiC film, a SiCN film, or a SiN film.

A low-k film 3 is formed thereon. The Low-k film 3 is made of an insulating material having a dielectric constant lower than that of the silicon dioxide film (SiO ₂ ). A material having a relative dielectric constant of 3.0 or less, more preferably a dielectric constant of 2.5 or less is preferably used. For example, a porous material of organopolysiloxane is suitable.

  Here, the organopolysiloxane is a polysiloxane having an organic functional group, and an alkylsilsesquioxane is preferable because it is excellent in dielectric properties and processability. For example, as shown in FIG. 4, methylsilsesquioxane having a film composition containing a methyl group is preferably used, and the coating system is called an MSQ film and the CVD system is called an SiOC film because of the difference in the film forming method. Low-k films having a relative dielectric constant of 2.5 to 3.0 are applied to 130 nm to 90 nm nodes. At the 65 nm node, the relative dielectric constant needs to be 2.5 or less, and porous MSQ films or porous SiOC films containing pores are being studied.

A method for forming the Low-k film 3 will be described in a specific manner. In the case of the plasma CVD method, a mixed gas of an alkylsilane gas and an oxidizing gas is used as a source gas. Examples of the alkyl silane gas include monomethyl silane, dimethyl silane, trimethyl silane, and tetramethyl silane. These can be used alone or in combination of two or more. Of these, trimethylsilane is preferably used. The oxidizing gas is a gas that exhibits an oxidizing action on alkylsilane, and includes an oxygen element in the molecule. For example, one or two or more gases selected from the group consisting of NO, NO ₂ , CO, CO ₂ and O ₂ can be used, and among these, the strength of oxidizing power is moderate, so NO and NO ₂ is preferably used. On the other hand, when forming by spin coating method (coating method), a solution in which a layer material is dissolved is applied dropwise onto a wafer rotating at a predetermined rotation speed, and then subjected to multi-step heat treatment to dry and solidify. A film is formed by performing. Furthermore, the degree of porosity can be increased and the dielectric constant can be lowered depending on the heat treatment conditions. In general, the pore diameter of the porous SiOC film is around 1 nm, and the pore diameter of the porous MSQ film is mainly 1 nm to 20 nm.

Next, the cap layer 4 is formed on the Low-k film 3 formed as described above. The cap layer 4 increases the O ₂ plasma ashing resistance of the resist during rework for forming the resist film, prevents the dielectric constant from increasing due to moisture absorption of the low-k film 3, and further serves as a polishing stopper for CMP after Cu plating. Formed with. The cap layer 4 is formed of a silicon oxide film, for example.

  Then, an ARC film 5 and a resist mask 6 which are organic polymer antireflection films are formed on the cap layer 4. Here, a wiring groove pattern 7 is formed in the resist mask 6.

Next, as shown in FIG. 1B, the ARC film 5, the cap layer 4, and the low-k film 3 are sequentially dry-etched to form a wiring groove 8 that reaches the surface of the first etching stopper layer 2. In this dry etching, a mixed gas system of fluorocarbon (CxHyFz) / Ar / N ₂ is used as an etching gas. By using this gas system, film damage to the Low-k film 3 is reduced. Here, x, y, and z are zero or a positive integer.

Here, in the dry etching of the interlayer insulating film having a low dielectric constant comprising the Low-k film 3, fluorocarbon _{CF 4, CHF 3, CH 2} F 2, C 4 F 8, C 5 F 8, C 4 and dry etching instead of F ₆ and various. As a result, it has been clarified that the resist roughness of the resist mask 6 is reduced when the atomic ratio of F (fluorine) / C (carbon) is large.

FIG. 5 is a photomicrograph showing the shape of the resist mask on the upper surface after dry etching the porous MSQ film using CF ₄ , CHF ₃ , CH ₂ F ₂ gas as the fluorocarbon of the mixed gas. Here, FIG. 5A shows a case where CF ₄ gas is fluorocarbon, FIG. 5B shows a case where CHF ₃ gas is fluorocarbon, and FIG. 5C shows CH ₂ F ₂ gas being fluorocarbon. This is the case. As can be seen from these photographs, the resist roughness (particle size) is about 24 nm for CF ₄ gas, about 48 nm for CHF ₃ gas, and about 80 nm for CH ₂ F ₂ gas. Then, as the resist roughness after the dry etching is large and the pattern sidewall roughness of the resist mask is large, and as the resist residual film is small, the pattern sidewall of the low-k film 3 after the dry etching of the interlayer insulating film, that is, A striation is easily formed on the side wall of the wiring groove.

Here, the above reason will be described from the viewpoint of the F / C ratio of the etching gas. When CF ₄ gas, CHF ₃ gas, and CH ₂ F ₂ gas are compared, the larger the F / C ratio, the greater the reactivity between F and C in the resist, and the main chain and side chain of the resist are cut. Cheap. In addition, the reaction is promoted because the deposit is weak. Therefore, it is considered that etching is performed uniformly regardless of the macro non-uniformity of the resist component. On the other hand, when the F / C ratio is decreased, the deposition property is increased relative to the etching, so that it is considered that the etching reaction portion and the unreacted portion become conspicuous with the addition of macro non-uniformity of the resist component.

Similarly, when CF ₄ gas, C ₄ F ₈ gas, C ₅ F ₈ gas, and C ₄ F ₆ gas are compared, in C ₄ F ₈ gas, C ₅ F ₈ gas, and C ₄ F ₆ gas, CH ₂ The resist roughness is as large as F ₂ gas. The high molecular weight fluorocarbon gas is decomposed in plasma, and low molecular weight ions and radicals are also generated. Therefore, although it cannot be generally stated, the high molecular weight has an F / C ratio of 1.5 to 2.0. It is considered that the reactivity is low compared with CF ₄ gas and the deposition property is large.

From the above, it was found that the resist roughening particle size is the smallest in CF ₄ gas, and the striation can be suppressed. In particular, if the F / C ratio is 4 or more, the processed shape of the wiring groove can be obtained without any problem in terms of electrical characteristics of the copper wiring.

It has also been clarified that the resist roughening can be prevented even when a fluorine-containing gas added to a fluorocarbon gas is used as the dry etching gas. As the additive gas, HF gas, F ₂ gas, SF ₆ gas, and NF ₃ gas are suitable. Even in the added etching gas, the striation is suppressed by increasing the F / C ratio in the etching gas. Even in this case, in particular, an F / C atomic ratio of 4 or more is suitable, and it is possible to obtain a processed shape of a wiring groove that has no problem in terms of electrical characteristics such as leakage current or short circuit between groove wirings of a semiconductor device. become.

Here, the resist film is not limited to ArF excimer laser exposure. When the F / C ratio of the etching gas is increased, particularly when the ratio is 4 or more, the striation suppression effect is remarkable even in the case of various resist films for exposure for I-line, KrF, F ₂ and EB. Be able to.

After forming the wiring trench 8 in the interlayer insulating film including the low-k film 3 as described above, as shown in FIG. 1C, the resist mask 6 and the ARC film 5 are subjected to high-temperature H ₂ / He plasma, The resist mask is removed without film damage using a low temperature N ₂ / H ₂ plasma or the like, and the cap layer 4 is exposed.

Next, as shown in FIG. 2A, in dry etching using the cap layer 4 as a hard mask, a CHF ₃ / Ar / N ₂ mixed gas, a CF ₄ / Ar / N ₂ mixed gas, or the like is used as an etching gas. Then, the first etching stopper layer 2 is dry-etched to penetrate the wiring groove 8 so as to reach the lower layer wiring 1.

  Next, as shown in FIG. 2B, Ta / TaN barrier metal sputtering, Cu seed, and Cu plating are performed, and the wiring material film 9 is connected to the lower layer wiring 1 and buried in the wiring groove 8. Next, Cu annealing is performed on the wiring material film 9 at 350 ° C. as shown in FIG. Further, as shown in FIG. 3A, the copper layer 10 is formed by polishing and removing unnecessary portions of the wiring material film 9 thereon using the cap layer 4 as a polishing stopper. Then, as shown in FIG. 3B, a second etching stopper layer 11 covering the copper wiring 10 and the cap layer 4 is formed with a SiC film or the like, thereby completing the groove wiring.

  In the present embodiment, as described above, striations on the side walls of the wiring grooves are greatly suppressed in the formation of the wiring grooves by dry etching of the interlayer insulating film including the low-k film 3. Leakage and short-circuiting can be suppressed. Furthermore, since the side wall of the wiring groove is smooth, the step coverage of the barrier metal is excellent, and the occurrence of voids in Cu plating due to defective barrier film formation can be suppressed.

  A multilayer wiring is formed by repeatedly forming a via on the copper wiring in the same manner. As for vias, the same effect as in the case of wiring can be obtained. As described above, a highly reliable semiconductor device that operates at high speed can be manufactured.

  The dry etching apparatus can be either a two-frequency RIE type or an ICP type, and the ashing apparatus can be a downflow type surface wave plasma asher, an ICP type plasma asher, or an etching apparatus (two-frequency RIE, Any device such as an ICP) etcher may be used.

According to the above embodiment, when dry etching the interlayer insulating film including the low-k film using the resist mask, the fluorocarbon (CxHyFz) / Ar / N ₂ mixed gas system or the etching that adds a fluorine-containing gas to the mixed gas system is performed. In the gas, when the atomic weight ratio of the total fluorine amount to the total carbon amount in the etching gas is 4 or more, the resist roughness of the resist mask can be suppressed. And since the striation of the wiring trench side wall, which is the pattern side wall after dry etching of the Low-k film, can be greatly suppressed, current leakage between damascene wirings and short circuit are greatly reduced. Furthermore, since the wiring trench side wall becomes smooth, the step coverage of the barrier metal is improved, and the occurrence of voids in Cu plating due to barrier film formation failure can be suppressed. In this way, a semiconductor device having a damascene wiring that is fine and has a very long wiring length can be manufactured with a high yield.

  Although the preferred embodiments of the present invention have been described above, the above-described embodiments do not limit the present invention. Those skilled in the art can make various modifications and changes in specific embodiments without departing from the technical idea and technical scope of the present invention.

For example, in the above embodiment, as the Low-k film, in addition to the MSQ film, another insulating film having a siloxane skeleton or an insulating film having an organic polymer as a main skeleton can be used. The insulating film having a siloxane skeleton includes a silica film containing at least one of a Si—CH ₃ bond, a Si—H bond, and a Si—F bond, which is an insulating film of silsesquioxanes. As an insulating film having molecules as a main skeleton, there is SiLK (registered trademark) made of an organic polymer. Insulating materials well known as insulating films of silsesquioxanes include MSQ, hydrogen silsesquioxane (HSQ), and methylated hydrogen silsesquioxane (MHSQ). Silsesquioxane). Furthermore, as the low dielectric constant film having a porous structure, a porous SiOCH film or SiOC film formed by the CVD method can be used in the same manner.

  Further, the material to be processed in the dry etching is not limited to the interlayer insulating film, and the dry etching method of the present invention can be similarly applied to other insulator materials, semiconductor materials, and conductor materials. Furthermore, the present invention can be similarly applied to etching of a material to be processed on a liquid crystal display substrate and a plasma display substrate as well as a semiconductor substrate.

It is element sectional drawing according to process in the damascene wiring manufacture concerning embodiment of this invention. FIG. 2 is an element sectional view by process following the process illustrated in FIG. 1. FIG. 3 is an element sectional view by process following the process illustrated in FIG. 2; It is a structural view showing the composition of a low dielectric constant MSQ film. It is a top view which shows the resist roughening of the resist mask after carrying out the dry etching of the interlayer insulation film.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Lower layer wiring 2 1st etching stopper layer 3 Low-k film 4 Cap layer 5 ARC film 6 Resist mask 7 Wiring groove pattern 8 Wiring groove 9 Wiring material film 10 Copper wiring 11 2nd etching stopper layer

Claims (1)

Forming an interlayer insulating film having a relative dielectric constant of 3.0 or less on a semiconductor substrate;
Forming a resist film having a wiring groove pattern on the interlayer insulating film;
Plasma-exciting a gas containing at least carbon and fluorine and having an atomic ratio of fluorine to carbon of 4 or more, and dry-etching the interlayer insulating film using the resist film as a mask, to thereby form the interlayer insulating film Forming a wiring groove in
After removing the resist film, a step of burying a wiring material film in the wiring groove to form a wiring layer;
I have a,
To the gas, HF gas, a method of manufacturing a semiconductor device, characterized in that the addition of _{F 2} gas, SF ₆ gas, or NF ₃ gas.