JP4212161B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which a processor and a memory are arranged on one chip, and particularly relates to a technique that improves the degree of integration and enables high-speed processing.
[0002]
[Prior art]
In recent years, many electronic devices have been developed in the direction of lighter weight and smaller size considering the user's easy operation. Furthermore, with the rapid increase in the amount of information handled by electronic devices, it has become desirable to further increase the information processing speed of electronic devices.
[0003]
Against this background, the concept of a one-chip LSI, which is a semiconductor device in which a processor chip and a memory chip are combined on one chip, has recently been proposed and has already entered a practical stage.
[0004]
Hereinafter, a typical one-chip LSI will be described with reference to FIG.
[0005]
FIG. 49 is a schematic diagram for explaining the configuration of a one-chip LSI.
[0006]
In the one-chip LSI, the chip 1 includes a CPU 3 for performing various calculations, a plurality of modules 5 serving as memory cell areas, and a bus 15 that electrically connects the CPU 3 and the individual modules 5. .
[0007]
Before the development of one chip, it consisted of a configuration in which a chip having a CPU function and a memory chip were connected to each other. However, this one-chip configuration significantly reduced the area occupied by the system. Furthermore, since the wiring length between modules has become shorter, higher speed processing has become possible.
[0008]
[Problems to be solved by the invention]
As described above, with the advent of 1-chip LSIs, semiconductor devices such as LSIs can be made smaller and perform higher-speed processing. Recently, however, new technical problems have emerged that stem from the concept of one chip.
[0009]
In general, a general-purpose processor chip and a general-purpose memory chip have different design techniques and wiring structures. For example, when the wiring structures of a memory chip and a processor chip are compared, wiring used for a memory generally has an upper limit of two layers, whereas a processor has a multilayer wiring structure as a basic structure. Therefore, when the processor chip and the memory chip are to be integrated on one chip, the desired performance cannot be achieved simply by installing individual elements on the same chip, and complicated assembly work is required. Will be required. Furthermore, in order to construct a system LSI, it is necessary to form a seamless connection with an optical wiring and integrate further functions, but there is no method that can realize this at present.
[0010]
One way to solve this problem is to unify the design process of the processor chip and the memory chip, but in general, changing the design process requires a lot of labor and time. Is accompanied by great difficulties in terms of technology and cost.
[0011]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device having a higher degree of integration, realizing high-speed processing, and further functions.
[0012]
[Means for Solving the Problems]
In order to solve the above technical problem, a semiconductor device according to the present invention includes a processor unit for performing an operation, and a plurality of memory cell regions arranged symmetrically three-dimensionally with the processor unit as a symmetry center, The present invention is characterized by comprising wiring means for transmitting information between the processor section and the memory cell region.
[0013]
As described above, in this semiconductor device, since the memory cell regions are three-dimensionally arranged symmetrically with the processor portion as the center of symmetry, higher integration and high-speed processing can be desired, and signals must be synchronized. Sexuality can be reduced.
[0014]
Further, the processor unit and the memory cell region may be composed of spheres. As a result, the degree of integration can be improved and the circuit area that can be mounted on each part can be increased.
[0015]
In addition, a program unit may be provided for changing the wiring relationship between the processor unit and the memory cell region and the function of each unit. As a result, various functions can be realized only by changing the program.
[0016]
Furthermore, a plurality of the processor units may exist. As a result, a multiprocessor can be formed.
[0017]
Further, the processor unit may be of any type, and may be a processor using a quantum effect. Thereby, since different kinds of processors coexist on one system, the system becomes more multifunctional.
[0018]
Further, it is desirable that the wiring means is constituted by a bus, and a bus interface is provided in the bus. As a result, faster instruction processing is possible.
[0019]
Further, a buffer or cache memory may be provided between the processor unit and the memory cell area. This further reduces the need for signal synchronization.
[0020]
Further, the processor section and the memory cell region may be connected by an optical wiring. Thereby, wiring between chips and between boards can be designed with the same rule.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the semiconductor device according to the present invention will be described in detail with reference to FIGS.
[0022]
FIG. 1 is a schematic diagram illustrating the semiconductor device according to the first embodiment.
[0023]
The semiconductor device of this embodiment includes a spherical CPU 3 for performing computation, a spherical memory cell region 5, wiring means 7 for electrically connecting the CPU 3 and the memory cell region 5, an input / output interface 9, The light-emitting / light-receiving means 11 for transmitting and receiving an optical signal provided in the input / output interface 9 is configured.
[0024]
In the above configuration, each memory cell region 5 is symmetrically arranged three-dimensionally with the CPU 3 as the center of symmetry. As a result, the distances between the CPU 3 and the memory cell regions 5 are all equal, and the effort for synchronizing the signals can be reduced.
[0025]
Since both the CPU 3 and the memory cell region 5 are spherical, they can be arranged more densely than a rectangular module, and a higher degree of integration can be desired.
[0026]
Furthermore, in the present embodiment, both the CPU 3 and the memory cell region 5 are composed of one sphere. However, a configuration in which the structural unit shown in FIG. 1 is included in each module may be adopted. That is, the CPU 3 and the memory cell area 5 may be composed of a plurality of spheres. In such a case, however, the symmetry of the structural unit as shown in FIG. 1 is always maintained.
[0027]
Furthermore, information may be transmitted and received between the modules by using an optical signal from the light emitting / receiving unit 11. In this case, it is necessary to provide light receiving / light emitting means as wiring means on each module as well, but this eliminates the need for physical wiring means such as wires between the modules.
[0028]
FIG. 2 is a schematic diagram showing the semiconductor device of the second embodiment.
[0029]
In this configuration, the input / output interface functions shown in FIG. 1 are added to the upper and lower memory cell regions to form the memory cell region 13.
[0030]
In the present embodiment, each component is rectangular, but as in the embodiment shown in FIG. 1, each memory cell region has spatial symmetry with respect to the CPU 3, so that the signals are synchronized. There is less need to try.
[0031]
In addition, each rectangular module does not need to be comprised from a single module, For example, the integration degree of each module itself can be raised by forming a module using a some sphere.
[0032]
FIG. 3 is a schematic view of the semiconductor device according to the third embodiment as viewed from the side.
[0033]
When each module has a rectangular shape as shown in FIG. 2, the degree of integration of the entire chip can be improved by arranging the modules in a nested manner as shown in FIG.
[0034]
FIG. 4 is a schematic view of the semiconductor device according to the fourth embodiment as viewed from the side.
[0035]
As shown in FIG. 4, when the components are stacked in layers, the effects of the present invention can be realized by arranging the components so as to have symmetry also in the vertical direction. However, in this case, care must be taken that the wiring lengths between the components are equal.
[0036]
FIG. 5 is a schematic view of the semiconductor device according to the fifth embodiment viewed from the side.
[0037]
In the present embodiment, the memory cell region 5 is arranged in the chip 1 so as to be symmetrical in space with the CPU 3 as the center of symmetry.
[0038]
Hereinafter, examples of wiring between components and various applications of the semiconductor device illustrated in FIG. 5 will be described with reference to FIGS.
[0039]
In the following description of the semiconductor device shown in FIGS. 8 to 43, it is assumed that the three-dimensionally formed device is viewed from the side. However, as described above, since the semiconductor device of the present invention is arranged so that each module has three-dimensional symmetry, the technical scope of the present invention is not limited to the arrangement shown in the figure. Absent. That is, the semiconductor device is arranged as shown in FIG. 6, for example, and the arithmetic unit and the memory unit are connected by the shortest path. In FIG. 6, there are a, b, c, d, e, f, g, and h, but only a and b, and only ab and de are possible. Further, any arrangement shown in FIG. 7 is within the meaning of the present invention.
[0040]
FIG. 8 is a diagram illustrating a configuration of a semiconductor device according to the eighth embodiment.
[0041]
The chip 1 includes a CPU 3, a memory cell region 5a, 5b, 5c, 5d, a bus 15a connecting short sides of the memory cell regions 5a and 5b, a bus 15b connecting short sides of the memory cell regions 5a and 5c, A bus 15c connecting the short sides of the memory cell areas 5c and 5d, and a program means 17 for changing the wiring relationship between the CPU 3 and the memory cell area and the function of each module by programming provided at the connection point between each module and the bus. The upper side of the CPU 3 and the bus 15b are electrically connected.
[0042]
The wiring of this embodiment is suitable for outputting a signal from the upper side of the chip 1. Note that the program means 17 may be formed in each module. In addition, it is assumed that wirings used in the following embodiments including this embodiment are used for transmission / reception of signals such as address signals, data signals, word line activation signals, column line activation signals, and control signals. It is assumed that the CPU 3 can execute the instruction stored in the memory cell area through the wiring.
[0043]
Further, the wiring shown in FIG. 8 may have a form as shown in FIG.
[0044]
FIG. 10 is a diagram illustrating a configuration of the semiconductor device according to the tenth embodiment.
[0045]
In this embodiment, the memory cell regions 5a and 5b are connected by a bus 15a, the memory cell regions 5a and 5c are connected by a bus 15b, the memory cell regions 5b and 5d are connected by a bus 15d, and the CPU 3 and the bus 15a are further connected. .
[0046]
The wiring of this embodiment is suitable for outputting signals from the upper side and the lower side of the chip 1.
[0047]
The wiring shown in FIG. 10 may have a form as shown in FIG.
[0048]
FIG. 12 is a diagram illustrating a configuration of the semiconductor device according to the twelfth embodiment.
[0049]
In the present embodiment, the short sides of the memory cell regions 5a and 5c are connected to each other by the bus 15b, the short sides of the memory cell regions 5b and 5d are connected to each other by the bus 15d, and the upper and lower sides of the CPU 3 are respectively connected to the bus 15b, 15d is connected.
[0050]
In this case, two buses are connected to the CPU 3. As a result, the memory cell regions connected to the respective systems can be controlled separately, and the two memory cell regions can be accessed in parallel. Therefore, this wiring is suitable when the size and application of the memory cell area of each system are different. In addition, since the bus length is shorter than that in the embodiment, higher speed processing can be realized.
[0051]
FIG. 13 is a diagram illustrating the configuration of the semiconductor device according to the thirteenth embodiment.
[0052]
In the present embodiment, the short sides of the memory cell regions 5a and 5b are connected by the bus 15a, the short sides of the memory cell regions 5c and 5d are connected by the bus 15c, and the left and right sides of the CPU 3 are connected by the bus 15a, 15d is connected.
[0053]
Also in this case, as in the twelfth embodiment, since there are two buses, the same effects as those in the tenth embodiment can be obtained. Furthermore, in this case, the FPGA unit (program means) 17 is connected to the bus, and the architecture itself can be changed.
[0054]
FIG. 14 is a diagram illustrating a configuration of the semiconductor device according to the fourteenth embodiment.
[0055]
In the present embodiment, the long sides of the memory cell regions 5a, 5b, 5c and 5d and the upper side of the CPU 3 are connected to a bus 15 extending in the lateral direction of the chip.
[0056]
In this case, the area occupied by the bus in the chip is large, but the bus is connected to the long side rather than the short side of the memory cell area, so that multiple addresses in the memory cell area can be accessed at a time. This is effective when there is a bias in the use of the memory cell region.
[0057]
As can be seen from the above configuration, in the present invention, a space is provided between the memory cell regions, and the CPU is arranged in this space. Therefore, it is possible to allocate a space to an arrangement place of components other than the CPU. Therefore, in the following, an arrangement / wiring example in the case where components such as a bus interface, a peripheral circuit, a buffer, and a cache memory are added to the semiconductor device according to the present invention together with the CPU will be described.
[0058]
First, in the embodiment according to the present invention shown in FIGS. 8 to 14, the case where a bus interface for enabling high-speed instruction processing is added to the elements will be described with reference to FIGS.
[0059]
FIG. 15 is a diagram illustrating a configuration of a semiconductor device according to the fifteenth embodiment.
[0060]
The present embodiment is characterized in that a bus interface 19 is provided on the upper side of the bus 15b in the semiconductor device of the eighth embodiment.
[0061]
In this configuration, since the bus interface receives an instruction from the CPU and controls an external pin, a higher-speed output is possible than when there is no bus interface.
[0062]
Also, since the bus interface has a data holding function, the number of pins can be greatly reduced for external output.
[0063]
Furthermore, in general, the functions related to the data output control of the bus interface can be changed by programming. Therefore, the arrangement and wiring of the bus interface can be changed using the program means, and other arrangements are also possible. Examples can also be made.
[0064]
Furthermore, this bus interface may correspond to an optical wiring.
[0065]
FIG. 16 is a diagram illustrating a configuration of a semiconductor device according to the sixteenth embodiment.
[0066]
The present embodiment is characterized in that in the semiconductor device of the tenth embodiment, bus interfaces 19a and 19b are provided above the bus 15b and below the bus 15d.
[0067]
With this configuration, higher-speed output is possible compared to the tenth embodiment, and it can withstand use with more frequent access. In addition, the number of pins per side of the chip can be greatly reduced.
[0068]
FIG. 17 is a diagram illustrating a configuration of a semiconductor device according to the seventeenth embodiment.
[0069]
The present embodiment is characterized in that, in the semiconductor device of the tenth embodiment, a bus interface 19 is provided on the upper side of the bus 15b.
[0070]
According to this configuration, the bus interface pins are concentrated on one side of the chip, and the pins on the other side can be used for other purposes. Further, the memory cell region connected to the bus interface can be used for data, the memory cell region not connected to the bus interface can be used for instructions, and the memory cell region can be used properly according to the application.
[0071]
FIG. 18 is a diagram showing a configuration of a semiconductor device according to the eighteenth embodiment.
[0072]
The present embodiment is characterized in that, in the semiconductor device of the twelfth embodiment, bus interfaces 19a and 19b are provided above the bus 15b and below the bus 15d. As a result, higher-speed output is possible than in the semiconductor device of the eighth embodiment, and it can be applied to use with frequent access. Essentially, by providing either one of the bus interfaces 19a and 19b, high-speed output is possible.
[0073]
FIG. 19 is a diagram showing a configuration of a semiconductor device according to the nineteenth embodiment.
[0074]
In this embodiment, the short sides of the memory cell regions 5a and 5c are connected by a bus 15b, the short sides of the memory cell regions 5b and 5d are connected by a bus 15d, and the short sides of the memory cell regions 5a and 5b are connected by a bus. 15a, the short sides of the memory cell regions 5c and 5d are connected using a bus 15c.
[0075]
Also in this configuration, a bus interface may be provided in the external output unit as in the above embodiment.
[0076]
Next, the case where a peripheral circuit is added to the elements of the semiconductor device will be described with reference to FIGS. Here, the peripheral circuit means typical peripheral circuits such as a timer, a counter, and various controllers. Similarly to the bus interface, the wiring may be changed by incorporating a desired function by programming by the program means.
[0077]
FIG. 20 is a diagram illustrating a configuration of a semiconductor device according to the twentieth embodiment.
[0078]
In this embodiment, in the semiconductor device of the eighth embodiment, the peripheral circuit 21 is connected to the same side as the CPU 3 with respect to the bus 15b. Thereby, the pins related to transmission / reception of the control signal can be concentrated on one side.
[0079]
FIG. 21 is a diagram showing a configuration of a semiconductor device according to the twenty-first embodiment.
[0080]
In this embodiment, in the semiconductor device of the eighth embodiment, the peripheral circuit is connected to the same side as the CPU with respect to the bus 15b. Thereby, unlike the twenty-first embodiment, the pins related to transmission and reception of control signals can be divided into two systems of chips.
[0081]
FIG. 22 is a diagram illustrating a configuration of a semiconductor device according to the twenty-second embodiment.
[0082]
The present embodiment is characterized in that, in the semiconductor device of the twentieth embodiment, the bus interface 19 is connected to the opposite side of the CPU 3 and the peripheral circuit 21 with respect to the bus 15b, and the bus interface 19 is connected to the bus 15b.
[0083]
FIG. 23 is a diagram illustrating a configuration of a semiconductor device according to the twenty-third embodiment.
[0084]
In this embodiment, in the semiconductor device of the tenth embodiment, the peripheral circuit 21 is installed on the CPU 3 and connected to the bus 15a.
[0085]
FIG. 24 is a diagram illustrating a configuration of a semiconductor device according to the twenty-fourth embodiment.
[0086]
In this embodiment, in the semiconductor device of the twelfth embodiment, a peripheral circuit 21 is provided beside the CPU 3 and connected to the buses 15b and 15d.
[0087]
FIG. 25 is a diagram illustrating a configuration of a semiconductor device according to the twenty-fifth embodiment.
[0088]
In this embodiment, in the semiconductor device of the thirteenth embodiment, the peripheral circuit 21 is installed on the CPU 3 and connected to the buses 15a and 15b.
[0089]
FIG. 26 is a diagram illustrating a configuration of a semiconductor device according to the twenty-sixth embodiment.
[0090]
In this embodiment, in the semiconductor device of the fourteenth embodiment, the peripheral circuit 21 is installed above the CPU 3 and connected to the bus 15.
[0091]
Next, a case where a plurality of CPUs are system configuration requirements will be described with reference to FIGS.
[0092]
FIG. 27 is a diagram showing a configuration of a semiconductor device according to the twenty-seventh embodiment.
[0093]
In this embodiment, in the semiconductor device of the eighth embodiment, a plurality of CPUs are installed in an empty space to constitute a multiprocessor.
[0094]
FIG. 28 is a diagram illustrating a configuration of a semiconductor device according to the twenty-eighth embodiment.
[0095]
In this embodiment, as in the previous embodiment, a plurality of CPUs are installed on both sides of the bus 15 to configure a multiprocessor.
[0096]
FIG. 29 is a diagram showing a configuration of a semiconductor device according to the twenty-ninth embodiment.
[0097]
Also in this embodiment, a plurality of CPUs are installed in series between the two buses 15a and 15b to constitute a multiprocessor.
[0098]
In the embodiment described above, the memory cell region and the CPU are directly wired. However, for example, as shown in FIGS. 30 to 31, a buffer may be provided between the memory cell region and the CPU. As a result, the memory cell area and the CPU can be surely synchronized. Further, in the data read process of the CPU, necessary data is transferred from the memory cell area to the buffer in advance, and the CPU write process is performed. In this case, high-speed processing can be realized by holding data in the buffer and transferring the data from the buffer to the memory cell area in parallel with subsequent CPU processing.
[0099]
In the above case, the size of the buffer and the size of the side of the memory cell area to be connected are the same. Further, the buffer may be applied to all memory cell regions or may be used only for memory cell regions that need to be synchronized.
[0100]
Here, the configuration of the buffer will be described with reference to FIGS.
[0101]
FIG. 32 is a diagram for explaining an embodiment of the buffer according to the present invention.
[0102]
As shown in the figure, the buffer is configured by installing a latch 25 for latching bidirectional signals in series between the memory cell region 5 and the CPU 3. In this configuration, the signal can be processed only in one direction at a time, but the latch can hold the input signal once, so that the output signal can be driven without synchronizing with the change of the input signal. .
[0103]
As another configuration, as shown in FIG. 33, a latch 25a for latching a signal from the memory cell area to the CPU and a latch 25b for latching a signal from the CPU to the memory cell area are arranged in parallel between the memory cell area and the CPU. The case where it installs is considered. In this case, bidirectional signals can be processed simultaneously.
[0104]
In addition, as shown in FIGS. 34 and 35, there is a case where a latch for latching only a signal in one direction and a driver 27 are installed in parallel between the memory cell region and the CPU. Since the driver occupies a smaller area than the latch, this configuration is suitable for downsizing the device. The driver can amplify the input signal and output it.
[0105]
In the above buffer configuration, the latch may be a flip-flop circuit.
[0106]
Finally, other application examples will be described with reference to FIGS.
[0107]
In some of the application examples shown below, a cache memory is added to the elements of the semiconductor device. This is because the cache memory reduces the frequency with which the CPU accesses the memory cell area and realizes higher-speed processing. It is.
[0108]
Similarly to the buffer, the cache memory may be provided in all memory cell areas, or may be provided only in the memory cell area that needs to be synchronized with the CPU.
[0109]
FIG. 36 is a diagram showing the configuration of the semiconductor device of the thirty-second embodiment.
[0110]
A cache memory 29 is installed between the memory cell area 5 and the CPU 3.
[0111]
FIG. 37 is a diagram showing a configuration of the semiconductor device of the thirty-third embodiment.
[0112]
In the present embodiment, in addition to the thirty-second semiconductor device embodiment, a buffer 23 is provided between the cache memory 29 and the memory cell region 5.
[0113]
FIG. 38 is a diagram showing a configuration of the semiconductor device of the thirty-fourth embodiment.
[0114]
In the present embodiment, a buffer 23 is provided between the memory cell region 5 and the CPU 3.
[0115]
The buffer 23 may be disposed on the CPU 3. Further, the cache memory 29 may be disposed on the CPU 3, the cache memory 29 may be disposed on the CPU 3, and the buffer 23 may be disposed on the cache memory 29. Furthermore, buffers 23a and 23b can be arranged above and below the CPU 3, respectively, and cache memories 29a and 29b can be arranged above and below the CPU, respectively. Furthermore, the buffers 23a and 23b can be arranged above the cache memory 29a and below the cache memory 29b, respectively.
[0116]
FIG. 39 is a diagram showing the configuration of the semiconductor device of the 35th embodiment.
[0117]
In this embodiment, the long sides of the memory cell regions 5a and 5b are connected to each other by the bus 15a, the bus 15a and the memory cell region 5c are connected by the bus 15b, the bus 15a, the memory cell region 5d and the bus 5d, and the left side of the CPU is connected. It is connected to the bus 15b. This configuration is suitable for outputting a signal from one side of the chip.
[0118]
FIG. 40 is a diagram showing the configuration of the semiconductor device of the thirty-sixth embodiment.
[0119]
In the present embodiment, the long sides of the memory cell regions 5a and 5b are connected by the bus 15a, the long sides of the memory cell regions 5c and 5d are connected by the bus 15c, and the bus 15a and the bus 15c are connected by the bus 15b. Are connected to the bus 15b. This configuration is suitable for outputting from two sides of the chip.
[0120]
FIG. 41 is a diagram showing a configuration of the semiconductor device according to the thirty-seventh embodiment.
[0121]
In the present embodiment, the long sides of the memory cell regions 5a and 5b are connected by a bus 15a, the long sides of the memory cell regions 5c and 5d are connected by a bus 15c, and the left side of the CPU and the bus 15a, and the right side of the CPU and the bus are connected. 15c is connected. In this configuration, parallel access is possible by separately controlling the memory cell regions connected to the two buses. Therefore, this configuration is appropriate when the size and usage of the memory cell areas of the respective systems are different.
[0122]
FIG. 42 is a diagram showing a configuration of the semiconductor device of the thirty-eighth embodiment.
[0123]
In the present embodiment, the long sides of the memory cell regions 5a and 5b are connected by the bus 15a, the long sides of the memory cell regions 5c and 5d are connected by the bus 15c, the bus 15a and the bus 15c are connected by the buses 15b and 15d, The left side of the CPU is connected to the bus 15a.
[0124]
In the embodiment shown in FIG. 43, elements such as a memory cell region are connected to a bus 15 extending in the vertical direction.
[0125]
In the various embodiments described so far, the shape of the CPU has not been touched at all, but in the present invention, a design that takes into account the shape is possible.
[0126]
The CPU generally comprises a control circuit 35 and a data bus unit 37 as shown in FIGS. As shown in FIG. 46, the data bus unit 37 has a configuration in which elements such as a register 39, an ALU 41, a shifter 43, and a bus interface 45 are arranged in a line, and these components extend in the horizontal direction. Connected to other signal lines. Therefore, when the connection portion between the CPU and the bus is in the left side (or right side) direction, the CPU configuration shown in FIG. 44 is shown. When the connection portion with the CPU extension bus is in the upper side (or lower side) direction, FIG. The CPU configuration shown is suitable considering the wiring length.
[0127]
Therefore, in the embodiments shown so far, it is desirable to select a CPU that takes into account the connection between the CPU and the bus. However, in the present invention, the arrangement / wiring can be changed by the program means. Therefore, the present invention is not constrained by the above-described configuration, and a configuration other than the illustrated internal configuration of the CPU can be produced by programming. The CPU may have a structure with different assembly languages, and CISC and RISC may be mixed. Furthermore, there may be a calculation mechanism different from the conventional one, for example, an analog calculation unit based on the quantum effect in the CPU unit.
[0128]
Next, the configuration and operation of the program means for changing the wiring between the CPU and the memory cell area and the function of each module provided in the present invention will be described.
[0129]
47 and 48 are diagrams for explaining the configuration and operation of the program means, respectively.
[0130]
As shown in FIG. 47, the program means according to the present invention includes a primary parameter input interface P1 for inputting primary parameters, a parameter generating unit P2 for generating secondary parameters from the input primary parameters, and secondary parameters. The processor generation unit P3 for generating processor definition information and the instruction generation unit P4 for generating instructions for operating the processor defined by the processor definition information. The instruction generation unit P4 further includes a compiler generation unit P5, It consists of an assembler generation unit P6.
[0131]
Next, the operation of the program means will be described with reference to FIG.
[0132]
When changing the wiring or function, the user first inputs primary parameters such as the number of registers in the register file, CPU bit width, data memory size, and instruction memory size (step S1). The processor definition information output step S2 is started by the input of the primary parameter, the instruction system storage step S3 for storing the instruction system consisting of a plurality of fields, the field for calculating the length of each field constituting the instruction according to the primary parameter A length calculation step S4, a processor definition information generation step S5 for generating processor definition information based on the stored instruction system and the length of each field are performed. Thereby, the definition of the processor is completed.
[0133]
On the other hand, the command output step S6 for operating the generated processor is started by the input of the primary parameter.
[0134]
Here, the instruction output step S6 includes an instruction system storage step S7 for storing an instruction system composed of a plurality of fields, a field length calculation step S8 for calculating the length of each field constituting the instruction according to the primary parameters, and stored. This comprises an instruction generation step S9 for translating a program written in a predetermined programming language and generating an instruction based on the instruction system and the length of each field.
[0135]
The instruction generation step S9 further includes a compiler generation step S10 and an assembler generation step S11.
[0136]
Through the above steps, an instruction for operating the processor is created.
[0137]
Next, the operation of the processor defined using the created instruction is simulated (step S12). Then, if the processor performs a desired operation, the programming ends. If the desired operation is not performed, the value of the primary parameter is changed again, and the processor is defined again.
[0138]
As described above, the wiring between the processor unit and the memory unit and the function of each module can be arbitrarily changed only by programming.
[0139]
In the embodiment described above, it is desirable that a single or a plurality of modules have a programmable address decoder, a programmable hierarchical bit line arrangement, a programmable input / output device, or such a function. Each portion of the array of one or more modules can be selectively mode programmed.
[0140]
Furthermore, it is desirable that a field programmable memory array and a field programmable gate array (hereinafter abbreviated as FPGA) are incorporated together with programmable resources.
[0141]
Further, in the semiconductor device according to the present invention, a memory cell for holding data, a first word line for transmitting a first selection signal, a first bit line, and a first bit line A first selective coupling circuit disposed between the memory cells; an output interface connected to the memory cell for transmitting a signal from the memory cell; and a memory cell for transmitting a signal to the memory cell It is preferable that the first selective coupling circuit has a first data line and the bit line and the memory cell are selectively coupled in accordance with a selection signal.
[0142]
In the above configuration, the second bit line, the second word line for transmitting the read enable signal, and the second selection arranged between the second bit line and the memory cell are further provided. And the first select signal is a write enable signal, and the first bit line is connected to the memory cell when the first select signal is enabled by the write enable signal. When data to be stored is transmitted and the second selective coupling circuit is enabled by the read enable signal, the second selective coupling circuit selectively selects between the second bit line and the memory cell. It may be configured to be coupled to enable reading of the memory cell.
[0143]
Further, a third bit line for transmitting alternative data stored in the memory cell, a third word line for transmitting an alternative write enable signal, a third bit line, A third selective coupling circuit disposed between the first data line and the third selective coupling circuit, when enabled by the alternative write enable signal; It is also desirable to have a configuration in which the first data lines are coupled to each other and further alternative data is transmitted to the memory cells.
[0144]
The semiconductor device of the present invention includes a memory cell for holding data, a plurality of word lines for transmitting an enable signal, a plurality of bit lines, a plurality of selective coupling circuits, and a plurality of selective coupling circuits. Each of the selective coupling circuits constituting the memory cell is arranged between the memory cell and the bit line and selectively couples between the bit line and the memory cell when enabled by an enable signal of the associated word line of the word line. The configuration may be such that a signal is transmitted.
[0145]
Further, in the above configuration, the reset word line of the word line transmits a reset enable signal, the reset bit line of the bit line is connected to a fixed power source for transmitting a reset level signal, and A first selective coupling circuit of the selective coupling circuits is arranged between a reset bit line and the memory cell, and when enabled by a reset enable signal of a reset word line, selects the memory cell as the reset bit line. It is desirable that the reset level signal be stored in the memory cell.
[0146]
Further, the memory cell is part of a memory array coupled to an FPGA, the FPGA state machine provides access to the memory array from the FPGA, and the word line program word line is enabled by the state machine. A program enable signal is transmitted, the program bit line of the bit line transmits program data from the state machine, and the first selective coupling circuit is disposed between the memory cell and the program bit line. Preferably, the memory cell is selectively coupled to the program bit line when enabled by the program enable signal to store program data from the state machine in the memory cell. .
[0147]
Further, a second word line of the plurality of word lines transmits a second enable signal, and a second bit line of the plurality of bit lines transmits second data of a second source. The second selective coupling circuit of the plurality of selective coupling circuits is disposed between the memory cell and the second bit line, and is enabled by the enable signal by the second enable signal. Preferably, the memory cell is selectively coupled to the second bit line and the second data is stored in the memory cell.
[0148]
The memory cell is a part of a memory array, a serial input terminal for receiving serial input data, a first selective coupling circuit disposed between the serial input terminal and the memory cell, and data And a second selective coupling circuit disposed between the memory cell and the second memory cell, wherein the first selective coupling circuit includes a first scan When enabled by the clock, the serial input data of the serial input terminal is selectively transmitted to the memory cell for storing, and the second selective coupling circuit is enabled by the second scan clock. The memory cell selectively transmits data of the memory cell to a second memory cell, and the memory cell receives an enable signal associated with the plurality of bit lines or a first scan clock from a serial input terminal. It may be such a structure as to receive data by click.
[0149]
Further, an N-bit address input terminal for addressing the memory array and an address decoder circuit for decoding a specific address of the address input terminal and providing an enable signal associated with the plurality of bit lines are provided. It is also desirable.
[0150]
Furthermore, the semiconductor device according to the present invention includes an array of memory cells that can be addressed by bit lines and word lines, and can be addressed by a first word line that enables first data access to itself. Between one memory cell, a second memory cell addressable by a second word line enabling first data access to itself, and between the first memory cell and the second memory cell A transfer cell arranged to store intermediate data and a first cell enabled by a first clock to selectively couple between the transfer cell and the first memory cell to enable data transmission; A selective coupling circuit, enabled by a second clock, having a transfer cell and a second selective coupling circuit, wherein the first clock and the second clock operate continuously; It is also desirable from the one of the two memory cells is configured to perform the data transfer to the other.
[0151]
Further, in order to transfer data from the first memory cell to the second memory cell, the first clock and the second clock are respectively used as a first phase push clock and a second phase push clock. It is also desirable to have a means for providing continuously.
[0152]
An input terminal for receiving data provided in the transfer cell; an output terminal for sending data according to intermediate data stored in the transfer cell; and the first memory. An input terminal for receiving data provided in the cell and the second memory cell, and data is transmitted according to data stored in the first memory cell and the second memory cell. Intermediate data stored in the transfer cell is updated according to the data received at the input terminal, and the first selective coupling circuit includes the output terminal of the first memory cell and the output terminal of the first memory cell. The second selective coupling circuit is arranged between the input terminal of the transfer cell, and the second selective coupling circuit is arranged between the output terminal of the transfer cell and the input terminal of the second memory cell. It is also desirable that the UNA configuration.
[0153]
【The invention's effect】
As described above, in the present invention, since the memory cell areas are symmetrically arranged three-dimensionally with the processor portion as the center of symmetry, the degree of integration can be improved and high-speed instruction processing is possible.
[Brief description of the drawings]
FIG. 1 is a schematic diagram for explaining a configuration of a semiconductor device according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram for explaining a configuration of a second embodiment of a semiconductor device according to the present invention;
FIG. 3 is a schematic diagram for explaining a configuration of a third embodiment of a semiconductor device according to the present invention;
FIG. 4 is a schematic diagram for explaining a configuration of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 5 is a schematic view for explaining a configuration of a semiconductor device according to a fifth embodiment of the present invention.
FIG. 6 is a schematic diagram for explaining a configuration of a sixth embodiment of a semiconductor device according to the present invention;
FIG. 7 is a schematic diagram for explaining a configuration of a seventh embodiment of a semiconductor device according to the present invention;
FIG. 8 is a schematic view for explaining a configuration of an eighth embodiment of a semiconductor device according to the present invention;
FIG. 9 is a schematic diagram for explaining a configuration of a ninth embodiment of a semiconductor device according to the present invention;
FIG. 10 is a schematic diagram for explaining a configuration of a tenth embodiment of a semiconductor device according to the present invention;
FIG. 11 is a schematic diagram for explaining a configuration of an eleventh embodiment of a semiconductor device according to the present invention;
FIG. 12 is a schematic diagram for explaining a configuration of a twelfth embodiment of a semiconductor device according to the present invention;
FIG. 13 is a schematic diagram for explaining a configuration of a thirteenth embodiment of a semiconductor device according to the present invention;
FIG. 14 is a schematic diagram for explaining the configuration of a fourteenth embodiment of a semiconductor device according to the present invention;
FIG. 15 is a schematic view for explaining a configuration of a fifteenth embodiment of a semiconductor device according to the present invention;
FIG. 16 is a schematic diagram for explaining a configuration of a sixteenth embodiment of a semiconductor device according to the present invention;
FIG. 17 is a schematic diagram for explaining a configuration of a seventeenth embodiment of a semiconductor device according to the present invention;
FIG. 18 is a schematic diagram for explaining the configuration of an eighteenth embodiment of a semiconductor device according to the present invention;
FIG. 19 is a schematic diagram for explaining a configuration of a nineteenth embodiment of a semiconductor device according to the present invention;
FIG. 20 is a schematic diagram for explaining a configuration of a twentieth embodiment of a semiconductor device according to the present invention;
FIG. 21 is a schematic diagram for explaining the configuration of a twenty-first embodiment of a semiconductor device according to the present invention;
FIG. 22 is a schematic diagram for explaining a configuration of a twenty-second embodiment of a semiconductor device according to the present invention;
FIG. 23 is a schematic diagram for explaining a configuration of a twenty-third embodiment of a semiconductor device according to the present invention;
FIG. 24 is a schematic diagram for explaining a configuration of a twenty-fourth embodiment of a semiconductor device according to the present invention;
FIG. 25 is a schematic diagram for explaining a configuration of a twenty-fifth embodiment of a semiconductor device according to the present invention;
FIG. 26 is a schematic diagram for explaining a configuration of a twenty-sixth embodiment of a semiconductor device according to the present invention;
FIG. 27 is a schematic diagram for explaining the configuration of a twenty-seventh embodiment of a semiconductor device according to the present invention;
FIG. 28 is a schematic diagram for explaining a configuration of a twenty-eighth embodiment of a semiconductor device according to the present invention;
FIG. 29 is a schematic diagram for explaining a configuration of a twenty-ninth embodiment of a semiconductor device according to the present invention;
FIG. 30 is a schematic diagram for explaining a configuration of a thirtieth embodiment of a semiconductor device according to the present invention;
FIG. 31 is a schematic diagram for explaining a configuration of a thirty-first embodiment of a semiconductor device according to the present invention;
FIG. 32 is a schematic diagram for explaining an embodiment of a buffer according to the present invention.
FIG. 33 is a schematic diagram for explaining another embodiment of the buffer according to the present invention.
FIG. 34 is a schematic diagram for explaining another embodiment of the buffer according to the present invention.
FIG. 35 is a schematic diagram for explaining another embodiment of the buffer according to the present invention.
FIG. 36 is a schematic diagram for explaining a configuration of a thirty-second embodiment of a semiconductor device according to the present invention;
FIG. 37 is a schematic diagram for explaining a configuration of a thirty-third embodiment of a semiconductor device according to the present invention;
FIG. 38 is a schematic diagram for explaining a configuration of a thirty-fourth embodiment of a semiconductor device according to the present invention;
FIG. 39 is a schematic diagram for explaining a configuration of a thirty-fifth embodiment of a semiconductor device according to the present invention;
FIG. 40 is a schematic diagram for explaining the configuration of a thirty-sixth embodiment of a semiconductor device according to the present invention;
FIG. 41 is a schematic diagram for explaining a configuration of a thirty-seventh embodiment of a semiconductor device according to the present invention;
FIG. 42 is a schematic diagram for explaining a configuration of a thirty-eighth embodiment of a semiconductor device according to the present invention;
FIG. 43 is a schematic diagram for explaining a configuration of a thirty-ninth embodiment of a semiconductor device according to the present invention;
FIG. 44 is a schematic diagram for explaining a configuration of a CPU;
FIG. 45 is a schematic diagram for explaining a configuration of a CPU;
FIG. 46 is a schematic diagram for explaining the configuration of a data bus unit;
FIG. 47 is a schematic diagram for explaining the configuration of an embodiment of the program means according to the present invention.
FIG. 48 is a flowchart for explaining the operation of an embodiment of the program means according to the present invention.
FIG. 49 is a schematic diagram for explaining a conventional semiconductor device.
[Explanation of symbols]
1 chip
3, 3a, 3b CPU
5, 5a, 5b, 5c, 5d Memory cell region
7 Wiring means
9 I / O interface
11 Light emitting / receiving means
13 Memory cell area with I / O interface
15, 15a, 15b, 15c, 15d bus
17 Program means
19 Bus interface
21 Peripheral circuits
23, 23a, 23b buffer
25, 25a, 25b Latch
27 Driver
29, 29a, 29b Cache memory
31 pads
33 Clock signal line
35 Control circuit
37 Data bus section
39 registers
41 ALU
43 Shifter
45 Bus interface

Claims (3)

A processor unit for executing operations;
A plurality of rectangular memory cell regions having a short side portion and a long side portion that are three-dimensionally symmetrically arranged with the processor portion as a symmetry center;
A plurality of wiring means connected to the long sides of the plurality of memory cell regions, and transmitting information between the processor unit and the memory cell region;
Wherein said processor unit a plurality of memory cell regions are arranged in one chip,
The semiconductor device according to claim 1, wherein the processor unit controls the plurality of memory cell regions for each wiring unit system.   2. The semiconductor device according to claim 1, further comprising a program unit for changing a wiring relation between the processor unit and the memory cell region and a function of each unit.   3. The semiconductor device according to claim 1, further comprising light receiving / light emitting means for receiving an optical signal from the processor unit and the memory cell region and further transmitting the optical signal.

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