JP4186575B2 - Memory access device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory access device, and in particular, in a multiprocessor system, the priority of a memory access request is determined according to the frequency of the memory access request transmitted from the processor, and the memory access bandwidth assigned to each priority is dynamically determined. It is related with the memory access apparatus with the favorable response characteristic with respect to a memory access request.
[0002]
[Prior art]
In a shared memory type multiprocessor system, there are access requests to a shared memory from a plurality of processors, and thus it is necessary to prevent contention of these access requests.
[0003]
As a conventional multiprocessor system for performing memory access, there is a configuration example as shown in FIG.
[0004]
In this conventional configuration example, the request count circuit 105 counts the number of transmissions in each shared memory request signal transmitted from the plurality of CPUs 101 a to 103 c. The request count circuit 105 determines the priority of the shared memory request signal according to the number of times the shared memory request signal is transmitted, and notifies the arbitration circuit 106 of the priority. The arbitration circuit 106 preferentially processes the shared memory request from the CPU having the highest priority. (For example, see Patent Document 1)
[0005]
The priority classification method and the bandwidth allocation method for each classified priority include, for example, a classification method based on TOS (Type Of Service) information in the IPv4 protocol, and a bandwidth allocation method for each TOS information unit. There is. Specifically, in the classification method based on TOS information, a TOS class is assigned in advance to an application unit or an IP terminal unit in the IP protocol. In addition, a method of allocating a bandwidth to each TOS information unit is employed. (For example, see Non-Patent Document 1)
[0006]
[Patent Document 1]
Japanese Unexamined Patent Publication No. 1-263762 (page 4, FIG. 1)
[Non-Patent Document 1]
University of Southern California, “IETF RFC791”, [online]
September 1981, Internet Engineering Task Force, [2002 August
Search 26th of March], Internet <URL: http://www.ietf.org/rfc/
rfc0791.txt? number = 791>
[0007]
[Problems to be solved by the invention]
The problem in the multiprocessor system described in Patent Document 1 is that when the load of a processor (CPU) in the multiprocessor suddenly increases and the number of memory accesses increases rapidly, the priority of the high-load CPU is increased. It is a point that always becomes high. As a result, access to the high load CPU is always processed preferentially, memory access from other CPUs becomes impossible, or delay in memory access speed increases rapidly. In addition, the throughput of the entire multiprocessor system may be reduced.
[0008]
Further, problems in the classification method based on TOS (Type Of Service) information in the IPv4 protocol described in Non-Patent Document 1 and the bandwidth allocation method in the TOS information unit will be described below. Here, when these classification and bandwidth allocation methods are applied to the multiprocessor system described in Patent Document 1, each processor is considered to be equivalent to an application on an IP protocol or an IP terminal, and a priority class is assigned to each processor. And the bandwidth is allocated according to the priority class.
[0009]
In this case, a memory access request from a processor having a high priority is always processed regardless of the load on each processor. As a result, even if the load on a processor with low priority increases, the memory access request of the processor is rarely accepted, and the processing of the processor cannot be accelerated. For this reason, processing in a low priority and high load processor becomes a bottleneck, which also causes a problem that the throughput of the entire multiprocessor system is lowered.
[0010]
SUMMARY OF THE INVENTION An object of the present invention is to provide a memory access device that solves the above problems.
[0011]
[Means for Solving the Problems]
In order to solve the above-described problem, in the memory access device of the present invention, a scheduler unit that manages a bandwidth of memory access to a plurality of command queues that store the memory access request, and management information from the scheduler unit are used. Reading a memory access request from one command queue of the plurality of command queues, and executing the memory access, and issuing the memory access request to one command queue of the plurality of command queues The control unit is configured to request the scheduler unit to change the band in accordance with the frequency.
[0012]
By adopting such a configuration, the memory access device of the present invention can perform a memory access process following the load fluctuation of each processor, and realizes a high response characteristic to a memory access request.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the internal configuration of the memory access device 20 of the present invention shown in FIG.
[0014]
The processors 10 to 1n are a plurality (n) of processors connected to the memory access device 20. The processors 10 to 1 n read / write data from / to the shared memory 30 via the memory access device 20.
[0015]
The memory access unit 40 in the memory access device 20 has an interface function between the memory access device 20 and the shared memory 30. The memory access unit 40 reads a memory access request from the command queue instructed by the scheduler unit 60 in the command queues 80 to 8m, and executes the command.
[0016]
The scheduler unit 60 manages a memory access band for each of the command queues 80 to 8m.
[0017]
The interface unit 70 distributes memory access requests from the processors 10 to 1n to the command queues 80 to 8m in accordance with instructions from the control unit 50.
[0018]
The command queues 80 to 8m store memory access requests transmitted from the processors 10 to 1n via the interface unit 70.
[0019]
When the frequency of sending a memory access request to a certain command queue exceeds or falls below a certain amount, the control unit 50 requests the scheduler unit 60 to change the bandwidth.
[0020]
Hereinafter, the detailed operation of the memory access device 20 having the above configuration will be described as an example in the case of processing an IP packet.
[0021]
The IP packet data is stored in the shared memory 30, and the processors 10 to 1n read and write necessary data from the shared memory 30 to perform IP packet processing. Here, the load of the processors 10 to 1n in the IP packet processing varies depending on the processing contents and the increase / decrease of traffic. Due to these fluctuations, the frequency of sending memory access requests from the processors 10 to 1n to the shared memory 30 changes.
[0022]
Here, the control unit 50 monitors the transmission frequency of the memory access request passing through the interface unit 70 in units of processors 10 to 1n. Then, the control unit 50 controls the interface unit 70 so that a memory access request from a processor having a high transmission frequency is input to the command queue 80, for example. On the contrary, the control unit 50 controls the interface unit 70 so that a memory access request from a processor with a low transmission frequency is input to the command queue 8m, for example.
[0023]
That is, the control unit 50 controls the interface unit 70 so that the memory access requests from the processors 10 to 1n are distributed to the command queues 80 to 8m according to the frequency of sending the memory access requests. Here, the control unit 50 has a plurality of thresholds for the number of memory access request transmissions from each processor per fixed time, and determines a memory access request distribution destination using the thresholds.
[0024]
As an example, assuming that the access time per one time to the memory is 100 ns, this memory can be accessed up to 10 7 times (10M times / s) per second. Therefore, as the threshold value, “4M times / s or more”, “3M times / s or more to less than 4M times / s”, “2M times / s or more to less than 3M times / s”, and so on are set. In addition, when the number of memory access request transmissions is 4M times / s or more, an access request is input to the command queue 80. When the number of memory access request transmissions is 3M times / s or more to less than 4M times / s For example, “If an access request is sent to the command queue 81”, “If the memory access request transmission number is 2M times / s or more and less than 3M times / s, an access request is sent to the command queue 82”. To do.
[0025]
As described above, the frequency of transmission of memory access requests from the processors 10 to 1n dynamically changes depending on the processor load and processing contents. For example, the transmission destination of the memory access request from the processor 10 is the command queue 80 when the load is high, but is changed to one of the command queues 81 to 8m when the load is low.
[0026]
With the operation described above, memory access requests are queued in the command queues 80 to 8m in accordance with the frequency of issuing memory access requests.
[0027]
The scheduler unit 60 manages the memory access bandwidth between the memory access device 20 and the shared memory 30 by dividing it into command queue units. The bandwidth allocation to the command queues 80 to 8m is performed using, for example, the number of memory accesses to the shared memory 30 per certain time. In this embodiment, the scheduler unit 60 allocates the most bandwidth to the command queue 80 and allocates the least bandwidth to the command queue 8m. The scheduler unit 60 instructs the memory access unit 40 from which command queue the memory access request is read according to the allocated bandwidth.
[0028]
The memory access unit 40 reads a memory access request from the command queue in accordance with an instruction from the scheduler unit 60 and executes memory access. That is, the memory access unit 40 writes data from the processor that is the source of the memory access request, or reads data from the processor.
[0029]
Here, if the memory access request does not stay in the command queue having a higher priority than the command queue of a certain priority class, the memory access unit 40 extracts the memory access request from the command queue and transmits the memory access request. Data is written from the original processor or data is read from the processor.
[0030]
When all the loads on the processors 10 to 1n are increased, the frequency of sending memory access requests to the command queue 80 is increased. As a result, the memory access request stays in the command queue 80. As described above, when the frequency of sending a memory access request to a specific command queue increases, the control unit 50 requests the scheduler unit 60 to change the bandwidth to the command queue. Then, the scheduler unit 60 redistributes the bandwidth allocation to each command queue according to the request from the control unit 50 and increases the bandwidth to the command queue 80. As described above, when the memory access bandwidth is dynamically changed, memory access from the processor with the highest load is preferentially processed at that time.
[0031]
Here, even in the same packet processing, since the processing contents differ depending on the packet length and packet type, the number of memory accesses also varies. For example, since error check processing in UDP (User Datagram Protocol) targets the entire packet data, the number of memory accesses varies depending on the packet length. Further, when an option is added to the header portion of the IP packet, the content of packet processing changes from normal processing, and the number of memory accesses changes.
[0032]
Therefore, if the memory access bandwidth can be changed dynamically, the number of memory accesses that can be issued per fixed time can be changed, and the change in the number of memory accesses as described above can be followed. Therefore, only the memory access of a processor in a plurality of processors is not delayed, and the response performance to the memory access of the entire multiprocessor system is improved.
[0033]
In the first embodiment, the priority classification is performed according to the frequency of issuing memory access requests from the processors 10 to 1n. However, as the second embodiment, the processing task unit or processing thread unit in each processor is used. Priority classification may be performed according to the frequency of sending memory access requests.
[0034]
As a third embodiment, a combination of a processor and a processing task unit or a processing thread unit in the processor may be created, and priority classification may be performed according to the frequency of issuing memory access requests in the combination unit.
[0035]
Further, as a fourth embodiment, the memory access request transmission frequency may be counted without distinguishing between a memory read command and a memory write command, or each command may be counted separately. . When the distinction is made, classification may be performed by giving different priorities to memory reading and memory writing.
[0036]
【The invention's effect】
The present invention has the following effects.
[0037]
The first effect is that the response characteristic to the memory access request can be improved by dynamically changing the memory access bandwidth in accordance with the frequency of issuing the memory access request to the command queue. It is possible to eliminate the bottleneck of memory access contention.
[0038]
The second effect is that by dynamically changing the memory access band according to the priority, it is possible to speed up the processing in the processor with a high load and guarantee the memory access to the processor with a low load. The throughput of the entire processor system can be improved.
[0039]
The third effect is that by dynamically changing the memory access band, it becomes possible to absorb the traffic fluctuation to each processor, and the programming of the memory access method corresponding to each processor can be simplified.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of a memory access device according to the present invention.
FIG. 2 is a block diagram illustrating a configuration example of a conventional memory access device.
[Explanation of symbols]
10 to 1n Processor 20 Memory access device 30 Shared memory 40 Memory access unit 50 Control unit 60 Scheduler unit 70 Interface unit 80 to 8m Command queue

Claims (9)

A memory access device for accessing a shared memory from a plurality of processors,
The memory access device is:
A plurality of command queues for storing memory access requests to the shared memory;
A scheduler unit that manages a bandwidth of memory access between each of the plurality of command queues and the shared memory in units of the command queue ;
Using the management information from the scheduler unit, a memory access request is read from each of the plurality of command queues, and the memory access is executed.
A controller that requests the scheduler unit to change the bandwidth between each of the plurality of command queues and the shared memory in response to the frequency of transmission of memory access requests from each of the command queues ;
A memory access device comprising: The memory access device is:
A memory access request from the processor, an interface unit for distributing to the command queue in accordance with an instruction from the control unit, further comprising that the memory access apparatus according to claim 1, wherein. The priority of the memory access request to the shared memory is determined according to the frequency of transmission of the memory access request from the plurality of processors, and a memory access bandwidth is allocated for each priority. The memory access device according to 1. The priority of the memory access request to the shared memory is determined according to the frequency of transmission of the memory access request from each processing task or each processing thread in the plurality of processors, and the memory access bandwidth for each priority The memory access device according to claim 1, wherein the memory access device is assigned. The transmission frequency of the memory access request to the shared memory is one of the number of read commands, the number of write commands per certain time for the shared memory, or the total of the number of read commands and the number of write commands. 5. The memory access device according to claim 3, wherein the memory access device is a memory access device. The memory access bandwidth allocated to the priority can be dynamically changed when the transmission frequency of the memory access request to the shared memory is concentrated on a specific priority. The memory access device according to claim 1. The control unit has a plurality of thresholds with respect to the transmission frequency of the memory access request per fixed time from the processor, and assigned to the priority using the presence / absence of the transmission frequency to the plurality of thresholds 7. The memory access device according to claim 1, wherein the allocation of the memory access band is changed. A memory access method for accessing shared memory from a plurality of processors,
A distribution step of distributing memory requests to the shared memory to a plurality of command queues;
A management step of managing a bandwidth of memory access between each of the plurality of command queues and the shared memory;
Using the management information managed in the management step, a memory access request is read from each of the plurality of command queues, and the memory access is executed,
Bandwidth between each of the plurality of command queues managed in the management step and the shared memory in correspondence with the frequency of transmission of memory access requests from each of the command queues Request steps to request changes
A memory access method comprising: 9. The distribution step is characterized in that a ratio of distributing memory requests to the shared memory to the plurality of command queues according to a change in a bandwidth of the memory access is changed in the memory access request from the processor. The memory access method described.

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