JP4058234B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor logic circuit having a multilayer wiring structure that achieves both low power consumption and high speed.
[0002]
[Prior art]
In a large-scale integrated semiconductor logic circuit composed of CMOS transistors, semiconductor elements are further miniaturized. On the other hand, the chip size is increasing year by year, and the wiring length in the chip is becoming longer.
[0003]
As the wiring length in the chip becomes longer, the wiring resistance and wiring capacitance become larger than the channel resistance and diffusion layer capacitance of the transistor that drives the wiring. Then, since the operation speed of the circuit is determined by the product of the wiring resistance and the wiring capacitance, the operation speed of the device is not further increased no matter how fast the semiconductor element such as a transistor becomes.
[0004]
For this reason, the operation speed of the circuit can be improved by increasing the wiring film thickness or wiring width to reduce the resistance, and widening the wiring interval to reduce the wiring capacitance. However, simply increasing the wiring film thickness and widening the wiring interval is not suitable for wiring an increasingly highly integrated logic circuit.
[0005]
Therefore, as a wiring structure suitable for a highly integrated logic circuit, there is a multilayer wiring structure having a plurality of wirings on a semiconductor chip. Of the logic circuits formed on the semiconductor chip, wiring between adjacent logic circuits is performed by a lower layer local wiring with a reduced wiring pitch, and wiring between separated logic circuits is performed by an upper layer global wiring. In the global wiring, the wiring film thickness and the wiring width are made larger than the local wiring, and the wiring interval is widened (Japanese Patent Laid-Open No. 6-13590).
[0006]
However, the clock frequency of the logic circuit increases with the scaling of miniaturization, and the number of wirings in the wiring layer also increases. Therefore, there is a problem that the power required for charging and discharging the capacitance of the wiring layer is greatly increased even in the multilayer wiring structure described above. .
[0007]
In the conventional multilayer wiring structure, it is difficult to reduce the electric power accompanying the charging / discharging of the wiring capacity while improving the wiring delay without increasing the number of wiring layers.
[0008]
[Problems to be solved by the invention]
The present invention has been made to solve the above problems, and reduces wiring delay and achieves both low power consumption and high speed without significantly changing the circuit layout and wiring structure of a CMOS logic circuit. An object of the present invention is to provide a semiconductor device.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, a first aspect of the present invention includes a semiconductor substrate,
A semiconductor element circuit formed on the semiconductor substrate;
A first wiring layer formed on the semiconductor substrate via an insulating film and electrically connected to the semiconductor element;
A second wiring layer formed on the first wiring layer via an insulating film;
A third wiring layer formed on the second wiring layer via an insulating film,
The wiring thickness of the first wiring layer is smaller than the wiring thickness of the second wiring layer and the wiring thickness of the third wiring layer,
A distance between the first wiring layer and the second wiring layer is greater than a distance between the second wiring layer and the third wiring layer.
[0010]
At this time, it is preferable that the first wiring layer, the second wiring layer, and the third wiring layer are laminated in this order without any other wiring layers.
[0011]
  At this time, the distance between the first wiring layer and the second wiring layerIs, Distance between the second wiring layer and the third wiring layerEqual to or greater than 1.7 timesIt is preferable that
[0012]
Further, it is preferable that an interval between adjacent wires in the first wiring layer is smaller than an interval between adjacent wires in the second wiring layer and an interval between adjacent wires in the third wiring layer. .
[0013]
The wiring width of the first wiring layer is preferably smaller than the wiring width of the second wiring layer and the wiring width of the third wiring layer.
[0014]
In addition, it is preferable that the wiring of the first wiring layer and the wiring of the second wiring layer have a crossover layout.
[0015]
  Further, the second wiringLayer andThe third wiringLayeredThe voltage amplitude is the first wiringLayer of electricityThe pressure amplitude is preferably smaller than the pressure amplitude.
[0016]
The power supply voltage of the semiconductor element is V_DDThen, the voltage amplitude of the first wiring layer is also V_DDIt is preferable that
[0017]
Further, the voltage amplitude of the second wiring layer is set to V₁Then, the distance between the first wiring layer and the second wiring layer is the distance (V) between the second wiring layer and the third wiring layer._DD/ V₁)^1.5It is preferable to be larger than twice.
[0018]
Further, it is preferable that the first wiring layer is directly connected to the semiconductor element.
[0019]
  The second wiring layerMultiple arrangementsThe voltage amplitude of the line is preferably 0.48 VDD or less.
[0020]
The second invention is a semiconductor substrate;
A semiconductor element formed on the semiconductor substrate;
A first wiring layer formed on the semiconductor substrate via an insulating film and electrically connected to the semiconductor element;
A second wiring layer formed on the first wiring layer via an insulating film;
A third wiring layer formed on the second wiring layer via an insulating film;
A fourth wiring layer formed on the third wiring layer via an insulating film,
The wiring thickness of the first wiring layer is smaller than the wiring thickness of the second wiring layer, the third wiring layer, and the fourth wiring layer,
A distance between the first wiring layer and the second wiring layer is greater than a distance between the third wiring layer and the fourth wiring layer.
[0021]
At this time, it is preferable that the first wiring layer, the second wiring layer, and the third wiring layer are laminated in this order without any other wiring layers.
[0022]
  At this time, the distance between the first wiring layer and the second wiring layerIs, Distance between the third wiring layer and the fourth wiring layerIs equal to or greater than 1.7 timesIt is preferable to increase.
[0023]
  Further, the interval between adjacent wires in the first wiring layer is smaller than the interval between adjacent wires in the second wiring layer and the interval between adjacent wires in the third wiring layer.Is preferred.
[0024]
Moreover, it is preferable that the space | interval of the adjacent wiring of the said 1st wiring layer is smaller than the space | interval of the adjacent wiring of the said 4th wiring layer.
[0025]
In addition, it is preferable that the wiring of the first wiring layer and the wiring of the second wiring layer have a crossover layout.
[0026]
  Further, the second wiring layerThe voltage amplitudes of the third wiring layer and the fourth wiring layer are the same as the first wiring layer.It is preferable that the voltage amplitude is smaller.
[0027]
The power supply voltage of the semiconductor element is V_DDThen, the voltage amplitude of the first wiring layer is also V_DDIt is preferable that
[0028]
Further, the voltage amplitude of the second wiring layer is set to V₁Then, the distance between the first wiring layer and the second wiring layer is (V) between the third wiring layer and the fourth wiring layer._DD/ V₁)^1.5It is preferable to be larger than twice.
[0029]
Further, it is preferable that the first wiring layer is directly connected to the semiconductor element.
[0030]
  Further, the second signal wiring layerMultiple arrangementsThe voltage amplitude of the line is preferably 0.48 VDD or less.
[0031]
In the present invention, the power supply voltage is V_DD, The voltage amplitude of the global wiring composed of the second signal wiring layer and the third signal wiring layer is represented by V_DDSmaller voltage V₁When the distance between the first signal wiring layer (local wiring layer) and the second signal wiring layer is H1, and the distance between the second signal wiring layer and the third signal wiring layer is H2, H1> 0.4 ×. H2 (V_DD / V₁) So that H1 is larger than H2 so that the voltage amplitude V at the local wiring layer_DDCan be prevented from malfunctioning on the global wiring due to capacitive coupling.
[0032]
Further, according to the present invention, since the voltage amplitude in the global wiring layer is made smaller than the voltage amplitude in the local wiring layer, charging / discharging in the global wiring layer can be reduced, so that lower power consumption can be realized.
[0033]
The present invention also includes a semiconductor substrate,
A semiconductor element formed on the semiconductor substrate;
A local wiring layer formed on the semiconductor substrate via an insulating film and electrically connecting the semiconductor elements;
A first wiring layer formed on the local wiring layer via an insulating film and electrically connected to the local wiring layer; and a second wiring layer formed thereon,
The wiring thickness of the local wiring layer is thinner than the wiring thickness of the first wiring layer and the wiring thickness of the second wiring layer,
A distance between the local wiring layer and the first wiring layer is greater than a distance between the first wiring layer and the second wiring layer.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
[0035]
(Embodiment 1)
FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention, and FIG. 4 shows a planar layout of each layer when an internal structure of a wiring layer is viewed from obliquely above. In FIG. 4, in order to make the wiring layer easier to understand, the semiconductor substrate region and the contact are omitted, and the connection relationship between the contact and the wiring is shown by a dotted line.
[0036]
In the present embodiment, the wiring layers are a local wiring layer (wiring layer 4 and first wiring layer 1) and a global wiring layer (second wiring layer 2 and third wiring layer 3) formed on the local wiring layer. ). The distance between the global wiring layer and the local wiring layer is wider than the distance between the global wiring layers, the wiring film thickness of the global wiring layer is made larger than the wiring film thickness of the local wiring layer, and the voltage amplitude of the global wiring layer is It is lower than the voltage amplitude of the layer. The wiring layer 1 is a first wiring layer, the wiring layer 2 is a second wiring layer, and the wiring layer 3 is a third wiring layer. The wiring layer 4 is formed below the first wiring layer 1 and functions as a local wiring layer. This will be described in more detail below.
[0037]
As shown in FIG. 1, a semiconductor substrate 10 is made of boron or indium with an impurity concentration of 10¹⁴~Ten¹⁸cm^-3It is formed of a p-type semiconductor made of doped silicon, for example.
[0038]
On the p-type semiconductor substrate 10, a MISFET is formed which includes a source / drain region 9, a channel region sandwiched between them, and a gate electrode 8 formed on the channel region via a gate insulating film. Yes. A plurality of these MISFETs are formed and constitute the semiconductor logic circuit 100.
[0039]
Among MISFETs, n-type MISFETs have an impurity concentration of 10¹⁹cm^-3A channel made of the following p-type impurity doped region, a gate insulating film made of a silicon oxide film or silicon nitride film having a thickness of 10 nm or less, and an impurity concentration of 10 formed on the gate insulating film¹⁹cm^-3The polysilicon gate electrode 8 to which the above P (phosphorus) or As (arsenic) is added, and the impurity concentration 10 formed on both sides of the gate electrode 8¹⁹cm^-3The source / drain region 9 is made of an n-type semiconductor region within a depth of 0.5 μm to which P (phosphorus) or As (arsenic) is added. Similarly, a p-type MISFET is formed on the semiconductor substrate 10 to form a switch element of an n-type MISFET and a complementary semiconductor logic circuit.
[0040]
On the semiconductor substrate 10 on which these n-type MISFETs and p-type MISFETs are not formed, an element isolation region 11 made of a silicon oxide film is formed at a depth of 0.05 μm to 1 μm to separate individual MISFETs 100.
[0041]
A wiring layer 4 is formed on the MISFET 100 constituting these logic circuits via an interlayer insulating film 13. A first wiring layer 1 is formed on the wiring layer 4 via an interlayer insulating film 13. The wiring layer 4 and the first wiring layer 1 constitute a local wiring layer. A second wiring layer 2 is formed on the first wiring layer via an interlayer insulating film 13. A third wiring layer 3 is formed on the second wiring layer 2 via an interlayer insulating film 13. The second wiring layer 2 and the third wiring layer 3 constitute a global wiring layer. The interlayer insulating film 13 is made of, for example, a silicon oxide film or a silicon nitride film, and is also formed between the wiring layers 4, the first wiring layer 1, the second wiring layer 2, and the third wiring layer 3.
[0042]
Here, the local wiring layer is connected to the transistors constituting the semiconductor logic circuit 100 on the semiconductor substrate 10. However, when there are two or more wiring layers connected to the transistors constituting the semiconductor logic circuit 100, the present invention The local wiring layer in FIG. 1 covers the lowermost layer to the second layer. The global wiring layer is formed on the local wiring layer and is connected to the local wiring layer. The global wiring layer is formed on the local wiring and has two wiring layers connected to the local wiring layer. When there are more layers, the global wiring layer in the present invention covers the uppermost layer to the second layer. Therefore, to apply the present invention, a multilayer wiring layer having at least one local wiring layer and two global wiring layers is required. In order to avoid increasing the normal wiring capacitance and to provide a contact at an arbitrary position of the element or wiring, if one layer is a wiring extending in the X direction, for example, the other layer is in the Y direction perpendicular to the X direction. The wiring is extended. That is, in order to give each of the local wiring layer and the global wiring layer freedom of contact, a multilayer wiring of four or more layers is required.
Further, the distance between the local wiring layer and the global wiring layer described in the present invention is the distance between the uppermost local wiring layer and the lowermost global wiring layer.
[0043]
Note that the wiring refers to a signal wiring used for signal transmission of the semiconductor logic circuit. The wiring material of each wiring layer 1, 2, 3, 4 can use W, Cu, Al, or AlCu.
[0044]
A wiring contact 7 is formed on the source / drain region 9 of the MISFET on the semiconductor substrate 10 and is connected to the wiring layer 4 in the local wiring layer. The wiring contact 7 is made of W, Ru, TaN, Ti, TiN, Cu, Al, or AlCu, and has a height of 0.1 μm to 2 μm and a diameter of 0.03 μm to 1 μm.
[0045]
The wiring width of the wiring layer 4 is such that the diameter of the contact 7 is made small by minimizing misalignment with the MISFET formed on the semiconductor substrate 10. In this way, the integration density of the MISFET is improved. The contacts 5 and 6 in the wiring layers 1, 2, and 3 positioned above the wiring layer 4 may be larger than this.
[0046]
As described above, the wiring of the wiring layer 4 is a local wiring layer for improving the degree of integration, which is used for a relatively short wiring for connecting adjacent semiconductor logic circuits. Therefore, it is desirable for improving the integration density that the minimum line width of the wiring layer 4 is 0.03 μm to 1 μm, and the minimum wiring layer interval is 0.03 μm to 1 μm, similarly to the wiring width.
[0047]
A wiring contact 5 is formed on the wiring layer 4 and connected to the first wiring layer 1 which is another local wiring layer. The wiring contact 5 is made of W, Ru, TaN, Ti, TiN, Cu, Al, or AlCu, and has a height of 0.03 μm to 1 μm and a diameter of 0.03 μm to 1 μm. The diameter of the wiring contact 5 is preferably equal to or larger than the diameter of the wiring contact 7 in order to reduce the resistance of the contact portion of the first wiring layer 1.
[0048]
The first wiring layer 1 extends in a direction orthogonal to the wiring layer 4 so that the semiconductor logic circuit region 100 disposed at random positions on the semiconductor substrate 10 can be arbitrarily wired. The first wiring layer 1 is also formed with the same film thickness and line width as the wiring layer 4, so that the minimum layout width of the semiconductor logic circuit 100 is made equal in the two-dimensional direction parallel to the wiring lamination surface. It is desirable to facilitate and improve the integration density of the wiring.
[0049]
An interlayer insulating film 13 is deposited on the entire surface of the first wiring layer 1 so as to have a height H1, and a second wiring layer 2 is formed thereon. An interlayer insulating film 13 is deposited on the entire surface of the second wiring layer 2 so as to have a height H2, and a third wiring layer 3 is formed thereon. Both the second wiring layer 2 and the third wiring layer 3 constitute a global wiring layer. The global wiring layer performs wiring at a relatively longer position than the local wiring layer. In addition, the second wiring layer 2 and the third wiring layer 3 extend in a direction orthogonal to each other, and arbitrarily route the semiconductor logic circuit region 100 and local wirings arranged at random positions.
[0050]
A wiring contact 6 is formed on the second wiring layer 2 and connected to the third wiring layer 3. The wiring contact 6 has a height H2 and a diameter of 0.05 μm to 3 μm and is made of W, Ru, Ti, TiN, TaN, Cu, Al, or AlCu, and has a diameter equal to or larger than the diameter of the wiring contact 5. To do.
[0051]
Although not shown in FIGS. 1 and 4, a height H1 and a diameter of 0.05 μm to the local wiring layer and the global wiring layer, that is, between the first wiring layer 1 and the second wiring layer 2. A wiring contact made of W, Ru, TaN, Ti, TiN, Cu, Al, or AlCu is formed at 3 μm, and the layers are connected to each other.
[0052]
The first wiring layer 1 and the second wiring layer 2 are formed so as to extend in a direction orthogonal to the parallel direction rather than in a parallel direction, thereby causing crosstalk between the local wiring layer and the global wiring layer. Desirable to reduce.
[0053]
In the present invention, the wiring film thickness T1 of the first wiring layer 1 and the wiring layer 4 which are local wiring layers is set to the wiring film thickness T2 of the second wiring layer 2 and the third wiring layer 3 which are global wiring layers. It is smaller than the wiring film thickness T3 (T1 <T2, T3). The distance H1 between the local wiring layer and the global wiring layer, that is, the distance H1 between the wiring layer 1 and the wiring layer 2 is the distance H2 between the second wiring layer 2 and the third wiring layer 3 in the global wiring layer. (H1> H2). Further, the wiring intervals S2 and S3 between the second wiring layer 2 and the third wiring layer 3 in the global wiring layer are larger than the wiring interval S1 between the first wiring layer 1 and the wiring layer 4 which are local wiring layers. (S1 <S2, S3). The wiring interval at this time means the minimum wiring interval in the wiring layer.
[0054]
Further, the minimum wiring widths W2 and W3 of the second wiring layer 2 and the third wiring layer 3 which are global wirings are formed to be larger than the minimum wiring width W1 of the local wiring (W1 <W2, W3).
[0055]
In this way, the wiring resistance per unit length in the global wiring layer is reduced and the wiring capacity is further reduced, so the product of the wiring resistance and wiring capacity in the global wiring layer is reduced, and the clock speed is increased. The amount of charging / discharging can be reduced, and the power consumption can be reduced. Specifically, when the wiring width is doubled, the resistance is halved. When the wiring layer interval is doubled, the capacity is halved. When the wiring interval is doubled, the capacity is halved. When the wiring film thickness is doubled, the resistance is halved.
[0056]
Further, when Al or Cu is used as the wiring material of the wiring layers 1, 2, 3, and 4, and an insulating film having a dielectric constant of 4 or less is used as the interlayer insulating film 13, the wiring delay time is optimized while the wiring is optimized. In a structure with an increased integration density, 0.2 × S2 <W2 <5 × S2, 0.2 × S2 <T2 <5 × S2, 0.2 × S3 <W3 <5 × S3, 0.2 ×. The wiring structure is optimized in the range of S3 <T3 <5 × S3.
[0057]
Further, since the distance H1 between the first wiring layer 1 and the second wiring layer 2 is larger than the distance H2 between the second wiring layer 2 and the third wiring layer 3 (H1> H2), Capacitive coupling between the first wiring layer 1 and the second wiring layer 2 can be prevented, and the occurrence of crosstalk noise in the second wiring layer 2 can be prevented.
[0058]
FIG. 2 shows a conventional case where the distance H1 between the first wiring layer 1 and the second wiring layer 2 is smaller than the distance H2 between the second wiring layer 2 and the third wiring layer 3 (H1 <H2). It is a figure which shows the multilayer wiring structure by a comparative example. Other structures are the same as those shown in FIG.
[0059]
Also in the structure of this comparative example, in order to reduce the wiring resistance per unit area of the global wiring layer, the wiring film thickness T2 of the second wiring layer 2 is larger than the wiring film thickness T1 of the first wiring layer 1 (T1 <T2). In order to reduce the capacitance between wirings in the global wiring layer, the minimum wiring interval in the wiring layer is made equal or larger as the upper layer structure is formed. Further, by making the interval between the respective wiring layers 1, 2, 3, 4 larger than the minimum wiring interval in each of the wiring layers 1, 2, 3, 4, the wiring capacitance caused by the wiring layers is reduced. .
[0060]
However, in this structure, crosstalk noise occurs in the second wiring layer 2 due to capacitive coupling between the first wiring layer 1 and the second wiring layer 2. With this structure, when the signal voltages of the second wiring layer 2 and the third wiring layer 3 which are global wiring layers are lowered, noise is large and it is difficult to transmit signals correctly.
[0061]
FIG. 3 is a diagram for explaining the driving method of the multilayer wiring structure according to the present invention, and is a diagram for explaining the voltage rise of the second wiring layer 2 due to the voltage pulse of the first wiring layer 1. The structure above the 1st wiring layer of FIG. 1 is shown.
[0062]
Here, the first wiring layer 1 and the third wiring layer 3 are formed in a direction orthogonal to the second wiring layer 2 in order to reduce crosstalk as much as possible. The first wiring layer 1 is densely formed with a wiring film thickness T1, a wiring width W1, and a wiring interval S1, and is GND before a certain time, V after a certain time._DDIt is assumed that a step pulse is applied.
[0063]
In FIG. 4, all the wiring in the first wiring layer 1 is laid under the second wiring layer 2 and the amplitude V_DDThe logic circuit operating at_DDIt corresponds to the case where it is driven to become. The third wiring layer 3 is densely formed with a wiring film thickness T3, a wiring width W3, and a wiring interval S3, and each wiring is grounded. The second wiring layer 2 is formed with a wiring film thickness T2, a wiring width W2, and a wiring interval S2, and one wiring is in a floating state, and a voltmeter 14 is connected to one end. Suppose that one of the wirings is grounded.
[0064]
In FIG. 3, first, from 0 V to V is applied to the first wiring layer 1._DDWhen the step pulse is applied, the voltage of the second wiring layer 2 is increased by capacitive coupling by ΔV. Where ΔV / V_DDThe inventor has newly found that the value agrees with the value obtained by the following relational expression.
[0065]
ΔV / V_DD= [{0.0261−0.0945 (T2 / S2)} (H2 / S2) + 0.3657−0.0541 (T2 / S2)] × (H1 / S2)^{− {0.65 + 0.05 (T2 / S2)}}                                            Formula (1)
However, 1 ≦ (H1 / S2) ≦ 3, 0.5 ≦ (T2 / S2) ≦ 3, and 1/4 ≦ (S1 / S2) ≦ 1/2, and W1 ≦ 2 × T1, W3 ≦ 2 × It can be obtained by equation (1) within an error range of ± 20% within the range of T3.
[0066]
Here, considering the case where the second wiring layer 2 and the third wiring layer 3 are formed with the same wiring width, wiring film thickness, and wiring interval, H1 = H2 under the condition of H2 = T2 = S2. In this case, ΔV / V from equation (1)_DD= 0.24, and ΔV = 0.24V in wiring 2 due to capacitive coupling_DDVoltage increase occurs.
[0067]
  Further, when the signal applied to the first wiring layer 1 is a step pulse from VDD to 0 V, the second wiring layer 20.24VDD Voltage drop occurs.
[0068]
Therefore, the voltage amplitude of the second wiring layer 2 is at least 2 × 0.24V_DD= 0.48V_DDIf the voltage of the wiring layer 2 is made to have a low voltage amplitude below this voltage, a malfunction occurs.
[0069]
Therefore, H1 is made larger than H2, and in particular, the signal amplitude of the second wiring layer 2 is set to V₁<V_DDH1> (V_DD/ V₁)^1.5XH2 In this case, from the formula (1), ΔV / V in the range of at least 0.5 ≦ (T2 / S2) ≦ 3 as compared with the condition where H1 = H2 and S2 and T2 are the same._DD≦ 0.24 × (V₁/ V_DD).
[0070]
Therefore, in the present invention, the voltage increase due to capacitive coupling is 0.24V._DDFrom 0.24V₁The crosstalk can be reduced to (V₁/ V_DD) Can be reduced to less than double. In addition, crosstalk (V₁/ V_DDThe suppression to less than double is also true for a general wiring layout in which the wiring width and wiring interval of the first wiring layer 1 are changed.
[0071]
As described above, in the second wiring layer 2 and the third wiring layer 3 which are global wiring layers, the voltage amplitude of the signal wiring with the minimum wiring interval adjacent in the layer is expressed as V.₁By making the following, the crosstalk voltage of the wiring adjacent in the second wiring layer 2 is set to the voltage amplitude of the signal wiring of the minimum wiring interval adjacent in the layer V_DDCompared to₁/ V_DD) Can be reduced to less than double.
[0072]
In these methods, it is not necessary to change the wiring line width, the wiring interval, and the distance between the second wiring layer 2 and the third wiring layer 3 of the second wiring layer 2 and the third wiring layer 3.
[0073]
By using the above in combination, in the present invention, all the crosstalk voltages due to capacitive coupling of the second wiring layer 2 and the third wiring layer 3 are all converted to the second wiring layer 2 and the third wiring layer 3 of the comparative example. Wiring included in V_DDCompared to driving with amplitude, (V₁/ V_DD) Can be reduced to less than double. By this method, the voltage amplitudes of the wirings included in the second wiring layer 2 and the third wiring layer 3 by the intra-chip wirings are compared with (V₁/ V_DD) Can be reduced to less than double.
[0074]
Further, by using the same idea for the upper wiring layer above the third wiring layer 3, the upper wiring layer also increases the voltage amplitude of the wiring (V₁/ V_DD) Can be reduced to less than double.
[0075]
In the configuration of FIG. 1, the voltage amplitude of the third wiring layer 3 is, for example, V_DDAnd the logic voltage amplitude of the second wiring layer 2 is, for example, V_DDLower V₁In this case, the crosstalk voltage from the third wiring layer 3 to the second wiring layer 2 is maintained with the distance between the second wiring layer 2 and the third wiring layer 3 being H2 narrower than H1. Amplitude is ± 0.24V_DDTherefore, the receiver of the second wiring layer 2 malfunctions, and the effect cannot be obtained sufficiently. Therefore, a sufficient effect can be obtained by suppressing the voltage amplitude of the third wiring layer 3 facing the second wiring layer 2.
[0076]
The second wiring layer 2 and the third wiring layer 3 which are global wiring layers and the wiring layers above this are usually V_DDIn many cases, an external input / output terminal that is driven with an amplitude voltage is provided. This V_DDThe crosstalk from the amplitude signal terminal to the low voltage wiring can be reduced, for example, by a wiring structure as shown in FIG.
[0077]
FIG. 5 shows V penetrating through the second wiring layer 2 and the third wiring layer 3._DDIt is an interlayer overhead view of the signal wiring structure of amplitude. The description of the same symbols as those in FIG. 4 is omitted.
[0078]
In the second wiring layer 2 and the third wiring layer 3, V_DDWirings that are driven in amplitude are the wiring 15 and the wiring 16 and are connected to an input circuit and an output circuit of an upper wiring layer not shown in the drawing. These external input circuit and output circuit can be formed by elements arranged very close to each other, and the wiring in the chip can be sufficiently realized by using a local wiring layer.
[0079]
Therefore, the areas of the wiring 15 and the wiring 16 penetrating through the second wiring layer 2 and the third wiring layer 3 may be a minimum area sufficient for forming a contact with the upper wiring as shown in FIG. Therefore, the capacitive coupling to the adjacent wiring in the second wiring layer 2 or the third wiring layer 3 can also be reduced because the cross-sectional areas of the wiring 15 and the wiring 16 are small. As a result, compared with the case where the wiring 15 and the wiring 16 are formed long in parallel in the global wiring layer, the crosstalk can be kept very small in proportion to the wiring cross-sectional area.
[0080]
Further, in FIG. 5, adjacent to the wiring 15 and the wiring 16, for example, GND or V_DDA wiring 17 having a constant potential is formed adjacently to shield the wiring 15 and the wiring 16. It is desirable that the distance between the wiring 17 and the wiring 15 and the wiring 16 in the plane is the minimum wiring interval.
[0081]
For example, the wiring 17 included in the same layer as the wiring 16 causes crosstalk to the low voltage amplitude wiring 18 in the same layer due to capacitive coupling of the wiring 16 when the distance between the wiring 16 and the wiring 18 is constant. It has been experimentally found that the number of wiring lines 17 can be reduced to 1/10 or less, and the crosstalk can be reduced while densely forming the wiring lines.
[0082]
Similarly, the wiring 17 included in the same layer as the wiring 15 reduces crosstalk due to capacitive coupling from the wiring 16 to the low voltage amplitude wiring 18 in the same layer when the distance from the wiring 18 is constant. . In this case, when the distance between the wiring 15 and the wiring 18 is set to be k times larger than the minimum wiring interval S2 of the wiring layer 2, the crosstalk generated in the wiring 18 is (1 / k) when arranged with the minimum wiring interval. It was found that it can be reduced to less than twice.
[0083]
By using the above method, V_DDCrosstalk from the terminal of the amplitude signal to the low voltage wiring can be reduced.
[0084]
In addition, the number of external input / output terminals is 1.9 × N at most in the gate array compared to the number of transistors, where N is the number of transistor gates.^0.5[Book]. Incidentally, the gate array has the largest number of external input / output terminals with respect to the number of gates among the microprocessor, static RAM, dynamic RAM, and gate array. In this case, as compared with the total number of wires in the chip using the transistors up to 3 × N,⁶The number of transistors is 0.07% or less, and the ratio to the total wiring is N as the number of transistors increases.^{− 0.5}Decrease.
[0085]
Here, the wiring area of the global wiring layer according to the bit line shielding method of FIG. 5 increases only at most about four times compared to the wiring area when the bit line shielding is not performed, and the minimum wiring of the second wiring layer 2 The pitch is 2F, 36F²Occupies only a certain area. Therefore, for example, when the wiring pitch is 2 μm, the area increase due to the bit line shield shown in FIG.²× (4-1) times to 100 μm²About 10 for all input / output pins⁶Piece × 0.07% × 100μm²~ 0.07mm²Smaller area, usually 10mm²With the above VLSI circuit chips, the rate of increase in chip area is very small.
[0086]
In addition, V_DDTo reduce crosstalk from the signal terminal of amplitude to the low voltage wiring, V_DDEven when a low voltage signal is transmitted to the second wiring layer 2 and the third wiring layer 3 through the first wiring layer 1 and the wiring layer 4 having the voltage amplitude, the first wiring layer 1 and the wiring layer 3 are also used. For 4, the same arrangement as in FIG. 5 can be used.
[0087]
This low voltage wiring is connected to other V_DDSince it is not necessary to connect to the first wiring layer 1 and the wiring layer 4 having the voltage amplitude, the wiring cross-sectional area is kept small in the first wiring layer 1 and the wiring layer 4 similarly to the wiring 15 and the wiring 16 in FIG. It can be formed in a rectangular shape.
[0088]
Therefore, V in the first wiring layer 1 and the wiring layer 4_DDCapacitive coupling from adjacent wirings of voltage amplitude can also be reduced because the wiring cross-sectional areas of the low-voltage wirings in the first wiring layer 1 and the wiring layer 4 are small. As a result, the crosstalk can be kept very small in proportion to the wiring cross-sectional area as compared with the case where the wiring is formed long in parallel.
[0089]
Next, FIG._DDIt is an example of an amplitude wiring drive circuit. 7 to 12 show examples of a low voltage amplitude circuit for driving the global wiring layer of the present invention.
[0090]
6 to 12, for example, the power supply voltage is V from inverters INV1 to INV11._DDCMOS inverters are shown. For NAND1 to NAND2 and NOR1 to NOR2, for example, the power supply voltage is V_DD1 shows a NAND circuit and a NOR circuit. Here, Cint indicates a wiring capacity, and a portion to which Cint is connected is a wiring, and a symbol corresponding to the wiring layers 1, 2, 3, 4 is attached.
[0091]
In FIG. 6, the output of the CMOS inverter INV1, which is a wiring driver, is connected to one end of the wiring layer 1 or 4 having a Cint capacitance, and the other end of the wiring is connected to the input of the inverter INV2, which is a wiring receiver. Has been. With these, V_INInput voltage is V through wiring layer 1 or wiring layer 4_OUTIs output.
[0092]
In the present invention, V in FIG._DDThe wiring drive circuit may be used for driving the wiring layer 1 and the wiring layer 4 which are local wiring layers, and there is no need to change the CMOS circuit from the wiring drive circuit.
[0093]
Further, the second wiring layer 2 and the third wiring layer 3 which are global wiring layers use, for example, the low voltage amplitude circuit of FIG. FIG. 7 is a so-called static sense amplifier circuit. For example, “VLSI system design circuit and basics of implementation”, written by H. Bakoglu, translated by Kisaburo Nakazawa and Hiroshi Nakamura, published on March 30, 1995, Maruzen Corporation. pp.184-198.
[0094]
In this circuit, the n-type MISFET Qn1 is a wiring driver, and the p-type MISFET Qp1 and the inverters INV3, INV4, and INV5 are wiring receivers.
[0095]
When the n-type MISFET Qn1 is off, the wiring of the wiring layer 2 is charged by the p-type MISFET Qp1, but when it becomes slightly higher than the logic inversion voltage of the inverter INV3, the Qp1 is turned off and the charging stops and the wiring layer The voltage of 2 is V_DDStays at a smaller value. When the n-type MISFET Qn1 is on, the voltage of the wiring layer 2 is clamped to a voltage determined by the channel resistance ratio between the n-type MISFET Qp1 and the p-type MISFET Qn1, and does not drop to 0V.
[0096]
From the above, the voltage amplitude of the second wiring layer 2 is V_DDSmaller V₁The electric power for charging the second wiring layer 2 can be expressed as (V₁/ V_DD)²Can be doubled.
[0097]
Here, this circuit uses V as the power supply voltage._DDThe voltage of the second wiring layer 2 is higher than 0V and V_DDIt can be kept lower. V_DDIn the circuit of FIG. 6 having a signal amplitude of ## EQU1 ## where the threshold value of the n-type MISFET forming the inverter INV2 in the first stage of the wiring receiver is Vthn and the threshold value of the p-type MISFET is Vthp, the input voltage of the inverter INV2 Is less than Vthn and (V_DDIn the range above -Vthp), the n-type MISFET and the p-type MISFET are not turned on, respectively. Therefore, even if the input voltage changes in this voltage range, the output voltage does not change and an output delay occurs with respect to the input signal.
[0098]
Therefore, in FIG. 7, the transistor widths of these Qn1 and Qp1 are adjusted so that the voltage range of the second wiring layer 2 is not less than the threshold value Vthn of the n-type MISFET forming the inverter INV3, and the inverter INV3 is Let Vthp be the threshold value of the p-type MISFET to be formed (V_DD-Vthp) or less, it is possible to reduce the input / output delay due to the dead zone due to the threshold value of the transistor generated in the inverter of FIG. 6, and to operate at higher speed. Actually, 0.4V in the circuit of FIG._DDIs designed to have a voltage amplitude of_INAnd V_OUTAnd investigated the delay time. Transistor threshold is 0.2V_DDAnd the delay time of the inverter with F / O = 1 is τ₀Then V_INTo V_OUT50% delay time is 0.5 × Cint × R + 3 × τ₀It has been found that the speed can be increased in a region where the wiring capacitance Cint is more dominant than the 50% delay time 0.7 × Cint × R when the wiring layer 2 is driven by the CMOS inverter of FIG.
[0099]
Further, when the second wiring layer 2 is driven by the circuit of FIG. 7, the power consumption accompanying the wiring layer charging / discharging can be reduced to 16% of the CMOS inverter of FIG. Further, a single long wiring for transmitting a signal is sufficient as in the case of the circuit of FIG. 6, and there is no increase in the number of wirings in the global wiring layer. Of course, the power supply voltage is V_DDTherefore, a new power supply voltage line is not necessary.
[0100]
In particular, in the receiver shown in FIGS. 7 to 11, the threshold V of the receiver transistor, such as the receiver shown in FIG._thnAnd V_thpThere is no dead band input voltage range due to. Therefore, even if the voltage amplitude of the second wiring layer 2 is reduced by this dead zone, the wiring delay does not increase. Where V_thnAnd V_thpIs 0.15 × V_DDThe above is desirable for reducing the through current in the receiver using the CMOS inverter of FIG. Therefore, without increasing the wiring delay, V₁≦ V_DD-V_thp-V_thn≦ 0.7 × V_DDThe power consumption accompanying wiring charge / discharge can be reduced. This is H₁≧ (V_DD/ V₁)^1.5× H₂≧ 1.7 × H₂It can be realized with the structure.
[0101]
The drive circuit shown in FIG. 8 is an example in which an n-type MISFET Qn2 is used instead of Qp1, and Qn1 and Qn2 are transistors having the same conductivity, so that matching is easily achieved.
[0102]
The drive circuit shown in FIG._DDThe / 2 precharge circuit is a driver for the second wiring layer 2 or the third wiring layer 3 on the left side of the second wiring layer 2 or the third wiring layer 3. The right side of the second wiring layer 2 or the third wiring layer 3 is a receiver for the wiring, and the voltage of the second wiring layer 2 or the third wiring layer 3 is V_DDV around 2_DDOperates with smaller voltage amplitude.
[0103]
Here, Φ1 and Φ2 are two-phase non-overlapping clocks as shown in FIG. 13, and when Φ1 is high, the wiring layer is almost V_DDSignal transmission is performed when Φ2 is high. By doing so, it is possible to reduce the direct current that is present when the transistor Qn1 is in the conductive state in the circuits of FIGS.
[0104]
The circuit shown in FIG. 10 is a sense amplifier with a clock obtained by adding a clock to the static sense amplifier circuit of FIG. Even in this circuit, it is possible to reduce the direct current consumption that is present when the transistor Qn1 is in the conductive state.
[0105]
These circuits shown in FIG. 9 and FIG. 10 require external clock input wirings [Phi] 1 and [Phi] 2. Also, V_INWhen the input HIGH period is long and the wiring power consumption due to the transistor Qn1 in the circuit of FIG. 7 being turned on becomes a problem, for example, a circuit of the complementary type of FIG. May be used.
[0106]
As described above, when the low voltage amplitude circuit shown in FIG. 7 to FIG. 11 is used for driving the global wiring layer, the wiring delay time is shortened, and the long wiring for transmitting a signal uses the driving circuit of FIG. Similarly, one line is sufficient, and there is no increase in the number of wires. In addition, the power supply voltage is V_DDTherefore, a new power supply voltage line is not necessary. Further, the increase in the circuit area is twice or less compared to the case where the drive circuit of FIG. 6 is used for the global wiring layer.
[0107]
Further, by dividing a long wiring into a plurality of pieces as in the drive circuit shown in FIG. 12 and connecting low voltage amplitude circuits from FIGS. 7 to 12 in series, thereby forming a low voltage amplitude repeater, Signal delay can be improved. If wiring capacitance is more problematic than wiring resistance, connect inverters INV10 and INV11 connected in series so that the size gradually increases before the low-voltage amplitude circuit, and form a cascade driver to delay. You can improve your time. This cascade driver can be formed by a very close transistor arrangement, and the global distribution can be formed as a low voltage amplitude circuit without increasing the number of global wiring layers of the low voltage amplitude circuit.
[0108]
The configuration described above has the following characteristics.
[0109]
First, the power consumption can be reduced and the delay time can be improved by the wiring delay without adding the number of wiring layers. Low power consumption means that the wiring voltage amplitude of the global wiring layer is V_DDThis is because the amplitude is V₁, Where Cu is the total capacitance of the global wiring, Cd is the sum of the total capacitance of the local wiring layer, the total junction capacitance of the transistor, and the gate capacitance (Cu × V₁ ²+ Cd × V_DD ²) / (Cu × V_DD ²+ Cd × V_DD ²) Power consumption can be reduced to a ratio of. At this time, as described in detail using the drive circuit of FIG. 7, the wiring delay time is also shortened to a maximum of 71%. Therefore, the circuit skew caused by the wiring delay can be reduced, and a circuit with higher speed and fewer malfunctions can be realized.
[0110]
In addition, the operating voltage of the global wiring layer is set to V_DDSince the voltage can be lower than that of the CMOS inverter, the current density of the global wiring layer can be reduced and reliability problems such as electromigration and interlayer insulation can be alleviated. .
[0111]
Furthermore, electromagnetic noise generated by the global wiring layer can be reduced, and power supply voltage fluctuations due to electromagnetic noise and malfunction of the sense circuit can be prevented. Of course, along with the reduction in power consumption, heat generation due to charge / discharge decreases, improving the reliability due to a decrease in the thermal history of the wiring, reducing the thickness of the power wiring, reducing the ratio of the power wiring, and transistor junction leakage Can be reduced, and higher integration can be realized with higher reliability and lower leakage.
[0112]
In addition, since it is not necessary to add the number of wiring layers, there is no occurrence of defects due to additional layers, such as defective interlayer connection, lower reliability, significant layout change of wiring layers, and no decrease in productivity due to increased manufacturing processes. .
[0113]
By simply replacing the wiring driver and wiring receiver of the low logic voltage amplitude circuit, the conventional circuit design method and tool can be used as they are, and it is not necessary to support multiple power supply voltages and multiple signal amplitudes. In other words, no change is required until the logical design of the conventional circuit design, and even at the layout design level, if the design of FIG. 14 is used, the wiring delay time model can be modified without any significant layout change. Yes, conventional CAD tools can be used.
[0114]
FIG. 14 shows a method for realizing the circuit wiring of this embodiment using a conventional layout design tool as it is. First, as indicated by reference numeral 20, all V and local wiring layers are all distinguished from each other._DDDesign the circuit layout with voltage.
[0115]
First, a global wiring layer is selected, and wirings assigned to the global wiring layer are determined. Next, a CAD tool is used to extract wiring belonging to the global wiring layer. Here, the wiring driver and the receiver used in the global wiring layer can be formed by adjacent elements, respectively, and the connection in the wiring driver and the receiver can be realized using only the local wiring layer.
[0116]
In addition, when the local wiring layer has two or more layers, the increase in area of the low voltage amplitude wiring driver and receiver from the driver and receiver by the CMOS inverter is less than twice.²This can be achieved with:
[0117]
In addition, in a situation where multilayer wiring is formed in which the chip operating speed is limited by wiring delay, the minimum area determined by the minimum dimensions of the transistor is smaller than the chip area determined by the wiring, and there is a margin for transistor placement become. Therefore, when the global wiring layer and the local wiring layer extracted by reference numeral 20 are allocated as the optimal arrangement, the layout of the local wiring layer near the low voltage driver is not changed without changing the allocation of the global wiring layer and the local wiring layer. By correcting this, the wiring delay can be increased.
[0118]
Next, if the dummy circuit arranged at reference numeral 22 is replaced with a wiring driver and a wiring receiver at reference numeral 24, the layout is completed.
[0119]
Further, in the static sense amplifier circuit shown in FIG. 7 and FIG. 8, the circuit area is 0.8 times or less when the wiring capacity is 100 times or more of the inverter capacity of the fan-out 1 compared to the CMOS inverter circuit shown in FIG. And become smaller. In this case, the wiring layout design is performed using the wiring driver and the wiring receiver formed by the CMOS circuit of FIG. 6, and the wiring driver and the receiver connected to the global wiring layer are changed in the layout of other wiring structures. This can be replaced with this static sense amplifier circuit without the need for automatic design. Of course, if the optimization shown in FIG. 14 is performed, the circuit area can be reduced as compared with the case where a wiring driver and a wiring receiver formed of a CMOS circuit are used. In this case, the lithography conditions and mask of the global wiring layer can be used as they are, and if a conventional structural process is established, high speed and low power consumption can be realized at a very low cost.
[0120]
Further, in the present invention, the change in the stacking direction of the wiring layers is only the interlayer film thickness between the global wiring layer and the local wiring layer as compared with the conventional method, and there is no increase in the number of manufacturing steps. In addition, between the global wiring layer and the local wiring layer, the conventional wiring line width, wiring interval, and interlayer film thickness can be kept unchanged, and all crosstalk voltages generated from adjacent wirings in the vertical and horizontal directions (V₁/ V_DD) Can be scaled twice. Therefore, it is possible to use a wiring arrangement that has already undergone circuit verification and process verification in a circuit having a conventional structure.
[0121]
Further, the wiring layer height is only the height of the interlayer film between the first wiring layer 1 and the second wiring layer 2, and the other wiring layers do not need to increase the interlayer film. The occurrence of defects due to film stress accompanying the increase in interlayer film can be reduced as compared with the case where the film thickness of other wiring layers is also increased.
[0122]
Next, the low voltage amplitude circuit and V in the horizontal direction_DDWhen the amplitude circuit is provided, it is necessary to suppress the logical voltage amplitude of the adjacent global wiring layer and local wiring layer of the multilayer wiring of the low voltage amplitude circuit. For example, a constant voltage layer such as a power supply layer is inserted. Although it is necessary, this method is not necessary, and the effective wiring area in the chip can be used more widely.
[0123]
(Embodiment 2)
FIG. 15 is a stacked cross-sectional view of a wiring structure including a semiconductor substrate region of a semiconductor device according to Embodiment 2 of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.
[0124]
In the present embodiment, the fourth wiring layer 12 is further formed on the third wiring layer 3 in the first embodiment, and the distance H1 between the first wiring layer 1 and the second wiring layer 2 is set to the third. The distance H2 between the wiring layer 3 and the fourth wiring layer 12 is larger.
[0125]
In FIG. 15, the portion below the second wiring layer 2 is the same as the structure described in the first embodiment, and is omitted.
[0126]
An insulating film 13 is deposited over the entire surface of the second wiring layer 2 so as to have a thickness larger than H1, and for example, a contact 6 between wiring layers made of W, Ru, Ti, TiN, Cu, Al, or AlCu. Is formed. The diameter of the wiring contact 6 is equal to or larger than the diameter of the wiring contact 5.
[0127]
Furthermore, the wiring contact 6 is formed with a third wiring layer 3 made of, for example, W, Cu, Al, or AlCu. The film thickness of the third wiring layer 3 is larger than the film thickness of the first wiring layer 1, and the wiring resistance per unit area on the laminated surface is lowered. Further, the wiring interval S3 in the third wiring layer 3 is formed to be larger than the wiring interval S1 in the first wiring layer 1, and the capacitance between the wirings included in the third wiring layer 3 is suppressed. The product of the wiring resistance and the wiring capacitance is reduced and used for wiring between circuit blocks farther than the first wiring layer 1. The wiring length of the third wiring layer 3 is larger than the wiring length of the first wiring layer 1. become longer.
[0128]
Further, the minimum line width W3 of the third wiring layer 3 is made larger than the wiring width W1 of the first wiring layer 1 to reduce the wiring resistance. The second wiring layer 2 and the third wiring layer 3 are formed so as to extend in the orthogonal direction and have the same film thickness and line width, thereby improving the integration density of wiring of random blocks. Desirable to form.
[0129]
Furthermore, the second wiring layer 2 and the third wiring layer 3 are formed so as to extend in a direction orthogonal to each other than in a parallel direction, thereby reducing crosstalk between the wiring layers. Is desirable.
[0130]
Further, an insulating film 13 is deposited on the entire surface of the third wiring layer 3 at a height of H2. For example, although not shown, the insulating film 13 is made of W, Ru, Ti, TiN, TaN, Cu, Al, or AlCu. A wiring contact is formed between the wiring layers. The diameter of the wiring contact is equal to or larger than the diameter of the wiring contact 6.
[0131]
Furthermore, a fourth wiring layer 12 made of, for example, W, Cu, Al, or AlCu is formed on the wiring contact. The film thickness of the fourth wiring layer 12 is larger than the film thickness of the first wiring layer 1, and the wiring resistance per unit area on the laminated surface is lowered. Furthermore, the wiring interval S4 in the fourth wiring layer 12 is formed to be larger than the wiring interval S1 in the first wiring layer 1, and the capacitance between the wirings included in the fourth wiring layer 12 is suppressed. The product of the wiring resistance and the wiring capacitance is reduced and used for wiring between circuit blocks farther than the first wiring layer 1, and the wiring length of the first wiring layer 12 is longer than the wiring length of the wiring 1.
[0132]
Further, the minimum line width W12 of the fourth wiring layer 12 is larger than the minimum wiring width W1 of the first wiring layer 1, and the wiring resistance is reduced. The fourth wiring layer 12 and the third wiring layer 3 are preferably formed so as to extend in a direction orthogonal to each other than in a parallel direction, in order to reduce crosstalk between the wiring layers. .
[0133]
Here, in this embodiment, H2 which is one of the wiring layer intervals of the global wiring is smaller than the distance H1 between the local wiring layer and the global wiring layer. Here, in particular, the signal amplitudes of the second wiring layer 2, the third wiring layer 3, and the wiring layer 4 are expressed as V.₁H1> (V_DD/ V₁)^1.5× H2. Even in such a structure, the crosstalk from the first wiring layer 1 (V₁/ V_DD), The logical voltage amplitude of the global wiring layer can be reduced to V₁Can be reduced. Of course, although not shown in FIG. 15, H1> (V, where H2 is the minimum value of the distance between layers adjacent to the fourth wiring layer 12 in the stacking direction._DD/ V₁)^1.5By satisfying × H2, all crosstalk due to capacitive coupling in the local wiring layer is reduced (V₁/ V_DD) Times or less, and the logical voltage amplitude of the global wiring layer is V₁Can be reduced.
[0134]
In the present embodiment, since the distance between the second wiring layer 2 and the third wiring layer 3 is greater than that in the first embodiment, the second wiring layer 2 and the third wiring layer 3 are more The crosstalk can be reduced.
[0135]
In the present invention, the element isolation film and the insulating film forming method itself are other methods for converting silicon into a silicon oxide film or a silicon nitride film, for example, a method of injecting oxygen ions into deposited silicon, or oxidizing deposited silicon. You may use the method to do.
[0136]
The gate insulating film and the interlayer insulating film 13 are made of SiN film, amorphous carbon film, TiO₂Organic insulation such as aluminum oxide, alumina, tantalum oxide film, strontium titanate, barium titanate, lead zirconium titanate, HSQ (hydrogen silsesquioxane), MSQ (methyl silsesquioxane), PAE (poly arylene ether), polyimide, etc. You may use a film | membrane and those laminated films.
[0137]
In addition, although a p-type Si substrate is used as the semiconductor substrate 10, a single crystal semiconductor substrate containing silicon such as an n-type Si substrate, an SOI silicon layer of an SOI substrate, or a SiGe mixed crystal or SiGeC mixed crystal may be used instead. .
[0138]
The gate electrode 8 may be p-type polycrystalline Si or SiGe mixed crystal, or a metal such as Al, TiN, TaN, Al, or Cu, or a laminated structure thereof.
[0139]
Moreover, although the example which formed the trench element isolation | separation 11 was shown, mesa etching and LOCOS element isolation | separation may be sufficient instead of trench element isolation | separation, for example.
[0140]
In addition, various modifications can be made without departing from the scope of the present invention.
[0141]
【The invention's effect】
The present invention can provide a semiconductor device that reduces wiring delay and achieves both low power consumption and high speed without significantly changing the circuit layout and wiring structure of a CMOS logic circuit.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the invention.
FIG. 2 is a cross-sectional view of a semiconductor device of a comparative example.
FIG. 3 is a cross-sectional view for explaining the method for driving the semiconductor device according to the first embodiment of the invention.
FIG. 4 is a perspective view of the semiconductor device according to the first embodiment of the present invention.
FIG. 5 is a perspective view of the semiconductor device according to the first embodiment of the present invention.
FIG. 6 is a drive circuit diagram for driving a local wiring layer of the present invention.
FIG. 7 is a low voltage driving circuit for driving the global wiring layer of the present invention at a low voltage.
FIG. 8 is a low voltage driving circuit for driving the global wiring layer of the present invention at a low voltage.
FIG. 9 is a low voltage driving circuit for driving the global wiring layer of the present invention at a low voltage.
FIG. 10 is a low voltage driving circuit for driving the global wiring layer of the present invention at a low voltage.
FIG. 11 is a low voltage driving circuit for driving the global wiring layer of the present invention at a low voltage.
FIG. 12 is a low voltage driving circuit for driving the global wiring layer of the present invention at a low voltage.
FIG. 13 is a graph showing the relationship of signal voltages for driving the semiconductor device of the present invention.
FIG. 14 is a flowchart for explaining a method for manufacturing a semiconductor device of the present invention;
FIG. 15 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention.
[Explanation of symbols]
1 ... 1st wiring layer
2 ... Second wiring layer
3 ... Third wiring layer
4 ... Wiring layer
5. Wiring contact
6. Wiring contact
7. Wiring contact
8 ... Gate electrode
9 ... Source / Drain
10 ... Semiconductor substrate
11: Element isolation region
12 ... Fourth wiring layer

Claims (18)

A first conductivity type MISFET and a second conductivity type MISFET formed on a semiconductor substrate, and a first insulating film formed on the semiconductor substrate via a first insulating film, and the first conductivity type MISFET and the second conductivity type A plurality of first wiring layers electrically connected to the MISFET of the type via a first wiring contact made of W, Ru, TaN, Ti, TiN, Cu, Al or AlCu, and the first of these a second wiring layer of the plurality of formed through the second insulating film on the wiring layer, a plurality of third formed via a third insulating film to those of the second wiring layer And a wiring layer of
The first wiring layer, the second wiring layer, and the third wiring layer are laminated in this order without any other wiring layer interposed,
The wiring thickness of the first wiring layer is smaller than the wiring thickness of the second wiring layer and the wiring thickness of the third wiring layer, and the first wiring layer and the second wiring layer Is formed to be equal to or greater than 1.7 times the distance between the second wiring layer and the third wiring layer ,
The semiconductor device , wherein a voltage amplitude of the second wiring layer or the third wiring layer is smaller than a voltage amplitude of a plurality of wirings of the first wiring layer . Said 1 The wiring width of the wiring layer of the first 2 The wiring width of the wiring layer or the first Three The semiconductor device according to claim 1, wherein the semiconductor device is smaller than a wiring width of the wiring layer. Said 1 Wiring layer wiring and the first 2 The wiring in the wiring layer is twisted ( (Crossover layout) The semiconductor device according to claim 1, wherein: Said 1 The voltage amplitude of the wiring layer VDD , The voltage amplitude of the second wiring layer V1 The first 1 Wiring layer and said first 2 The distance between the wiring layers is H1, 2 Wiring layer and the first Three When the distance between the wiring layers is H2, H1 ≧ ( VDD / V1 ) ^1.5 × H2 4. The semiconductor device according to claim 1, wherein the semiconductor device is configured as follows. An interval between adjacent wires in the first wiring layer is smaller than an interval between adjacent wires in the second wiring layer and an interval between adjacent wires in the third wiring layer. The semiconductor device according to claim 1. Said 1 The voltage amplitude of the wiring layer VDD , The voltage amplitude of the plurality of wirings of the second wiring layer V1 Then, V1 ≦ 0.48 × VDD The semiconductor device according to claim 1, wherein: A first conductivity type MISFET and a second conductivity type MISFET formed on a semiconductor substrate, and a first insulating film formed on the semiconductor substrate via a first insulating film, and the first conductivity type MISFET and the second conductivity type A plurality of first wiring layers electrically connected to the MISFET of the type via a first wiring contact made of W, Ru, TaN, Ti, TiN, Cu, Al or AlCu, and the first of these a second wiring layer of the plurality of formed through the second insulating film on the wiring layer, a plurality of third formed via a third insulating film to those of the second wiring layer And a wiring layer of
The first wiring layer, the second wiring layer, and the third wiring layer are laminated in this order without any other wiring layer interposed,
A distance between the first wiring layer and the second wiring layer is equal to or greater than 1.7 times a distance between the second wiring layer and the third wiring layer;
At least one of the wirings included in the first wiring layer, the second wiring layer, and the third wiring layer includes copper as a main component,
The semiconductor device , wherein a voltage amplitude of the second wiring layer or the third wiring layer is smaller than a voltage amplitude of a plurality of wirings of the first wiring layer . Said 1 The wiring width of the wiring layer of the first 2 The wiring width of the wiring layer or the first Three The semiconductor device according to claim 7, wherein the semiconductor device is smaller than a wiring width of the wiring layer. Said 1 Wiring layer wiring and the first 2 The wiring in the wiring layer is twisted ( (Crossover layout) The semiconductor device according to claim 7, wherein the semiconductor device has a relationship of Said 1 The voltage amplitude of the wiring layer VDD , The voltage amplitude of the second wiring layer V1 The first 1 Wiring layer and said first 2 The distance between the wiring layers is H1, 2 Wiring layer and the first Three When the distance between the wiring layers is H2, H1 ≧ ( VDD / V1 ) ^1.5 × H2 The semiconductor device according to claim 7, wherein the semiconductor device is configured as follows. An interval between adjacent wires in the first wiring layer is smaller than an interval between adjacent wires in the second wiring layer and an interval between adjacent wires in the third wiring layer. The semiconductor device according to claim 7. Said 1 The voltage amplitude of the wiring layer VDD , The voltage amplitude of the plurality of wirings of the second wiring layer V1 Then, V1 ≦ 0.48 × VDD The semiconductor device according to claim 7, wherein: A first conductivity type MISFET and a second conductivity type MISFET formed on a semiconductor substrate, and a first insulating film formed on the semiconductor substrate via a first insulating film, and the first conductivity type MISFET and the second conductivity type A plurality of first wiring layers electrically connected to a MISFET of a type via a first wiring contact made of W, Ru, TaN, Ti, TiN, Cu, Al or AlCu , and the first wiring a second wiring layer of the plurality of formed through the second insulating film on the layer, the third wire of said second plurality of formed through the third insulating film on the wiring layer comprising a layer, a fourth wiring layer of the third plurality of formed through the fourth insulating film on the wiring layer,
The first wiring layer and the second wiring layer are laminated in this order without any other wiring layer,
The third wiring layer and the fourth wiring layer are laminated in this order without any other wiring layer interposed,
The wiring thickness of the first wiring layer is smaller than the wiring thickness of the second wiring layer, the wiring thickness of the third wiring layer, or the wiring thickness of the fourth wiring layer. distance 1 between the wiring layer and the second wiring layer is much larger than or equal to 1.7 times the distance between the third wiring layer and the fourth wiring layer,
The third voltage amplitude of the wiring layer or the fourth wiring layer, wherein a first small Ikoto than the voltage amplitude of the plurality of wirings of the wiring layers. Said 1 The voltage amplitude of the wiring layer VDD , The voltage amplitude of the third wiring layer V2 Then, the above 1 Wiring layer and the first 2 The relationship between the distance H1 between the wiring layer and the distance H3 between the third wiring layer and the fourth wiring layer is as follows: H1 ≧ ( VDD / V2 ) ^1.5 × H 3. The configuration according to claim 1, wherein Three A semiconductor device according to 1. The first wiring layer, a second wiring layer, according to claim 1 3 or 1 4 at least one of the wirings included in the third wiring layer and the fourth wiring layer of which comprises copper as a main component The semiconductor device according to any one of the above . Wherein the first wiring layer of the wiring and the second wiring layer of the wiring, the semiconductor device according to any one of claims 1 3 to 15, characterized in that a relation of twisting (Crossover layout). Wiring width of said first wiring layer, according to any one of claims 1 3 to 15, wherein less than the wiring width of the second wiring width of the wiring layer and the third wiring layer Semiconductor device. An interval between adjacent wires in the first wiring layer is smaller than an interval between adjacent wires in the second wiring layer and an interval between adjacent wires in the third wiring layer. the semiconductor device according to any one of claims 1 3 to 15.

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