JP4058231B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor manufacturing apparatus and a semiconductor manufacturing process, and more particularly to a heat treatment apparatus and a heat treatment method for crystallizing a ferroelectric film or improving contact characteristics of a contact portion, and a method for manufacturing a semiconductor device. is there.
[0002]
[Prior art]
In recent years, a ferroelectric memory (FerroelectricRAM) has attracted attention. This is because it has a response speed substantially equivalent to that of a DRAM and has a feature of non-volatility in which memory is not erased. The feature is attracting expectations as it can be used in system LSIs that are mixed with logic devices as well as general-purpose memories.
FIG. 16 shows a cross section of the ferroelectric memory element. As is apparent from the figure, transistors, ferroelectric capacitors, and wirings are formed in order from the bottom. In this ferroelectric memory element, the lower electrode 101 of the capacitor also serves as a plate line, and the upper electrode 103 is connected to the bit line with the ferroelectric film 102 interposed therebetween. As a matter of course, in the manufacturing process, a transistor is first formed, and then a ferroelectric capacitor is formed. Then, the connection hole is opened to form an Al—Cu wiring. Tungsten (W) is used for the connection wiring in the connection hole.
[0003]
One difficulty in manufacturing a ferroelectric memory is that the ferroelectric is susceptible to process damage. When dry etching or sputtering for forming a multilayer wiring is performed, it is affected by charged particles in the plasma. Further, since these processes are performed under reduced pressure, lead zirconate titanate PZT (Pb (Ti_x・ Zr_1-x) O_Three) And strontium bismuth tantalate SBT (Sr₂BiTaO₉) And the like, and oxygen is desorbed into the ferroelectric material, and the ferroelectricity is remarkably impaired.
As one contrivance for avoiding such process damage in the multilayer wiring forming process, for example, Japanese Patent Laid-Open No. 11-317500 discloses a method of forming a multilayer wiring first and forming a ferroelectric capacitor thereon. Has been proposed. Since the multilayer wiring is formed first and the ferroelectric capacitor is formed thereon, it is natural that the ferroelectric is not subjected to process damage in the wiring forming process.
The problem with this process is that the crystallization temperature of PZT and SBT, which are ferroelectric materials, is higher than the temperature that the aluminum wiring can withstand (450 ° C.). The crystallization temperature of PZT is at least 550 ° C., while SBT requires at least 650 ° C. When heated to such a temperature, problems such as melting of aluminum and disconnection of wiring occur.
[0004]
In order to avoid such a problem, for example, a process of forming by CVD (Chemical Vapor Deposition) with a heat treatment temperature of about 450 ° C. has been studied, but a high-quality ferroelectric performance has not been realized at a low temperature. In order to obtain sufficient performance as a ferroelectric, it is necessary to crystallize it sufficiently at a high temperature.
If the heating time is very short, even if the temperature is high, the aluminum will not change in quality and melt. For example, in the case of 500 ° C., aluminum does not change within a few seconds. Therefore, RTP (Rapid Thermal Process) can be one means, but when it is heated to 650 ° C. with the current RTP, for example, since it takes a long time to reach 450 ° C. or more, the aluminum is altered. . Thus, at present, a solution cannot be found between crystallization requiring high temperature and a process at a temperature not exceeding the temperature at which aluminum does not change.
[0005]
In addition, the problem of depletion of the gate electrode is becoming apparent as the gate insulating film is made thinner in order to improve the performance of transistors at present. Since the parasitic capacitance increases due to the presence of the gate electrode depletion layer, an effective oxide film thickness increases even if a very thin gate insulating film is formed. In order to solve this, it is extremely effective to use a metal gate electrode or a high dielectric constant gate insulating film. However, one of the problems faced by metal gates and high dielectric films is the low temperature of the contact process. Usually, since a natural oxide film exists on the surface of the Si substrate, it is difficult to make a contact with the metal as a barrier layer. In recent years, a method for forming a contact portion of a semiconductor device is to deposit a metal conductive film as an electrode or an underlayer of the electrode in a contact hole patterned and opened in an interlayer insulating film, and then in an infrared heating furnace at 550 ° C. for 1 hour. The above heat treatment has been performed. The purpose of this heat treatment is to reduce the natural oxide film at the interface between the electrode and the semiconductor substrate to form a low resistance ohmic contact.
[0006]
However, conventional heat treatment conditions have a large thermal budget, and Al, which is a metal with low resistivity, has a low melting point.₂O_FiveSince the gate leakage current increases with crystallization, it is not sufficient for use as a gate electrode or a gate insulating film, respectively. In order to achieve higher performance of device characteristics, it is necessary to use a low dielectric constant material for the interlayer insulating film. However, in the conventional thermal process, the mechanical strength decreases or the moisture absorption decreases as the density decreases. Increase in the characteristics, making it difficult to apply to transistors. However, it has been found that when the heat treatment temperature for forming the contact portion is lowered to 500 ° C. or less, both the contact resistance and the variation in the semiconductor substrate surface increase. This is because the natural oxide film on the silicon substrate surface cannot be sufficiently reduced by the heat treatment at 500 ° C. or lower.
[0007]
[Problems to be solved by the invention]
As described above, the problem of depletion of the gate electrode has become apparent as the gate insulating film is made thinner in order to improve the performance of transistors at present. And there was a problem that a contact part was formed with the above-mentioned low thermal budget. Further, the method of forming a ferroelectric capacitor on the multilayer wiring can avoid damage to the multilayer wiring, but there is a limitation that the ferroelectric must be crystallized at a temperature at which aluminum does not change as described above.
The present invention has been made under such circumstances, such as forming a high-quality ferroelectric film at a low temperature of about 400 ° C., forming a contact portion having a high contact property at a low temperature, and rapidly forming a silicide at a low temperature. A heat treatment method for performing formation and the like and a method for manufacturing a semiconductor device using the heat treatment method are provided.
[0008]
[Means for Solving the Problems]
The present invention includes two heating sources having different heating times, for example, at least two kinds of lamps when the sample is heat-treated. First, the first lamp is turned on to heat the sample, and the constant temperature is set. The second lamp is turned on when the temperature reaches the point, and the temperature of the sample is further increased to reach a desired temperature.
In the case of conventional RTP, heating is performed with a single lamp to a desired temperature. For example, when the heat treatment temperature is 700 ° C., heating is performed up to 700 ° C. with one kind of lamp. Assuming that the temperature is raised at 50 ° C./second, which is the standard RTP performance, it takes 14 seconds to reach 700 ° C., and even if the temperature is lowered immediately after setting the processing time to zero, it takes more than 20 seconds to lower the temperature. The heat treatment time exceeds 30 seconds. When a sample is a semiconductor substrate, an aluminum wiring is formed thereon, and a ferroelectric film formed thereon via an interlayer insulating film is heat-treated by crystallization, 450 ° C. or more, which is a dangerous temperature for aluminum The time for heating to 10 seconds or more will lead to dissolution of the aluminum wiring. Aluminum does not deteriorate for 1 hour even if heating is continued at 450 ° C. At 500 ° C., heating can be continued for about 10 to 15 seconds. At 550 ° C., heating can be continued for about 5 to 6 seconds.
[0009]
Furthermore, at 600 ° C., the material changes in about 1 to 2 seconds. Aluminum melts at 660 ° C. However, even if the temperature is lower than the melting temperature, if the heating time exceeds the above-mentioned range, the quality is changed. Such alteration refers to a state in which aluminum grains in aluminum wiring grow and hillocks occur.
The reason why it is necessary to perform preheating using the first lamp is as follows. In other words, the heat energy applied by the second lamp is limited to some extent. If the sample surface is heated only with a flash lamp having a very short irradiation time, in some cases, a large amount of heat energy may be required. In such a case, even if the ferroelectric can be crystallized as intended, there is a problem that the applied energy is conducted to the lower layer and the temperature of aluminum rises due to the large amount of total energy. The thermal energy input by the second lamp must be adjusted so that only the ferroelectric is heated and heated to the extent necessary for crystallization. Therefore, preheating to a certain extent makes sense.
[0010]
FIG. 10 is a characteristic diagram showing the lamp energy and the energy dependence of the irradiated lamp by the temperature by the heat treatment of the ferroelectric film. As shown in the figure, the ferroelectric film starts to crystallize at a predetermined temperature and decomposes at a higher temperature T. And the required energy corresponding to each is obtained from the energy curve shown in the figure. The energy required for crystallization is between the energy widths d. FIG. 11 is a characteristic diagram showing the relationship between the crystallization temperature and the heat treatment time when carrying out the present invention. In the present invention, the ferroelectric film is preheated to a predetermined temperature (T1 or T2) with the first lamp, and then the second lamp that can be heated in a short time, for example, 1000 The temperature is raised to the crystallization temperature (Tc) in a short time of about 1 second. The amount of energy provided by the second lamp depends on the preheating temperature. When it is desired to reduce the energy amount of the second lamp (for example, E2), it is preferable to increase the preheating temperature (for example, T2) and shorten the preheating time (for example, t2). When a flash lamp is used as the second lamp, the amount of energy is 27 joules (J) / cm.²If set as follows, the aluminum wiring formed in the lower layer of the ferroelectric film is not melted and broken. For example, when the PZT ferroelectric film is crystallized, if the preheating temperature is set to 400 ° C., the energy of the flash lamp is 10 J / cm.²Crystallization is complete.
[0011]
When preheating is set to 550 ° C, the energy of the flash lamp is 7-8 J / cm.²Crystallize with. Thus, when the preheating temperature is high, the preheating temperature of the first lamp can be set to 1 second or less.
It is also possible to embed a heater in the sample stage without using a lamp and perform preheating using this heater. However, in this case, the preheating time before and after the original crystallization time is several tens of seconds due to the sample being placed on the heated heater. This method is also possible if the preheating temperature is a temperature that does not cause a problem for aluminum. However, depending on the amount of thermal energy applied by the second lamp, it may be necessary to perform preheating at about 500 ° C. In that case, considering the alteration of aluminum, the preheating time must be reduced to seconds. Therefore, it is necessary to perform preheating with a lamp. The method of preheating with a lamp has a wide range of applicability that it can handle various cases.
[0012]
  In addition, the present invention is characterized in that a first heating source and a second heating source having different emission wavelength distributions and irradiation times are combined for the purpose of reducing the thermal budget of the contact process. The contact resistance between the wiring or electrode and the semiconductor substrate or conductor film is reacted at high speed, thereby realizing a reduction in contact resistance.
  In addition, the silicide is formed by combining the first heating source and the second heating source having different emission wavelength distributions and irradiation times. Since silicide can be formed rapidly at low temperature, it becomes easy to apply new materials such as metal gates with low heat resistance, high dielectric constant gate insulating films, and low dielectric constant interlayer insulating films to transistors. High performance can be realized.
[0015]
  A method for manufacturing a semiconductor device of the present invention includes:Forming an insulating film on the semiconductor substrate, forming a contact hole in the insulating film to expose the first silicide film having the first metal formed on the semiconductor substrate; and exposing the insulating film from the contact hole. Depositing a second metal connected to the first silicide film to form a contact portion, and heat-treating the semiconductor substrate to form a second silicide film having the second metal. A step of improving the contact property of the contact portion by forming on the first silicide film having a metal, and in the step of heat-treating the semiconductor substrate, two heating sources having different emission wavelength distributions and irradiation times are provided. When a halogen lamp as a first heating source is used and a flash lamp as a second heating source is shorter than the irradiation time of the first heating source during the irradiation. And wherein the irradiationis doing.The halogen lamp is turned off after the flash lamp is turned off.You may do it.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, the heat treatment apparatus of the present invention will be described with reference to a schematic sectional view shown in FIG.
This heat treatment apparatus has a sample chamber 1 made of aluminum. Inside the sample chamber 1, a sample stage 2 on which a sample is placed, a gas introduction port 3 for introducing gas, an exhaust port 4 for exhausting gas, and light are introduced. An upper quartz window 5 is provided, a rod-shaped lamp (first lamp) 6 and a flash lamp (second lamp) 7 are used for preheating the sample. Sixteen rod lamps 6 of 3 kW tungsten halogen lamps are installed under the sample 8 and heat the sample 8 from below. On the other hand, the flash lamps 7 are similarly rod-shaped lamps, and 15 lamps are installed on the sample 8 to heat the sample 8 from above. Both lamps are connected to dedicated power sources 9 and 10 respectively. The lamp lighting timing, lighting time, and flash lamp lighting frequency are configured to be controlled by a microcomputer.
It is not essential that the two types of lamps are rod-shaped lamps, and a similar effect can be expected even in a lamp type in which two external terminals are provided in one direction, which is called single-ended in the field of lamps. it can.
[0017]
Next, a first embodiment will be described with reference to FIGS.
FIG. 1 is a manufacturing process cross-sectional view illustrating a method for forming a contact portion between a semiconductor substrate and a wiring. First, as shown in FIG. 1A, a 200 nm SiO 2 film is formed on a single crystal silicon substrate 41 by a CVD (Chemical Vapor Deposition) method.₂A film 42 is deposited. Next, as illustrated in FIG.₂The film 42 is patterned to open 0.3 μm × 0.3 μm contact holes 43. Next, SiO₂Using the film 42 as a mask, boron (B) is accelerated to the silicon semiconductor substrate 41 with an acceleration energy of 10 keV and a dose of 5 × 10.¹⁵cm^-2Ion implantation. As a result, an ion implantation layer 44 is formed as shown in FIG. Here, not only the p-type layer forming impurities but also an n-type conductive layer by ion implantation of P, As, etc. may be formed on the surface of the silicon semiconductor substrate 41. Thereafter, heat treatment is performed at 1000 ° C. for 10 seconds in a nitrogen atmosphere of an infrared lamp heating furnace (RTA). As a result, as shown in FIG. 1D, the crystal implantation of the ion implantation layer 44 is performed and the impurity is activated, so that the ion implantation layer 44 has a p-type impurity used for the source / drain region and the like. A diffusion region 47 is formed. Next, a metal film 45 having a thickness of 30 nm or less is deposited on the silicon semiconductor substrate 41 including the impurity diffusion region 47. The metal film 45 is preferably a metal that can reduce the natural oxide film on the silicon semiconductor substrate, for example, Ti.
[0018]
Other suitable metals include IIIa, IVa and Va refractory metals. Thereafter, the silicon semiconductor substrate 1 is heated to 400 ° C. in an infrared heating furnace in a nitrogen atmosphere, and the energy density is 10 J / cm during the heating.^-2The Xe flash lamp having a pulse width of 1 msec is irradiated with one pulse. Thereby, an ohmic contact between the metal film 5 and the underlying silicon semiconductor substrate 41 was formed. Next, as shown in FIG. 1E, a metal film 46 having a low resistivity, for example, Al, is deposited to a thickness of about 400 nm, and then patterned in accordance with the contact hole 43 to form an electrode 48.
Note that the heat treatment condition of the infrared heating furnace in the contact portion formation of the semiconductor device according to the present invention is set so as not to be treated for a long time at a temperature of 500 ° C. or higher.
In the sample S1 of this example formed by the above-described method, the contact resistance between the Al electrode and the impurity diffusion layer was measured and found to be 1.3 × 10.^-7Ωcm²Met.
[0019]
In order to investigate the effect of reducing the contact resistance in the example, only the substrate heating at 400 ° C. is performed without performing the flash lamp irradiation, and a sample S2 having the same structure as that shown in FIG. When the contact resistance of the sample S2 of the comparative example was measured, it was 5.3 × 10.^-FourΩcm²Met.
Further, when the contact resistance of the sample S3 having the same structure as that shown in FIG. 1 (e) manufactured at 550 ° C. for 90 minutes under the heat treatment condition of only the conventional infrared heating furnace was measured, it was 2.5 × 10.^-7Ωcm²Met.
From the above results, it can be seen that the contact resistance of the sample S1 of the example is significantly lower than that of the comparative sample S2, and is lower than that of the sample S3 of the conventional example.
[0020]
Next, in the sample S1 of the example, the sample S2 of the comparative example, and the sample S3 of the conventional example, the element diffusion behavior and the state of reaction at the contact portion between the metal wiring and the silicon semiconductor substrate are examined by Auger spectroscopy. The result is shown in FIG. FIG. 2 is a composition diagram illustrating the effect of the flash lamp in the reaction mode of the contact portion of the present invention, comparative example, and conventional semiconductor device, where the vertical axis represents the elemental composition ratio (atom%), and the horizontal axis represents Ar ions. It represents the sputtering time (minutes). That is, the horizontal axis corresponds to the depth direction. 2A is an example sample S1, FIG. 2B is a comparative sample S2, and FIG. 2C is a conventional sample S3. Here, as a method for further reducing the contact resistance, the conductor film CoSi is formed on the surface of the silicon semiconductor substrate.₂Layer, the metal film Ti and CoSi₂The mode of reaction with the layer is shown.
[0021]
As shown in FIG. 2, in the sample S2 of the comparative example, Ti / CoSi₂Oxygen is detected at the interface and CoSi₂Insulating natural oxide film (SiO₂, CoO) is present. On the other hand, in the example sample S1 and the conventional example sample S3, CoSi₂It can be seen that the natural oxide film is not detected and is reduced by the metal film Ti. Further, it was found that interdiffusion between Ti and the underlying silicon semiconductor substrate occurred, and a Ti silicide layer was formed. Incidentally, in the comparative sample S2, the formation of the Ti silicide layer could not be confirmed even when the heat treatment time was continued for 90 minutes or more.
From the above results, it is considered that the reduction reaction of the natural oxide film existing on the surface of the silicon semiconductor substrate and the formation of the silicide layer by the metal film hold the key to forming the low resistance contact. It is considered that the contact resistance could not be lowered because the low-temperature heat treatment could not reduce the native oxide film on the surface of the silicon semiconductor substrate because Ti as a metal film could not be reduced and the formation of the Ti silicide layer was suppressed. The effect of the Xe flash lamp in this example is that, by using light energy in addition to heat, energy that could not be reached in an infrared heating furnace could be obtained in a very short time. The high-speed reaction with the semiconductor substrate is possible, and the contact resistance can be reduced with a low thermal budget.
[0022]
The present invention is not limited to the above embodiments. The two heating sources for forming the contact portion of the semiconductor device need only have a heating source whose emission wavelength is in the infrared region and at least a part of the emission wavelength in the ultraviolet region on the shorter wavelength side, for example, Ar, N₂It is also possible to apply a laser such as an excimer or a hydrogen lamp.
[0023]
Next, a second embodiment will be described with reference to FIGS.
FIG. 3 is a composition diagram for explaining the effect of the flash lamp in the reaction mode of the contact portion of Comparative Sample S4, where the vertical axis represents the elemental composition ratio (atom%) and the horizontal axis represents the Ar ion sputtering time (minutes). It represents. That is, the horizontal axis corresponds to the depth direction. A semiconductor device is manufactured according to the first embodiment described above. However, the heat treatment conditions for forming the contact portion between the metal wiring and the silicon semiconductor substrate in this embodiment are as follows: the substrate temperature is 100 to 480 ° C., and the irradiation energy density of the Xe flash lamp is 5 to 25 J / cm.²Set within the range.
That is, in this example, the substrate temperature by the first heating source is conditioned on the condition that the refractory metal film, here the Ti layer is not affected by the atmosphere during the heat treatment and does not induce deterioration as device characteristics, In the second heating source, the irradiation energy is set so that the reaction of the contact portion can be promoted within the low load of the light source body. In order to investigate the reaction effect of the contact portion in the example, the substrate temperature was set to 500 ° C., and the irradiation energy density of the Xe flash lamp was set to 10 J / cm.²A sample S4 set to be prepared as a comparative example.
[0024]
When the contact resistance between the Al electrode and the impurity diffusion layer of sample S4 of the comparative example was measured, it was 7.2 × 10.^-3Ωcm²Met.
From the above results, it was found that the contact resistance of the comparative example sample S4 increased compared to the sample S1 of the first example.
FIG. 3A shows the result of examining the reaction state of the contact portion from Auger spectroscopic analysis for the sample S4 of the comparative example.
In the comparative sample S4, a considerable amount of oxygen is taken into the Ti layer, and not only the Ti oxide film of about 15 nm exists on the outermost surface, but also the thickness of the Ti silicide layer has decreased. I understand. This suggests that the higher the substrate temperature, the more easily affected by the atmosphere, and the increase in the amount of oxygen entering from the substrate surface side limits the growth rate of the Ti silicide layer. That is, in the comparative sample S4, it is considered that the contact resistance is increased because the metal film Ti is oxidized to become an insulator and the growth of Ti silicide is suppressed.
[0025]
Therefore, the Xe flash lamp (irradiation energy: 10 J / cm) with the substrate temperature of the silicon semiconductor substrate set to room temperature.²) Alone, a sample S5 having the structure shown in FIG. The contact resistance of sample S5 at this time is 3.1 × 10^-FiveΩcm²It was significantly higher than the sample of the example. FIG. 3B shows the result of examining the reaction state of the contact portion of the sample S5 from Auger spectroscopic analysis.
From the above results, even if the substrate temperature by the first heating source is set too low in order to prevent the oxidation reaction of the Ti layer, the low resistance contact is formed only by the Xe flash lamp as the second heating source. Proves difficult. To form a metal silicide layer only by Xe flash lamp irradiation, 30 J / cm²The above irradiation energy density is expected to be required, but the higher the irradiation energy density, the more difficult it is to control the amount of metal silicide generated, and it is also practical from the viewpoint of the flash lamp load. I can't say that.
[0026]
FIG. 4 illustrates a substrate temperature by a first heating source and a Xe flash lamp (pulsed by a second heating source) necessary for forming a Ti silicide layer at a contact portion with a low thermal budget and forming a low-resistance ohmic contact. This shows the relationship with the irradiation energy density at the time of 1 msec in width. In the figure, the shaded area is 5 × 10 5 within the range considering the lifetime of the Xe flash lamp.^-7Ωcm²The conditions under which the following low resistance contact can be formed are shown. As the substrate temperature is increased up to around 480 ° C., 5 × 10 5 is obtained with low energy density flash irradiation.^-7Ωcm²It can be seen that the following low resistance contact is obtained.
FIG. 5 illustrates a case where the Xe flash lamp is irradiated 10 times. Increasing the number of irradiations will result in 5 × 10^-7Ωcm²It can be seen that the conditions under which the following low-resistance contact is obtained spread to the low temperature and low irradiation energy side.
From the above, the heat treatment conditions for forming the contact portion between the metal wiring and the silicon semiconductor substrate are the substrate temperature of 100 to 480 ° C. and the irradiation energy density of the Xe flash lamp of 5 to 25 J / cm.²It is appropriate to set within the range.
[0027]
Next, a third embodiment will be described with reference to FIG.
In this embodiment, a semiconductor device is manufactured according to the first embodiment. However, a metal conductive film to which 5 to 20% Si is added is deposited as an electrode base layer for forming a contact portion between the metal wiring and the silicon semiconductor substrate in this embodiment. A metal conductive film of Ti-10% Si is deposited on the contact bottom, and then an Xe flash lamp is applied at an energy density of 10 J / cm at a substrate temperature of 400 ° C. of the silicon semiconductor substrate.²A sample S6 having the structure shown in FIG.
That is, according to the present invention, before depositing the refractory metal film on the bottom of the contact, Si for forming a metal silicide layer at the contact interface is included in the refractory metal film in advance in the thermal process. The purpose is to reduce the junction leakage current by suppressing the forward diffusion amount to the silicon surface side of the silicon semiconductor substrate as the underlying substrate and suppressing the silicidation reaction.
[0028]
In order to investigate the effect of reducing the junction leakage current of the sample S6 in this example, the thermal process of the contact process is the same as that of the sample S6 of the example, but the sample S1 using a metal film Ti not added with Si as an electrode underlayer. A comparative experiment is performed using. In the sample S6 of the example, the junction leakage current at the time of applying the reverse bias voltage of 5 V was measured and found to be 3.5 × 10.^-9A / cm²Met. The contact resistance between the Al electrode and the impurity diffusion layer is 3.6 × 10^-7Ωcm²Met. On the other hand, when the junction leakage current was measured in the sample S1 of the comparative example (the example sample in the first example), 5.1 × 10 5 was obtained.^-7A / cm²(Contact resistance: 1.3 × 10^-7Ωcm²)Met. Furthermore, the junction leakage current of the conventional sample S3, which was heat-treated at 550 ° C. for 90 minutes using only the first heating source without using the second heating source, was 2.6 × 10.^-9A / cm²(Contact resistance: 2.5 × 10^-7Ωcm²)Met. As a result, the junction leakage current of the example sample S6 is the same level as that of the conventional sample S3, and although the contact resistance is increased when compared with the sample S1 of the comparative example, the junction leakage current is obtained. It can be seen that the leakage current is nearly two orders of magnitude lower and can be improved very effectively.
[0029]
Although the method for forming the contact portion combined with the second heat source has a remarkable effect in reducing the contact resistance because the metal silicide layer can be formed thick, on the other hand, the method for forming the contact portion on the metal film side of the underlying silicon semiconductor substrate is effective. It is considered that the amount of forward diffusion is large and vacancies are formed in the silicon semiconductor substrate, and the vacancies are included in the depletion layer when a reverse bias is applied, which causes an increase in junction leakage current. Therefore, by adding Si in advance before metal film deposition, the amount of Si diffusion from the underlying silicon semiconductor substrate accompanying heat treatment can be suppressed, and the metal silicide layer can be formed while controlling the silicidation reaction. This is considered to have led to an improvement in junction leakage current.
FIG. 6 shows an irradiation energy density of 10 J / cm with a Xe flash lamp at a substrate temperature of 400 ° C.²FIG. 6 is a characteristic diagram showing the relationship between contact resistance and junction leakage current (when 5 V is applied) with respect to the amount of Si added to Ti when one pulse is irradiated at. It can be seen that the contact resistance increases as the amount of Si added increases, but the junction leakage current decreases. It is shown that the range of Si addition amount that can satisfy the specifications from both sides of contact resistance and junction leakage current is 5 to 20%.
[0030]
As described above, it can be seen that it is effective to add 5 to 20% Si to the metal conductive film as the electrode base layer for forming a contact portion having good contact characteristics between the metal wiring and the silicon semiconductor substrate. .
Next, a fourth embodiment will be described with reference to FIGS.
In this embodiment, the present invention is applied to manufacture of a contact portion between an impurity diffusion region of a logic element and a connection plug. A MOS transistor is formed in the element region surrounded by the element isolation region (STI) 53 of the p-type silicon semiconductor substrate 51. The MOS transistor is formed on an n-type impurity diffusion region 57 constituting a source / drain region, a gate insulating film 54 made of a silicon oxide film formed between the impurity diffusion regions 57, and the gate insulating film 54. A gate electrode 50 made of polysilicon or the like and protected by a sidewall insulating film is formed. Cobalt silicide (CoSi) is formed on the surfaces of the gate electrode 50 and the impurity diffusion region 57.₂) Layer 55 is formed to reduce the resistance. A silicon nitride film 56 formed by plasma CVD is formed on the surface of the semiconductor substrate 51. On the silicon nitride film 56, an interlayer insulating film 52 made of a BPSG film and a TEOS film thereon is formed.
[0031]
The surface of the interlayer insulating film 52 is flattened, and a metal wiring 59 composed of a TiN / Ti barrier metal layer and an Al—Cu metal film sandwiched between the barrier metal layers is formed. The metal wiring 59 and the gate electrode 50 of the MOS transistor and the impurity diffusion region 57 are electrically connected by a connection plug 58 embedded in a contact hole formed in the interlayer insulating film 52. The connection plug 58 is composed of a TiN / Ti barrier metal layer formed on the inner wall of the contact hole and tungsten (W) wrapped in the barrier metal layer.
The connection plug 58 is connected to the silicide layer 55. The contact portion is shown in the region A shown in FIG. The silicide layer is formed by depositing a cobalt film on the polysilicon of the gate electrode 50 and the impurity diffusion region 57 by sputtering or the like, and heat-treating it to form a silicide. However, the contact structure shown in region A is SiO₂And since the CoO layer is formed, the resistance is high (FIG. 8A). Therefore, normally, after forming the barrier metal layer of the connection plug, annealing is performed at 550 ° C. for 90 minutes to obtain SiO₂In addition, the CoO layer is eliminated to reduce the resistance (FIG. 8B). In this example, annealing is not performed under such conditions, the semiconductor substrate is heated at 400 ° C. by infrared heating, and the energy density is 10 J / cm during heating.², One Xe flash lamp having a pulse width of 1 msec is irradiated. As a result, the structure of the A region shown in FIG. 8B, which is the same as the conventional one, can be obtained at a low temperature of 400 ° C.
[0032]
Next, a fifth embodiment will be described with reference to FIGS.
FIG. 12 shows an equivalent circuit of a 1-transistor 1-capacitor ferroelectric memory cell, which has the same circuit connection as an equivalent circuit of a DRAM cell. FIG. 13 is a cross-sectional view of a semiconductor substrate on which an FRAM is formed. A semiconductor substrate on which a conventional FRAM is formed has a structure in which a ferroelectric capacitor is formed on a transistor and a multilayer wiring is formed thereon. In this embodiment, the multilayer wiring is formed on the transistor as a sample to be heat-treated. A semiconductor substrate having a structure in which a ferroelectric capacitor is formed on a multilayer wiring is used. FIG. 14 is a flowchart for explaining a manufacturing process of a FRAM structure semiconductor device to which the present invention is applied. First, a MOS transistor used for a memory or the like is formed on a wafer (1), and then aluminum or metal wiring mainly composed of aluminum is formed in a multilayer structure through an interlayer insulating film (2). Thereafter, a capacitor having a ferroelectric film is formed through the interlayer insulating film (3). This semiconductor device is characterized in that the position of the capacitor is changed up and down as compared with the FRAM structure shown in FIG.
[0033]
C is an information recording capacitor using a ferroelectric material having a perovskite structure as an interelectrode insulating film, Q is a charge transfer MOS transistor connected in series with this capacitor, and WL is connected to the gate of this MOS transistor. The word line BL, the bit line PL connected to one of the source / drain regions of the MOS transistor, the plate line connected to one end (plate) of the capacitor, and VPL the plate line voltage.
FIG. 13 is a cross-sectional view of an FRAM including a capacitor having a ferroelectric film having ferroelectric characteristics. The semiconductor substrate 20 made of a p-type silicon semiconductor or the like is made of SiO by LOCOS method.₂An element isolation region constituted by is formed. An n-type impurity diffusion region 21 used as a source / drain region is formed in the surface region of the semiconductor substrate 20. A gate oxide film (SiO2) is formed between the source / drain regions.₂) 22 is formed through the gate electrode 23. The gate electrode 23 connected to the word line (WL) is composed of a polysilicon film and a tungsten silicide film on the polysilicon film, and the upper surface is protected by a silicon nitride film. The semiconductor substrate 20 is covered with a first insulating film 241 made of a BPSG (Born Phospharus Silicate Glass) film used as an interlayer insulating film formed by a low pressure CVD method so as to cover the gate electrode 23. The first insulating film 241 is polished and planarized by CMP (Chemical Mechanical Polishing) or the like.
[0034]
In the first interlayer insulating film 241, a metal wiring 251 such as aluminum with a barrier metal layer interposed is buried. On the first interlayer insulating film 241, second to fourth interlayer insulating films 242 to 244 made of silicon oxide films or the like in which second to fourth metal wirings 252 to 254 are embedded are formed, respectively. A fifth interlayer insulating film 245 is deposited on the fourth interlayer insulating film 244.
A ferroelectric capacitor C is formed on the fifth interlayer insulating film 245. The capacitor C is composed of a laminated body in contact with the interlayer insulating film 245 and sequentially depositing a lower electrode 301, a ferroelectric film 302 such as PZT having ferroelectric characteristics, and an upper electrode 303 connected to a plate line (PL). Has been. Contact holes are formed in the first to fifth interlayer insulating films 241 to 245, and connection plugs 27 such as tungsten are embedded therein, and the connection plugs 27 are formed in the lower electrode 301 and the source / drain regions of the MOS transistor Q. Is electrically connected to one of the two. The other of the source / drain regions is connected to a bit line (BL) (not shown).
[0035]
The lower electrode 301 is composed of a Ti film in contact with the interlayer insulating film 245 and a Pt film formed on the Ti film. The upper electrode 303 is composed of a Pt film. The insulating film 28 in which the insulating film 28 is formed on the interlayer insulating film 245 so as to cover the capacitor C is a TEOS film (SiO 2₂Film). The insulating film 28 is planarized by CMP or the like. A contact hole and a wiring groove are formed in the insulating film 28 by etching, and a metal wiring (PL) 29 such as aluminum is embedded therein.
In the FRAM described above, the capacitor ferroelectric film is formed by applying the crystallization method of the present invention. That is, a ferroelectric film such as PZT or SROP is formed in an amorphous state, and then crystallized by heat treatment to form a film used as a capacitor dielectric.
[0036]
Next, a sixth embodiment will be described with reference to FIG.
FIG. 15 is a cross-sectional view of a semiconductor substrate on which a capacitor having a ferroelectric film as a dielectric is formed. A p-type (100) silicon semiconductor substrate 31 is placed in a heating furnace and heated to 850 ° C. in an oxygen atmosphere to form a thermal oxide film 32 having a thickness of 100 nm. On this, an aluminum (Al) film 33 is deposited to a thickness of about 400 nm by sputtering using argon gas. On top of this, SiH_FourAnd N₂A silicon oxide film 34 is deposited to a thickness of about 500 nm by plasma CVD using O gas. A metal titanium (Ti) film 35 and platinum (Pt) 36 are further deposited on the semiconductor substrate 31 by sputtering to a thickness of 30 nm and 100 nm, respectively. Next, again using a sputtering apparatus, lead zirconate titanate (PbZr_xTi_1-xO_ThreeA film 37 (hereinafter referred to as PZT) is deposited to a thickness of about 150 nm. The gas used for sputtering at this time is argon gas, and the substrate temperature during sputtering is room temperature.
[0037]
The semiconductor substrate 31 is placed in the heat treatment apparatus shown in FIG. 9, and crystallization is performed while introducing oxygen. In this step, first, 3 kW was charged into the tungsten halogen lamp (first lamp) 6 from the bottom in order to preheat the semiconductor substrate 31, and the temperature was raised at a rate of 80 ° C. per second. The flash lamp (second lamp) 7 was turned on only once when the temperature reached 400 ° C. 5 seconds after the start of temperature increase, and the tungsten halogen lamp 6 was turned off immediately after that. The lighting time of the flash lamp 7 is 1.3 msec, and its energy is 12 J / cm.²It is.
Thus, when the semiconductor substrate which implemented this invention was analyzed by X-ray diffraction, in the sample (semiconductor substrate) which did not irradiate the flash lamp 6, PZT was not crystallized, but irradiated with the flash lamp. It was confirmed that the sample was crystallized in the perovskite phase. At the same time, the state of the underlying aluminum film 33 was examined with a microscope and a scanning electron microscope, but no change was observed, and it was clear that the PZT film 37 could be crystallized without changing the aluminum film 33. Became. When the preheating temperature by the tungsten halogen lamp 7 was fixed at 400 ° C. and the output of the flash lamp 8 required for crystallization of the PZT film was examined, it was 10 J / cm.²From the above, it was found that crystallization occurred.
[0038]
Conversely, when the range in which the PZT film 37 can be crystallized without changing the aluminum film 33 using the preheating temperature as a parameter is investigated, the preheating time is set to about 550 ° C. if the preheating time is within 1 second. It was also confirmed that no change occurred in the aluminum film 33.
A Pt film 38 was again formed on the semiconductor substrate 31 by sputtering using argon gas. The film thickness was 150 nm. When the polarization characteristics of this sample were measured, the remanent polarization value was 30 μC / cm.²In other words, it has been clarified that there is no inferiority to a PZT film crystallized by ordinary RTA.
If two types of lamps are turned on simultaneously, power is consumed accordingly. With the aim of reducing power consumption, for example, the tungsten halogen lamp 6 can be turned on and the flash lamp 7 can be turned on at the moment when the lamp is turned off. In this case, after the tungsten halogen lamp 6 that consumes several tens of kW of power is turned off, the temperature of the semiconductor substrate 31 is still maintained immediately after the turn-off. Therefore, only one electrode for lighting the lamp is required, and at the same time, power consumption can be reduced.
[0039]
The ferroelectric film is not limited to the PZT film but SBT (SrBiTa).₂O₉), BTO (BaTiO_ThreeHowever, it goes without saying that these films can be crystallized by implementing the present invention without causing any change in the aluminum film.
The present invention is not limited to the method of crystallizing a ferroelectric film formed on a semiconductor substrate, and is not limited to strontium titanate (SrTiO_Three, Abbreviated as STO), strontium barium titanate (Ba)_xSr_1-xTiO_Three), Crystallization of Ta₂O_FiveIt can be applied to a wide range of processes in which the thermal energy applied to the substrate, such as crystallization, must be suppressed.
[0040]
【The invention's effect】
  According to the present invention, the contact portion of a semiconductor device can be manufactured at a low temperature and rapidly with good controllability. New materials with low properties can be easily applied to semiconductor devices, and high performance of element characteristics can be realized.Further, the SiO present between the first silicide film and the second silicide film by the method of the present invention is used. ₂ In addition, since the CoO can be effectively eliminated, the resistance of the contact portion can be reduced.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a manufacturing process of a contact portion in a semiconductor device of the present invention.
FIG. 2 is a composition diagram showing the effect of a flash lamp in a reaction mode of a contact portion in samples of the present invention and a comparative example.
FIG. 3 is a composition diagram showing the effect of substrate temperature on the reaction mode of the contact portion in the samples of the present invention and comparative examples.
FIG. 4 is a characteristic diagram showing a relationship between a substrate temperature necessary for forming a low-resistance contact when the flash lamp is irradiated once and an irradiation energy density of the flash lamp.
FIG. 5 is a characteristic diagram showing the relationship between the substrate temperature required to form a low-resistance contact when the flash lamp is irradiated 10 times and the irradiation energy density of the flash lamp.
FIG. 6 is a characteristic diagram showing the relationship between the amount of Si added to the base metal film, contact resistance, and junction leakage current.
FIG. 7 is a cross-sectional view of a silicon semiconductor substrate on which a logic element of the present invention is formed.
8 is a cross-sectional view showing the structure of region A in FIG. 7;
FIG. 9 is a schematic cross-sectional view of the heat treatment apparatus of the present invention.
FIG. 10 is a characteristic diagram showing the lamp energy and the energy dependence of the lamp irradiated with temperature by heat treatment of the ferroelectric film, illustrating the present invention.
FIG. 11 is a characteristic diagram showing the relationship between the crystallization temperature and the heat treatment time for explaining the present invention.
FIG. 12 is an equivalent circuit diagram of a ferroelectric memory cell having a one-transistor / one-capacitor configuration.
FIG. 13 is a cross-sectional view of a semiconductor substrate on which an FRAM of the present invention is formed.
FIG. 14 is a manufacturing process diagram of a FRAM structure semiconductor device applied to the invention;
FIG. 15 is a cross-sectional view of a semiconductor substrate on which a capacitor using the ferroelectric film of the present invention as a dielectric is formed.
FIG. 16 is a cross-sectional view of a conventional FRAM element.
[Explanation of symbols]
1 ... sample chamber, 2 ... sample stage, 3 ... gas inlet,
4 ... exhaust port, 5 ... quartz window,
6 ... 1st lamp (tungsten halogen lamp),
7: Second lamp (flash lamp),
8 ... sample, 9, 10 ... power supply, 20,31 ... silicon substrate,
21, 47, 57... Impurity diffusion region, 22... Gate oxide film,
23, 50 ... gate electrode, 27 ... connection plug,
28 ... insulating film 29, 251-254 ... metal wiring,
32 ... thermal oxide film, 33 ... aluminum film,
34 ... silicon oxide film, 35 ... metal titanium film,
36 ... platinum film, 37 ... lead zirconate titanate film,
41, 51 ... silicon semiconductor substrate, 42 ... SiO₂film,
43 ... contact hole, 44 ... ion implantation layer,
45 ... metal film, 46 ... metal film with low resistivity,
48 ... Electrode, 52, 241-245 ... Interlayer insulating film,
53 ... element isolation region, 54 ... gate insulating film,
55 ... Silicide layer, 56 ... Silicon nitride film,
58 ... connection plug, 59 ... metal wiring,
101, 301 ... lower electrode, 102, 302 ... ferroelectric film,
103, 303 ... upper electrodes, 241 to 245 ... interlayer insulating films.

Claims (2)

Forming an insulating film on the semiconductor substrate, and forming a contact hole in the insulating film for exposing the first silicide film having the first metal formed on the semiconductor substrate;
Depositing a second metal connected to the first silicide film exposed from the contact hole to form a contact portion;
Forming a second silicide film having a second metal on the first silicide film having the first metal by heat-treating the semiconductor substrate to improve the contact property of the contact portion. ,
In the step of heat-treating the semiconductor substrate, two heating sources having different emission wavelength distributions and irradiation times are used to irradiate a halogen lamp that is a first heating source, and a flash lamp that is a second heating source during the irradiation. Is irradiated for a time shorter than the irradiation time of the first heat source. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the halogen lamp is turned off after the flash lamp is turned off .

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