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JP3923661B2 - Semiconductor device - Google Patents

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Publication number
JP3923661B2
JP3923661B2 JP24797998A JP24797998A JP3923661B2 JP 3923661 B2 JP3923661 B2 JP 3923661B2 JP 24797998 A JP24797998 A JP 24797998A JP 24797998 A JP24797998 A JP 24797998A JP 3923661 B2 JP3923661 B2 JP 3923661B2
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Prior art keywords
insulating substrate
adhesive
semiconductor chip
semiconductor device
terminal
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JP24797998A
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JP2000077433A (en
Inventor
友春 堀尾
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Rohm Co Ltd
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Rohm Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Description

【０００１】
【技術分野】
本願発明は、合成樹脂製フィルムなどから形成された絶縁基板上に接着剤を利用して半導体チップを接着したタイプの半導体装置に関する。
【０００２】
【従来の技術】
周知のとおり、樹脂パッケージ型の半導体装置を製造する手段としては、金属製のリードフレームを利用し、このリードフレーム上に半導体チップを搭載する手段がある。ところが、この手段では、リードフレームの一部分を樹脂パッケージの外部に端子として露出させる必要があるために、半導体装置全体の幅や厚みのサイズが大きくなり易い。また、リードフレームは一般にはかなり複雑な形状に形成する必要があり、そのコストが高価であるために、最終的に得られる半導体装置の製造コストも高価になってしまう。
【０００３】
そこで、従来では、リードフレームを利用する手段に代えて、たとえば薄手の合成樹脂製フィルムやその他の材質からなる絶縁基板を利用する手段も採用されている。具体的には、この従来の手段は、図１１に示すように、たとえば薄手の合成樹脂製フィルムからなる絶縁基板９０の表面上に、接着剤９１を介して半導体チップ３ｅを接着するとともに、この半導体チップ３ｅの複数の電極３０ｅと絶縁基板９０の複数の端子部９２とを金線などのワイヤＷを介して電気的に接続する手段である。このような手段によれば、絶縁基板９０の原材料コストを安価にすることができる。また、たとえば絶縁基板９０の裏面にハンダバンプ９３を設けることによって、全体の幅や厚みを大きく嵩張らないようにして、面実装型の半導体装置として仕上げることができる。
【０００４】
【発明が解決しようとする課題】
しかしながら、上記従来の手段では、次のような不具合を生じていた。
【０００５】
すなわち、絶縁基板９０の表面上に半導体チップ３ｅを適切に接着させるには、平面視において接着剤９１が半導体チップ３ｅの外周にはみ出しを生じる程度の広い範囲で接着剤９１を絶縁基板９０の表面部に塗布する必要がある。接着剤９１の塗布面積や塗布量が少ないと、接着剤９１の内部に空洞部が発生し易くなり、たとえばハンダバンプ９３をリフローさせようとしてこのハンダバンプ９３を加熱する際に、上記空洞部内のエアが膨張する現象を生じ、適切ではないからである。より具体的には、上記空洞部内のエアの膨張は、リードフレームを用いる手段ではさほど大きな問題を生じさせないものの、絶縁基板９０としてたとえば軟質な合成樹脂製が用いられている場合には、この絶縁基板９０が上記エアの膨張に起因して半導体チップ３ｅの周辺部分において大きく膨らむように撓み変形する要因となり、ハンダバンプ９３に位置ずれが生じるのである。
【０００６】
ところが、従来では、接着剤９１を半導体チップ３ｅの外周にはみ出す程度に塗布すると、この接着剤９１が硬化する以前の状態において、矢印Ｎａ方向に流動し、端子部９２の表面に流れ込む場合があった。とくに、上記半導体装置の製造に際して、半導体チップ３ｅの接着を確実にする手法としては、半導体チップ３ｅをその上方から下向きに押圧するのが一般的であるために、上記接着剤９１は、端子部９２の表面により流れ込み易くなっていたのである。したがって、従来では、端子部９２の表面に接着剤が付着することに起因して、この端子部９２へのワイヤＷのボンディング作業を適切に行えなくなる場合があった。また、従来では、このような事態をできる限り防止する観点から、端子部９２を半導体チップ３ｅに余り接近させることができず、半導体装置の小型化を図る上で一定の限界を生じていた。さらに、従来では、接着剤９１が端子部９２の表面に流れ込まないようにするための接着剤９１の塗布量や塗布位置の管理も厳格に行う必要があった。
【０００７】
本願発明は、このような事情のもとで考え出されたものであって、絶縁基板の表面に接着剤を用いて半導体チップを接着する場合に、半導体チップと絶縁基板の端子部とを大きく離反させるようなことなく、接着剤が絶縁基板の端子部に流れ込むことを簡易な手段によって適切に防止できるようにすることをその課題としている。
【０００８】
【発明の開示】
上記の課題を解決するため、本願発明では、次の技術的手段を講じている。
【０００９】
本願発明により提供される半導体装置は、表面に複数条の導電配線が形成されるとともに、これら導電配線の一端部からなる複数の端子部が外周縁に沿って形成され、かつ、上記複数条の導電配線のうち上記各端子部以外の領域を覆うように略全面にレジスト層が設けられた絶縁基板と、この絶縁基板の表面上における上記複数の端子部によって囲まれる領域における上記レジスト層上に接着剤を介して接着された半導体チップとを具備しており、かつ上記半導体チップの電極と上記絶縁基板上の上記端子部とはワイヤを介して接続されている、半導体装置であって、上記レジスト層のうち、上記半導体チップの接着箇所と上記端子部との間に形成した上記導電配線の蛇行部を覆う部位は、上記接着剤がその未硬化状態において上記絶縁基板上の上記端子部に流れ込むことを防止可能な凸状の段部を形成していることに特徴づけられる。
【００１０】
【００１１】
【００１２】
本願発明では、絶縁基板の表面上に塗布された接着剤が未硬化状態において絶縁基板の端子部の方向に流れる事態を生じても、凸状の段部によってその流れを堰き止めるなどして、上記接着剤が端子部の方向へそれ以上流れないようにすることができる。したがって、本願発明では、上記端子部の表面に接着剤が不当に付着することを防止することができ、絶縁基板上に搭載された半導体チップの電極と上記端子部とのワイヤ接続を適切に行うことができる。本願発明では、半導体チップの接着箇所と絶縁基板の端子部との間の距離を小さくした場合であっても、端子部の表面に接着剤が流れ込まないようにできる。したがって、半導体装置全体のサイズを従来よりも小さくすることが可能となる。また、本願発明では、絶縁基板の表面に接着剤をかなり多めに塗布しても端子部の表面に接着剤が流れ込むことを防止することが可能となるため、絶縁基板に対する接着剤の塗布作業の管理も容易なものにできる。
【００１３】
本願発明のその他の特徴および利点については、次の発明の実施の形態の説明から、より明らかになるであろう。
【００１４】
【発明の実施の形態】
以下、本願発明の好ましい実施の形態について、図面を参照しつつ具体的に説明する。
【００１５】
図１は、本願発明に係る半導体装置の参考例を示す断面図である。図２は、図１に示す半導体装置の平面透視図である。
【００１６】
図１において、半導体装置Ａは、いわゆるボールグリッドアレイタイプの樹脂パッケージ型半導体装置として構成されたものである。この半導体装置Ａは、複数の端子部１１を有する絶縁基板１、レジスト層１２、凸状の段部１３、接着剤２、半導体チップ３、封止樹脂４、および複数のハンダバンプ５を具備して構成されている。
【００１７】
上記絶縁基板１は、たとえばポリイミドなどの薄手の合成樹脂製フィルムからなり、その平面視の形態は半導体チップ３よりも一廻り大きな矩形状である。上記絶縁基板１の表面には、複数条の帯状の導電配線１０がパターン形成されている。これら複数条の導電配線１０は、たとえば銅箔によって形成されており、後述する図３の説明から理解されるように、それらの一端が上記複数の端子部１１となっている。これら複数の端子部１１は、接着剤２の塗布領域（半導体チップ３の接着箇所）を囲むように上記絶縁基板１の外周縁に沿って並んでいる。上記複数のハンダバンプ５は、この半導体装置Ａを所望の位置へ面実装するのに利用されるものであり、上記複数条の導電配線１０のそれぞれの他端部の下面に接合しているとともに、上記絶縁基板１に設けられた貫通孔１４を介して絶縁基板１の下方に突出している。
【００１８】
上記レジスト層１２は、上記複数条の導電配線１０を保護するためのものであり、上記複数条の導電配線１０のうち上記複数の端子部１１以外の領域を覆うように絶縁基板１の表面の略全面にわたって設けられている。上記段部１３は、上記レジスト層１２によって形成されている。上記段部１３は、上記レジスト層１２を形成するレジストのスクリーン印刷を複数回にわたって繰り返して行い、上記レジスト層１２の一部の厚みを他の部分の厚みよりも大きくした凸状部分である。上記段部１３は、図２によく表れているように、平面視の全体形状が中空矩形状となる筋状であり、上記複数の端子部１１の配置領域よりも内側の領域において半導体チップ３の接着箇所を囲むように設けられている。
【００１９】
上記半導体チップ３は、たとえばＩＣチップであり、上記絶縁基板１のレジスト層１２上に接着剤２を介して接着されている。上記接着剤２としては、たとえば熱硬化性のエポキシ樹脂系のものが適用されている。上記半導体チップ３の上向きの主面に設けられた複数の電極３０と上記複数の端子部１１とは、金線などのワイヤＷを介して導電接続されている。上記封止樹脂４は、上記半導体チップ３やワイヤＷを封止して、これらを保護するためのものである。
【００２０】
次に、上記半導体装置Ａの製造方法の一例について説明する。
【００２１】
まず、上記絶縁基板１を形成するための部材として、図３に示すような帯状のフィルム基板１ａを用いる。このフィルム基板１ａの表面には、複数条の導電配線１０を１組とする導電配線パターンＰが、このフィルム基板１ａの長手方向に一定間隔で多数組設けられている。図３では、その図示を省略しているが、実際には、図４に示すように、上記フィルム基板１ａの表面には上記複数条の導電配線１０を覆うレジスト層１２が設けられている。また、このレジスト層１２によって凸状の段部１３も形成されている。上記フィルム基板１ａには、後にハンダバンプ５を接合させるための複数の貫通孔１４も設けられている。
【００２２】
図５に示すように、上記フィルム基板１ａのレジスト層１２上には、接着剤２を塗布してから半導体チップ３を接着する。この工程は、流動可能な液状またはペースト状態で接着剤２を塗布してから、その上に半導体チップ３を載置し、上記接着剤２を加熱しながら上記半導体チップ３の上面を下方に向けて押圧しながら行う。また、上記接着剤２は、半導体チップ３の周囲に若干量だけはみ出すように多めに塗布し、接着剤２内に空洞部が生じないようにする。したがって、上記接着剤２が加熱によって硬化するまでの間は、図５および図６の矢印Ｎ１に示すように、上記接着剤２がその四方に流動する虞れがある。ところが、そのような事態を生じても、上記接着剤２は凸状の段部１３によって堰き止められる。したがって、上記接着剤２が上記段部１３の外側に位置する複数の端子部１１まで流動しないようにできる。
【００２３】
半導体チップ３の接着作業後には、各電極３０と各端子部１１とにワイヤＷのボンディング作業を行う。次いで、金型を用いた樹脂成形工程によって上記封止樹脂４を形成し、さらにはハンダバンプ５の形成作業を行う。その後は、上記フィルム基板１ａを絶縁基板１とするように切断し、または打ち抜く。このような一連の作業工程により、上記帯状のフィルム基板１ａから多数の半導体装置Ａを順次生産することができる。
【００２４】
上記半導体装置Ａでは、複数の端子部１１の表面に接着剤２が不当に付着しないようにできるために、これら複数の端子部１１へのワイヤＷのボンディング作業を適切に行うことが可能である。とくに、上記凸状の段部１３は、接着剤２の塗布領域の四方全周を囲むように形成されているために、複数の端子部１１の表面が接着剤１２によって汚れることをより確実に防止することができる。
【００２５】
図７は、本願発明に係る半導体装置の一実施形態を示す断面図である。図８は、図７に示す半導体装置に用いられている絶縁基板の導電配線パターンを示す要部概略斜視図である。なお、図７以降の各図においては、先の参考例と同一部分は同一符号で示す。
【００２６】
図７に示す半導体装置Ａａは、絶縁基板１の表面上のうち、半導体チップ３の接着箇所と複数の端子部１１との間に凸状の段部１３Ａが設けられている点で、先の半導体装置Ａと共通している。ただし、上記段部１３Ａは、複数条の導電配線１０Ａ上にレジスト層１２を形成することによって設けられている。より具体的には、図８によく表れているように、上記各導電配線１０Ａは、ハンダバンプ５が接合される一端部１０’からその他端部である端子部１１に到るまでの中間部の平面視形状がジグザグ状、クランク状、あるいは略コの字状などに蛇行した形状とされており、この導電配線１０Ａの形成部分は絶縁基板１自体の表面と比較すると凸状となっている。したがって、上記絶縁基板１の表面や各導電配線１０Ａの表面に厚みが均一のレジスト層１２を形成すると、このレジスト層１２のうち上記導電配線１０Ａの形成箇所の高さが他の部分よりも高くなり、これが１条または複数条の凸状の段部１３Ａとなっているのである。
【００２７】
上記半導体装置Ａａにおいても、上記段部１３Ａによって接着剤２が複数の端子部１１に向けて流れることを防止することができ、各端子部１１に対するワイヤボンディングを適切に行うことができる。このように、本願発明では、絶縁基板１上に形成される導電配線パターンの厚みを利用して接着剤の流動を阻止するための段部を設けた構成としてもかまわない。さらに、本願発明では、導電配線パターンやレジスト層を利用することなく、それ以外の物質または部材を絶縁基板上に設けることよって凸状の段部を形成し、これによって接着剤の流動を阻止するようにしてもかまわない。
【００２８】
図９は、本願発明に係る半導体装置の他の参考例を示す断面図である。図１０は、本願発明に係る半導体装置の他の参考例を示す平面透視図である。
【００２９】
図９に示す半導体装置Ａｂでは、絶縁基板１Ｂの表面に凹状の段部１３Ｂが設けられている。この段部１３Ｂは、絶縁基板１Ｂの表面に凹溝を直接形成することにより設けられたものであり、その平面視形状は、たとえば先の半導体装置Ａの段部１３と同様に、複数の端子部１１の形成領域よりも内側において接着剤２の塗布領域を囲む中空矩形状とされている。
【００３０】
上記半導体装置Ａｂでは、その製造過程において上記接着剤２が四方に流動する事態を生じたときには、この接着剤２を上記凹状の段部１３Ｂ内に落とし込むことによって、接着剤２がそれ以上複数の端子部１１の方向に流動することを阻止し、または抑制することができる。
【００３１】
絶縁基板に凹状の段部を形成する場合には、この段部の存在によって絶縁基板の強度に不足が生じないように配慮する必要がある。したがって、凹状の段部を形成する手段は、絶縁基板の厚みが比較的大きい場合、あるいは絶縁基板を強度性に優れた材質とした場合に適する。また、絶縁基板の材質をたとえばガラスエポキシ樹脂製にした場合には、絶縁基板の表面に適当なジグを押し当てることによって凹状の段部を簡単に形成することができ、その製造を容易なものにできる。上記凹状の段部１３Ｂは、絶縁基板１Ｂの表面に形成された凹溝上にレジスト層１２の一部が存在した構成となっている。ただし、本願発明では、これに代えて、たとえば絶縁基板１Ｂ自体には凹溝を形成することなく、レジスト層１２にのみ凹溝を形成し、これを凹状の段部としてもかまわない。
【００３２】
図１０に示す半導体装置Ａｃは、絶縁基板１Ｃの複数の端子部１１が半導体チップ３Ｃの左右両側方にのみ設けられており、これら複数の端子部１１と半導体チップ３Ｃとの間には、凸状または凹状の段部１３Ｃ，１３Ｃが平面視直線状の形態で設けられている。この半導体装置Ａｃでは、接着剤２が四方に広がる事態を生じても、上記段部１３Ｃ，１３Ｃによって上記接着剤２が複数の端子部１１の表面に流れ込まないようにできる。また、同図の矢印Ｎ２方向に広がる接着剤については、上記段部１３Ｃ，１３Ｃによってその流れをくい止めることはできないものの、その方向に接着剤が比較的大きく広がってもとくに支障は生じない。このように、本願発明でいう段部は、必ずしも半導体チップの接着箇所の周囲を囲むように設けられている必要はない。段部は、要は、少なくとも半導体チップの接着箇所と絶縁基板の端子部との間に設けられていればよい。むろん、段部の具体的な数も問わない。
【００３３】
本願発明は、上述の実施形態に限定されない。本願発明でいう絶縁基板とは、リードフレームなどの金属やその他の導電部材からなる基板を除外する概念であり、絶縁部材からなるものであれば、その具体的な材質もとくに限定されるものではない。
【図面の簡単な説明】
【図１】 本願発明に係る半導体装置の参考例を示す断面図である。
【図２】 図１に示す半導体装置の平面透視図である。
【図３】 絶縁基板を形成するためのフィルム基板の一例を示す要部斜視図である。
【図４】 レジスト層を有するフィルム基板の要部断面図である。
【図５】 フィルム基板上に半導体チップを接着する工程を示す要部断面図である。
【図６】 図５の要部平面図である。
【図７】 本願発明に係る半導体装置の一実施形態を示す断面図である。
【図８】 図７に示す半導体装置に用いられている絶縁基板の導電配線パターンを示す要部概略斜視図である。
【図９】 本願発明に係る半導体装置の他の参考例を示す断面図である。
【図１０】 本願発明に係る半導体装置の他の参考例を示す平面透視図である。
【図１１】 従来の半導体装置の一例を示す要部断面図である。
【符号の説明】
１ 絶縁基板
１ａ フィルム基板（絶縁基板）
２ 接着剤
３，３Ｃ 半導体チップ
４ 封止樹脂
５ ハンダバンプ
１１ 端子部
１２ レジスト層
１３，１３Ａ〜１３Ｃ 段部
３０ 電極
Ｗ ワイヤ
Ａ，Ａａ〜Ａｃ 半導体装置[0001]
【Technical field】
The present invention relates to a semiconductor device of a type in which a semiconductor chip is bonded onto an insulating substrate formed of a synthetic resin film or the like using an adhesive.
[0002]
[Prior art]
As is well known, as a means for manufacturing a resin package type semiconductor device, there is a means for using a metal lead frame and mounting a semiconductor chip on the lead frame. However, with this means, since it is necessary to expose a part of the lead frame as a terminal outside the resin package, the width and thickness of the entire semiconductor device tend to increase. In addition, the lead frame generally needs to be formed in a considerably complicated shape, and the cost is expensive, so that the manufacturing cost of the finally obtained semiconductor device is also expensive.
[0003]
Therefore, conventionally, instead of means using a lead frame, means using an insulating substrate made of, for example, a thin synthetic resin film or other material has been adopted. Specifically, as shown in FIG. 11, this conventional means adheres the semiconductor chip 3e to the surface of an insulating substrate 90 made of, for example, a thin synthetic resin film via an adhesive 91, and This is means for electrically connecting a plurality of electrodes 30e of the semiconductor chip 3e and a plurality of terminal portions 92 of the insulating substrate 90 via wires W such as gold wires. According to such means, the raw material cost of the insulating substrate 90 can be reduced. Further, for example, by providing the solder bumps 93 on the back surface of the insulating substrate 90, the overall width and thickness can be prevented from becoming large and bulky, so that a surface mounting type semiconductor device can be finished.
[0004]
[Problems to be solved by the invention]
However, the conventional means described above has the following problems.
[0005]
That is, in order to appropriately bond the semiconductor chip 3e on the surface of the insulating substrate 90, the adhesive 91 is applied to the surface of the insulating substrate 90 in a wide range such that the adhesive 91 protrudes from the outer periphery of the semiconductor chip 3e in plan view. It is necessary to apply to the part. When the application area and the application amount of the adhesive 91 are small, a cavity is likely to be generated inside the adhesive 91. For example, when the solder bump 93 is heated to reflow the solder bump 93, the air in the cavity is This is because an expansion phenomenon occurs and is not appropriate. More specifically, the expansion of the air in the cavity does not cause a significant problem with the means using the lead frame, but this insulation is used when the insulating substrate 90 is made of, for example, a soft synthetic resin. This causes the substrate 90 to bend and deform so as to swell greatly in the peripheral portion of the semiconductor chip 3e due to the expansion of the air, and the solder bump 93 is displaced.
[0006]
However, conventionally, if the adhesive 91 is applied to the extent that it protrudes to the outer periphery of the semiconductor chip 3e, it may flow in the direction of the arrow Na and flow into the surface of the terminal portion 92 before the adhesive 91 is cured. It was. In particular, when the semiconductor device is manufactured, as a technique for ensuring the adhesion of the semiconductor chip 3e, it is common to press the semiconductor chip 3e downward from above, and therefore, the adhesive 91 has a terminal portion. It was easier to flow into the surface of 92. Therefore, conventionally, there is a case where the bonding work of the wire W to the terminal portion 92 cannot be appropriately performed due to the adhesion of the adhesive to the surface of the terminal portion 92. Conventionally, from the viewpoint of preventing such a situation as much as possible, the terminal portion 92 cannot be brought too close to the semiconductor chip 3e, and there has been a certain limit in reducing the size of the semiconductor device. Further, conventionally, it has been necessary to strictly manage the application amount and application position of the adhesive 91 in order to prevent the adhesive 91 from flowing into the surface of the terminal portion 92.
[0007]
The present invention has been conceived under such circumstances, and when a semiconductor chip is bonded to the surface of the insulating substrate using an adhesive, the semiconductor chip and the terminal portion of the insulating substrate are greatly increased. It is an object of the present invention to appropriately prevent the adhesive from flowing into the terminal portion of the insulating substrate by simple means without causing separation.
[0008]
DISCLOSURE OF THE INVENTION
In order to solve the above problems, the present invention takes the following technical means.
[0009]
In the semiconductor device provided by the present invention, a plurality of conductive wirings are formed on the surface, a plurality of terminal portions composed of one end portions of these conductive wirings are formed along the outer peripheral edge, and An insulating substrate provided with a resist layer on substantially the entire surface so as to cover a region other than the terminal portions of the conductive wiring, and the resist layer in a region surrounded by the plurality of terminal portions on the surface of the insulating substrate. A semiconductor device comprising a semiconductor chip bonded via an adhesive, and the electrode of the semiconductor chip and the terminal portion on the insulating substrate are connected via a wire, of the resist layer, a portion covering the meander of the conductive wiring formed between the adhesive portion and the terminal portion of the semiconductor chip, the insulating substrate the adhesive is in its uncured state Characterized in that the forming the convex stepped portion capable prevented from flowing into the terminal section.
[0010]
[0011]
[0012]
In the present invention, even if a situation where the adhesive applied to the surface of the insulating substrate flows in the direction of the terminal portion of the insulating substrate in an uncured state, and the like damming its flow by convex stepped portion, It is possible to prevent the adhesive from flowing further in the direction of the terminal portion. Therefore, in this invention, it can prevent that an adhesive agent adheres to the surface of the said terminal part inappropriately, and performs the wire connection of the electrode of the semiconductor chip mounted on the insulating substrate, and the said terminal part appropriately be able to. In this invention, even if it is a case where the distance between the adhesion location of a semiconductor chip and the terminal part of an insulated substrate is made small, an adhesive agent can be prevented from flowing into the surface of a terminal part. Therefore, the size of the entire semiconductor device can be made smaller than before. Further, in the present invention, it is possible to prevent the adhesive from flowing into the surface of the terminal portion even if a relatively large amount of adhesive is applied to the surface of the insulating substrate. Easy management.
[0013]
Other features and advantages of the present invention will become more apparent from the following description of embodiments of the invention.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a preferred embodiment of the present invention will be specifically described with reference to the drawings.
[0015]
FIG. 1 is a cross-sectional view showing a reference example of a semiconductor device according to the present invention. FIG. 2 is a plan perspective view of the semiconductor device shown in FIG.
[0016]
In Figure 1, a semi-conductor device A are those that are configured as a resin packaged semiconductor device of the so-called ball grid array type. The semiconductor device A includes an insulating substrate 1 having a plurality of terminal portions 11, a resist layer 12, a convex step portion 13, an adhesive 2, a semiconductor chip 3, a sealing resin 4, and a plurality of solder bumps 5. It is configured.
[0017]
The insulating substrate 1 is made of a thin synthetic resin film such as polyimide, and has a rectangular shape that is a size larger than the semiconductor chip 3 in plan view. On the surface of the insulating substrate 1, a plurality of strip-like conductive wirings 10 are formed in a pattern. The plurality of conductive wires 10 are formed of, for example, copper foil, and one end thereof is the plurality of terminal portions 11 as understood from the description of FIG. The plurality of terminal portions 11 are arranged along the outer peripheral edge of the insulating substrate 1 so as to surround the application region of the adhesive 2 (bonded portion of the semiconductor chip 3). The plurality of solder bumps 5 are used for surface mounting the semiconductor device A to a desired position, and are bonded to the lower surfaces of the other end portions of the plurality of conductive wirings 10. It protrudes below the insulating substrate 1 through a through hole 14 provided in the insulating substrate 1.
[0018]
The resist layer 12 is for protecting the plurality of conductive wirings 10, and is formed on the surface of the insulating substrate 1 so as to cover a region other than the plurality of terminal portions 11 in the plurality of conductive wirings 10. It is provided over almost the entire surface. The step 13 is formed by the resist layer 12. The step portion 13 is a convex portion in which a resist screen forming the resist layer 12 is repeatedly screen printed a plurality of times, and the thickness of a part of the resist layer 12 is larger than the thickness of other portions. As shown in FIG. 2, the stepped portion 13 has a streak shape whose overall shape in plan view is a hollow rectangular shape, and the semiconductor chip 3 is located in a region inside the region where the plurality of terminal portions 11 are arranged. It is provided so as to surround the adhesion part.
[0019]
The semiconductor chip 3 is, for example, an IC chip, and is bonded to the resist layer 12 of the insulating substrate 1 with an adhesive 2. As the adhesive 2, for example, a thermosetting epoxy resin-based one is applied. The plurality of electrodes 30 provided on the upward main surface of the semiconductor chip 3 and the plurality of terminal portions 11 are conductively connected through wires W such as gold wires. The sealing resin 4 is for sealing the semiconductor chip 3 and the wires W and protecting them.
[0020]
Next, an example of a method for manufacturing the semiconductor device A will be described.
[0021]
First, as a member for forming the insulating substrate 1, a band-shaped film substrate 1a as shown in FIG. 3 is used. On the surface of the film substrate 1a, a large number of conductive wiring patterns P each including a plurality of conductive wirings 10 are provided at regular intervals in the longitudinal direction of the film substrate 1a. Although not shown in FIG. 3, actually, as shown in FIG. 4, a resist layer 12 is provided on the surface of the film substrate 1 a to cover the plurality of conductive wirings 10. The resist layer 12 also forms a convex step portion 13. The film substrate 1a is also provided with a plurality of through holes 14 for bonding solder bumps 5 later.
[0022]
As shown in FIG. 5, the semiconductor chip 3 is bonded onto the resist layer 12 of the film substrate 1a after the adhesive 2 is applied. In this step, the adhesive 2 is applied in a flowable liquid or paste state, and then the semiconductor chip 3 is placed thereon, and the upper surface of the semiconductor chip 3 is directed downward while heating the adhesive 2. Press while pressing. Further, the adhesive 2 is applied in a large amount so that it slightly protrudes around the semiconductor chip 3, so that no cavity is formed in the adhesive 2. Therefore, until the adhesive 2 is cured by heating, the adhesive 2 may flow in the four directions as indicated by an arrow N1 in FIGS. However, even if such a situation occurs, the adhesive 2 is dammed by the convex step portion 13. Therefore, the adhesive 2 can be prevented from flowing to the plurality of terminal portions 11 positioned outside the stepped portion 13.
[0023]
After the semiconductor chip 3 is bonded, the wire W is bonded to each electrode 30 and each terminal portion 11. Next, the sealing resin 4 is formed by a resin molding process using a mold, and further, a solder bump 5 is formed. Thereafter, the film substrate 1a is cut or punched so as to be the insulating substrate 1. Through such a series of work steps, a large number of semiconductor devices A can be sequentially produced from the strip-shaped film substrate 1a.
[0024]
In the semiconductor device A, since the adhesive 2 can be prevented from unfairly adhering to the surfaces of the plurality of terminal portions 11, it is possible to appropriately perform the bonding work of the wires W to the plurality of terminal portions 11. . In particular, since the convex step portion 13 is formed so as to surround the entire circumference of the four sides of the application region of the adhesive 2, the surface of the plurality of terminal portions 11 is more reliably contaminated by the adhesive 12. Can be prevented.
[0025]
FIG. 7 is a sectional view showing an embodiment of a semiconductor device according to the present invention. FIG. 8 is a schematic perspective view of a main part showing a conductive wiring pattern of an insulating substrate used in the semiconductor device shown in FIG. 7 and the subsequent drawings, the same parts as those in the previous reference example are denoted by the same reference numerals.
[0026]
The semiconductor device Aa shown in FIG. 7 is different from the surface of the insulating substrate 1 in that a protruding step portion 13A is provided between the bonding portion of the semiconductor chip 3 and the plurality of terminal portions 11. Common to the semiconductor device A. However, the step portion 13A is provided by forming the resist layer 12 on the plurality of conductive wirings 10A. More specifically, as clearly shown in FIG. 8, each conductive wiring 10 </ b> A has an intermediate portion from one end portion 10 ′ where the solder bump 5 is joined to the terminal portion 11 which is the other end portion. The shape in plan view is a zigzag shape, a crank shape, or a meandering shape such as a substantially U shape, and the portion where the conductive wiring 10A is formed has a convex shape as compared with the surface of the insulating substrate 1 itself. Therefore, when the resist layer 12 having a uniform thickness is formed on the surface of the insulating substrate 1 or the surface of each conductive wiring 10A, the height of the portion where the conductive wiring 10A is formed in the resist layer 12 is higher than other portions. Thus, this is the one or a plurality of convex stepped portions 13A.
[0027]
Also in the semiconductor device Aa, the step portion 13A can prevent the adhesive 2 from flowing toward the plurality of terminal portions 11, and wire bonding to each terminal portion 11 can be performed appropriately. As described above, in the present invention, a stepped portion for preventing the flow of the adhesive may be provided by using the thickness of the conductive wiring pattern formed on the insulating substrate 1. Furthermore, in this invention, without using a conductive wiring pattern or a resist layer, a convex step part is formed by providing another substance or member on the insulating substrate, thereby preventing the flow of the adhesive. It doesn't matter if you do.
[0028]
FIG. 9 is a sectional view showing another reference example of the semiconductor device according to the present invention. FIG. 10 is a plan perspective view showing another reference example of the semiconductor device according to the present invention.
[0029]
In the semiconductor device Ab shown in FIG. 9, a concave step portion 13B is provided on the surface of the insulating substrate 1B. The step portion 13B is provided by directly forming a groove on the surface of the insulating substrate 1B, and the shape of the step view thereof is, for example, similar to the step portion 13 of the semiconductor device A, a plurality of terminals. A hollow rectangular shape surrounding the application region of the adhesive 2 inside the region where the part 11 is formed is formed.
[0030]
In the semiconductor device Ab, when a situation occurs in which the adhesive 2 flows in all directions in the manufacturing process, the adhesive 2 is dropped into the concave stepped portion 13B, so that the adhesive 2 is more than a plurality. It is possible to prevent or suppress the flow in the direction of the terminal portion 11 .
[0031]
When forming a concave stepped portion on the insulating substrate, it is necessary to consider that the strength of the insulating substrate does not become insufficient due to the presence of the stepped portion. Therefore, the means for forming the concave step portion is suitable when the thickness of the insulating substrate is relatively large or when the insulating substrate is made of a material having excellent strength. In addition, when the material of the insulating substrate is made of glass epoxy resin, for example, a concave step can be easily formed by pressing an appropriate jig against the surface of the insulating substrate. Can be. The concave step portion 13B has a configuration in which a part of the resist layer 12 is present in a concave groove formed on the surface of the insulating substrate 1B. However, in the present invention, instead of this, for example, a groove may be formed only in the resist layer 12 without forming a groove in the insulating substrate 1B itself, and this may be a concave stepped portion .
[0032]
In the semiconductor device Ac shown in FIG. 10, the plurality of terminal portions 11 of the insulating substrate 1C are provided only on the left and right sides of the semiconductor chip 3C, and a protrusion is provided between the plurality of terminal portions 11 and the semiconductor chip 3C. Or concave step portions 13C and 13C are provided in a linear form in plan view. In the semiconductor device Ac, even if the adhesive 2 spreads in all directions, the adhesive 2 can be prevented from flowing into the surfaces of the plurality of terminal portions 11 by the step portions 13C and 13C. Further, the adhesive spreading in the direction of the arrow N2 in the figure cannot be blocked by the steps 13C and 13C, but there is no particular problem even if the adhesive spreads relatively large in that direction. As described above, the step portion in the present invention does not necessarily have to be provided so as to surround the periphery of the bonding portion of the semiconductor chip. In short, the stepped portion only needs to be provided at least between the bonding portion of the semiconductor chip and the terminal portion of the insulating substrate. Of course, the specific number of steps is not limited.
[0033]
The present invention is not limited to the embodiments described above. As the insulating substrate in the present gun invention, a concept excludes a substrate made of metal or other conductive member such as a lead frame, as long as it is made of a insulating member, its concrete material is also limited particularly is not.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a reference example of a semiconductor device according to the present invention.
2 is a plan perspective view of the semiconductor device shown in FIG. 1; FIG.
FIG. 3 is a perspective view of relevant parts showing an example of a film substrate for forming an insulating substrate.
FIG. 4 is a cross-sectional view of a main part of a film substrate having a resist layer.
FIG. 5 is a fragmentary cross-sectional view showing a process of bonding a semiconductor chip on a film substrate.
6 is a plan view of the main part of FIG. 5. FIG.
FIG. 7 is a cross-sectional view showing an embodiment of a semiconductor device according to the present invention.
8 is a main part schematic perspective view showing a conductive wiring pattern of an insulating substrate used in the semiconductor device shown in FIG. 7;
FIG. 9 is a cross-sectional view showing another reference example of the semiconductor device according to the present invention.
FIG. 10 is a plan perspective view showing another reference example of a semiconductor device according to the present invention.
FIG. 11 is a cross-sectional view of main parts showing an example of a conventional semiconductor device.
[Explanation of symbols]
1 Insulating substrate 1a Film substrate (insulating substrate)
2 Adhesive 3, 3C Semiconductor Chip 4 Sealing Resin 5 Solder Bump 11 Terminal 12 Resist Layer 13, 13A-13C Step 30 Electrode W Wire A, Aa-Ac Semiconductor Device

Claims (1)

表面に複数条の導電配線が形成されるとともに、これら導電配線の一端部からなる複数の端子部が外周縁に沿って形成され、かつ、上記複数条の導電配線のうち上記各端子部以外の領域を覆うように略全面にレジスト層が設けられた絶縁基板と、この絶縁基板の表面上における上記複数の端子部によって囲まれる領域における上記レジスト層上に接着剤を介して接着された半導体チップとを具備しており、かつ上記半導体チップの電極と上記絶縁基板上の上記端子部とはワイヤを介して接続されている、半導体装置であって、
上記レジスト層のうち、上記半導体チップの接着箇所と上記端子部との間に形成した上記導電配線の蛇行部を覆う部位は、上記接着剤がその未硬化状態において上記絶縁基板上の上記端子部に流れ込むことを防止可能な凸状の段部を形成していることを特徴とする、半導体装置。A plurality of conductive wirings are formed on the surface, and a plurality of terminal portions composed of one end portions of these conductive wirings are formed along the outer peripheral edge, and of the plurality of conductive wirings other than the terminal portions. An insulating substrate provided with a resist layer on substantially the entire surface so as to cover the region, and a semiconductor chip bonded to the resist layer in a region surrounded by the plurality of terminal portions on the surface of the insulating substrate via an adhesive And an electrode of the semiconductor chip and the terminal portion on the insulating substrate are connected via a wire,
The portion of the resist layer that covers the meandering portion of the conductive wiring formed between the bonding portion of the semiconductor chip and the terminal portion is the terminal portion on the insulating substrate when the adhesive is in an uncured state. characterized in that it forms a convex stepped portion capable of preventing from flowing into the semiconductor device.
JP24797998A 1998-09-02 1998-09-02 Semiconductor device Expired - Fee Related JP3923661B2 (en)

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JP4308608B2 (en) 2003-08-28 2009-08-05 株式会社ルネサステクノロジ Semiconductor device
US6992380B2 (en) * 2003-08-29 2006-01-31 Texas Instruments Incorporated Package for semiconductor device having a device-supporting polymeric material covering a solder ball array area
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