JP3989816B2 - Pattern synchronous pull-in device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a bit error detection device, and more specifically, compares a pseudo-random pattern sent from a transmission device to a reception device and a reference pseudo-random pattern generated by a pseudo-random pattern generation circuit in the reception device. The present invention relates to a pseudo random pattern synchronous pull-in apparatus and method.
[0002]
[Prior art]
A pseudo-random pattern (Pseudo Random Bit Sequence pattern, hereinafter referred to as “PRBS pattern”) is often used for testing communication devices, transmission apparatuses, transmission lines, and the like. In a test apparatus that performs a test by transmitting and receiving a PRBS pattern, the following procedure is taken. In the receiving apparatus, (1) the received signal is synchronized with the internally generated reference signal, (2) the received data is compared with the reference signal, (3) the number of erroneous bits is counted, (4) The received data is evaluated.
[0003]
That is, in this type of test, the PRBS pattern generated in the transmission device is received by the reception device via the device or the transmission device, and the reference PRBS pattern generated by the PRBS pattern generation circuit in the reception device To be compared. The PRBS pattern generated in the transmitting apparatus is compared with a reference PRBS pattern output (generated) by the PRBS pattern generating circuit in the receiving apparatus, and the number of occurrences of bit errors in the received data is counted and output.
[0004]
An example of a conventional error measurement circuit will be described with reference to FIG.
FIG. 6 is a block diagram of an error measurement circuit in the prior art.
The synchronization detection circuit 3 performs synchronization determination between the received data and the reference data output from the PRBS pattern generation circuit 1 based on the detection pulse of the comparison circuit 2.
When correct data without error is input to the received data, the PRBS pattern generation circuit 1 outputs a reference PRBS pattern with the received data as an initial value. The comparison circuit 2 compares the next input reception data with the reference data output from the PRBS pattern generation circuit 1. The synchronization detection circuit 3 detects synchronization based on the comparison result.
[0005]
A conventional technique of an error measurement circuit that counts the number of occurrences of bit errors in received data when a PRBS pattern is generated when synchronization is detected will be described with reference to FIG.
In FIG. 6, 1 is a PRBS pattern generating circuit for outputting reference data in the receiving apparatus, 2 is a comparison circuit, 3 is a synchronization detection circuit for determining the synchronization between the reference data and the received data, 4 is a count circuit, and 5 is PRBS. In the pattern generation circuit, a selector circuit for loading an initial value, 6 is an FF (Flip Flop), and 7 is a Pseudo-random Noise (hereinafter referred to as “PN”) arithmetic circuit for generating a PRBS pattern.
[0006]
In FIG. 6, the reception data input by the receiving device is input to the PRBS pattern generation circuit 1 and the comparison circuit 2. The PRBS pattern generation circuit 1 outputs a PRBS pattern serving as reference data based on the last a bits of the received data until synchronization is detected by the synchronization detection circuit 3. After the synchronization is detected by the synchronization detection circuit 3, a PRBS pattern serving as the next reference data is output based on the generated reference data. Here, n is the number of bits for parallel processing, a is the number of bits for generating a PRBS pattern, and a ≦ n.
[0007]
The comparison circuit 2 compares the input received data with the reference data output from the PRBS pattern generation circuit 1, and outputs a detection pulse whenever they differ. The count circuit 4 counts the number of pulses and outputs a count value.
The PRBS pattern generation circuit 1 outputs a PRBS pattern that becomes the next reference data based on the reference data generated until synchronization is lost. If there is an error in the received data, since the received data is different from the reference PRBS pattern, the comparison circuit 2 outputs a pulse at that time. The count circuit 4 counts and outputs this pulse.
[0008]
[Patent Document 1]
JP-A-9-46323
[0009]
[Problems to be solved by the invention]
In the conventional error measurement circuit, if there is a lot of errors in the received data in a state where synchronization is not detected, the PRBS pattern generation circuit 1 outputs a PRBS pattern generated based on the erroneous received data. There was a problem that I could not.
Thus, in the conventional error measurement circuit, the received data must not have an incorrect pattern until synchronization is detected. At least, erroneous data should not continue to exist in the data position used for PRBS pattern generation. When wrong received data is received, the PRBS pattern generation circuit 1 is based on the wrong data, and therefore, there is a problem that the PRBS pattern synchronized with the received data cannot be output and the synchronization cannot be detected. It was.
[0010]
Therefore, an object of the present invention is to provide a PRBS pattern synchronization pull-in apparatus and method that can detect synchronization and accurately count bit errors even when there are many errors in received data.
[0011]
[Means for Solving the Problems]
The pattern synchronization pull-in device according to the present invention inputs partial data extracted from received data, and generates a plurality of pattern generation circuits based on the partial data.
A plurality of pattern data generated by the plurality of pattern generation circuits, the received data is input, a comparison unit that compares each of the plurality of pattern data with the received data;
A synchronization detection unit that inputs a comparison result compared by the comparison unit and detects the pattern data synchronized with the received data using the comparison result;
It is characterized by providing.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
The PRBS pattern synchronization acquisition method and the PRBS pattern synchronization acquisition device according to the present invention are characterized by providing a plurality (m) of PRBS pattern generation circuits having different positions for receiving n-parallel received data when detecting synchronization. By this means, means for avoiding errors in received data and enabling synchronization detection are provided. “N-parallel received data” means “n-bit parallel received data”, and the number of bits processed at one time is n bits.
[0013]
FIG. 1 is a conceptual explanatory diagram using four PRBS pattern generation circuits (m = 4) as an example of the present invention.
In FIG. 1, 8, 9, 10, and 11 are PRBS pattern generation circuits. 8, 9, 10, and 11 generate the next PRBS pattern by using the PRBS pattern generated by themselves as an input in the normal operation state, and generate the next PRBS pattern by receiving the received data in the out-of-synchronization state. The four PRBS pattern generation circuits have different bit positions when a-bits of n parallel received data are input.
[0014]
When receiving received data in units of n bits using m PRBS pattern generation circuits, m partial data (a bits) are extracted from the received data as follows.
Of the received data, n bits are defined (hereinafter referred to as “n-bit received data”), and m partial data (a bits) are extracted from different positions of the n-bit received data.
Each of the m PRBS pattern generation circuits receives different partial data (a bit) and generates a PRBS pattern (pattern data) using the partial data. In the example of FIG. 1, the PRBS pattern is shown to be b bits. The b bits may be the same as the n bits or the number of bits smaller than the n bits. b may take a numerical value in the range of b ≦ n.
[0015]
FIG. 2 shows the relationship among received data, n-parallel received data (nbit), and a-bit (abbit) of the n-parallel received data.
Each portion of the received data indicated as nbit is the number of PRBS data generated at one time, and at the same time, the number of bits to be compared with the received data.
The portion shown as “bit” shows an example of a plurality of a bits input to the PRBS pattern generation circuits 8, 9, 10, and 11 among the n bits. m corresponds to the number of PRBS pattern generation circuits, and in the example of FIGS. 1 and 2, the case where m is 4 is shown. The four a bits shown in FIG. 2 indicate partial data of a bits taken from different positions, but this does not exclude the fact that they are the same.
FIG. 2 shows two examples in which partial data of a bits different from each other are received from n bits of received data. Once the position of the a bit to be input to the PRBS pattern generation circuit is determined, it is not changed thereafter.
Further, although not shown in FIG. 2, the a bit input to each of the PRBS pattern generation circuits 8, 9, 10 and 11 is an n bit divided into m (m is the number of PRBS pattern generation circuits). You may enter one.
Further, a part of four (m) a-bit partial data may overlap.
[0016]
A comparison circuit 12 compares the PRBS pattern generated by the four PRBS pattern generation circuits with the received data.
Reference numeral 13 denotes a synchronization detection circuit, which detects synchronization based on the previous comparison result.
[0017]
When received data without error is input, the PRBS pattern generation circuits 8, 9, 10, and 11 generate correct PRBS patterns. When received data including an error is input, the PRBS pattern generation circuits 8, 9, 10, and 11 input different bit positions, and thus generate a PRBS pattern based on the correct received data portion. There may be a PRBS pattern generation circuit. Suppose that the PRBS pattern generation circuit 8, 10 , 11 and the received data part without error is input to the PRBS pattern generation circuit 9, the synchronization detection circuit compares the PRBS pattern generated by the PRBS pattern generation circuit 9 with the received data. Synchronization detection is possible based on the result.
[0018]
The internal configuration of the PRBS pattern generation circuit is the same as that of the pattern generation circuit 1 of FIG. Therefore, it includes the components of the selector circuit, FF, and PN arithmetic circuit. The PRBS pattern generation circuits 8, 9, 10, and 11 select either the PRBS pattern (normal operation state) or the received data (out-of-synchronization state) generated by the selector circuit based on the selected result. The next PRBS pattern is generated.
“Correct data” refers to data sent to the receiving device without error (without error) when data is transmitted from the transmitting device to the receiving device.
The “normal operation state” is a state in which synchronization is established. Specifically, the next PRBS is based on the state in which the received data and the generated PRBS pattern data are synchronized, or the data that the PRBS pattern generation circuit has generated (generated). A state where pattern data is being generated.
The out-of-synchronization state refers to a state where the received data and the generated PRBS pattern data are not synchronized. Specifically, it means a state in which the PRBS pattern generation circuit is generating the next PRBS pattern data based on the received data.
[0019]
Here, m = 4 has been described as an example, but it goes without saying that the object of the present invention is similarly achieved when m is other than 4.
[0020]
As described above, the pattern synchronization pull-in device (PRBS pattern sync pull-in device) extracts partial data (a bit) extracted from received data (n parallel received data of received data, that is, n-bit received data). A plurality of pattern generation circuits 8 to 11 for generating pattern data (PRBS pattern data, b bits (b ≦ n)) and a plurality of pattern generation circuits 8 to 11 are input based on the partial data. A comparison circuit (comparison unit) 12 that acquires a plurality of pattern data, inputs reception data (n bits), compares each of the plurality of pattern data with the reception data (n bits), and a comparison that the comparison circuit 12 compares A synchronization detection circuit that inputs the result and detects the pattern data synchronized with the received data using the comparison result. Explained that anda (synchronization detection unit) 13. The comparison circuit 12 is an example of a comparison unit, and the synchronization detection circuit 13 is an example of a synchronization detection unit.
[0021]
Further, the pattern synchronization pull-in apparatus and method receives received data, extracts a plurality of different partial data from the input received data, and generates the plurality of pattern data based on each of the extracted plurality of partial data. Explaining that each of a plurality of generated pattern data is compared with the received data, and at least one pattern data synchronized with the received data is detected using a comparison result of the comparison. did.
[0022]
Embodiment 1 FIG.
Hereinafter, specific embodiments according to the present invention will be described in detail with reference to the drawings.
FIG. 3 shows an embodiment of a bit error measurement circuit to which the present invention is applied. FIG. 3 shows an example in which four PRBS pattern generation circuits (m = 4) are used and the number of PRBS pattern generation bits (b) of each of the four PRBS pattern generation circuits is n (b = n). .
In FIG. 3, the bit error measurement circuit includes a PRBS pattern generation circuit 8, a PRBS pattern generation circuit 9, a PRBS pattern generation circuit 10, a PRBS pattern generation circuit 11, a comparison circuit 12, a synchronization detection circuit 13, a count circuit 14, and a selector circuit 15. Consists of.
[0023]
The PRBS pattern generation circuit 8, the PRBS pattern generation circuit 9, the PRBS pattern generation circuit 10, and the PRBS pattern generation circuit 11 convert a bit of n bits (n parallel reception data) of received data into partial data in an out-of-synchronization state. And the next n parallel PRBS pattern is generated (output) based on the value (the a-bit partial data). Here, the bit position of the received data taken in by each PRBS pattern generation circuit is changed. When the received data is each PRBS pattern having no error, the PRBS pattern generated by each PRBS pattern generation circuit is the same. . That is, as shown in FIG. 2, when any a bit (consecutive a bit) partial data of n bits (n parallel) of the received data is input to the PRBS pattern generation circuit (any of 8 to 11). The same PRBS pattern will be generated.
[0024]
In the synchronized state, the PRBS pattern generation circuit 8, the PRBS pattern generation circuit 9, the PRBS pattern generation circuit 10, and the PRBS pattern generation circuit 11 continuously generate the PRBS pattern based on the PRBS pattern generated by itself.
[0025]
The comparison circuit 12 compares the PRBS pattern input from each PRBS pattern generation circuit 8, 9, 10, 11 with the received data for each corresponding bit, and outputs the result. Specifically, the comparison circuit 121 in the comparison circuit 12 compares the PRBS pattern input from the PRBS pattern generation circuit 8 with the received data. The comparison circuit 122 in the comparison circuit 12 compares the PRBS pattern input from the PRBS pattern generation circuit 10 with the received data. The comparison circuit 123 in the comparison circuit 12 inputs the PRBS pattern from the PRBS pattern generation circuit 11. The comparison circuit 124 in the comparison circuit 12 compares the received data and the received data independently for each corresponding bit and outputs the result.
[0026]
The synchronization detection circuit 13 detects whether the outputs of the four PRBS pattern generation circuits 8, 9, 10, and 11 are synchronized with the received data based on the output of the comparison circuit 12. Specifically, the synchronization detection circuit 131 in the synchronization detection circuit 13 synchronizes the PRBS pattern generation circuit 8 and the received data, and the synchronization detection circuit in the synchronization detection circuit 13 synchronizes the PRBS pattern generation circuit 9 and the reception data. 132, the synchronization detection circuit 133 in the synchronization detection circuit 13 synchronizes the PRBS pattern generation circuit 10 and the received data, and the synchronization detection circuit 134 in the synchronization detection circuit 13 synchronizes the PRBS pattern generation circuit 11 and the reception data. , Synchronous detection is performed independently.
The result detected by the synchronization detection circuit 13 is notified to the PRBS pattern generation circuits 8, 9, 10, and 11.
[0027]
When the PRBS pattern generation circuits 8, 9, 10, and 11 are notified of the synchronization state from the synchronization detection circuit 13, the PRBS pattern generation circuits 8, 9, 10, and 11 generate the next PRBS pattern using the PRBS pattern generated by themselves. Whether or not to use its own PRBS pattern is selected by the selector circuit 5 shown in FIG. The selector circuit 5 selects either its own PRBS pattern or a-bit partial data based on the notification from the synchronization detection circuit 13.
[0028]
The selector circuit 15 selects the output of the comparison circuit 12 corresponding to the output of the PRBS pattern generation circuit if there is a synchronized PRBS pattern generation circuit among the PRBS pattern generation circuits 8, 9, 10, and 11. Output. The selector circuit 15 maintains the selected state until the selected PRBS pattern generation circuit is out of synchronization. If two or more PRBS pattern generation circuits are synchronized, priority processing is performed and one is selected.
The count circuit 14 counts errors in the synchronization state selected by the selector circuit 15.
[0029]
As described above, in this embodiment, the pattern synchronization pull-in device includes a plurality of pattern generation circuits (PRBS pattern generation circuits), and the plurality of pattern generation circuits as an example of the comparison circuit (comparison unit) 12. An example having a plurality of comparison circuits 121 to 124 corresponding to each of them, and having a plurality of synchronization detection circuits 131 to 134 corresponding to each of the plurality of comparison circuits 121 to 124 as an example of the synchronization detection circuit (synchronization detection unit) 13. Indicated.
Each of the plurality of pattern generation circuits 8 to 11 outputs the generated pattern data to each of the corresponding comparison circuits 121 to 124, and each of the plurality of comparison circuits 121 to 124 includes any one of the plurality of pattern generation circuits 8 to 11. The pattern data is input from one of them, and the comparison result is output to the corresponding synchronization detection circuits 131-134.
Each of the plurality of synchronization detection circuits 131 to 134 receives the comparison result from any one of the plurality of comparison circuits 121 to 124, and uses the comparison result to synchronize the received pattern data with the received data. It was explained that it is characterized by detecting.
[0030]
As described above, in the out-of-synchronization state, the PRBS pattern is generated by capturing the initial pattern at a plurality of positions from the received data having an error, thereby enabling detection of synchronization while avoiding error bits.
[0031]
As described above, in this embodiment, a pseudo-random pattern generation circuit (PRBS pattern generation circuit 8, 9, 10, 11) that takes in different bit positions of parallel received data and generates pseudo-random pattern data when out of synchronization. A comparison circuit 12 that compares the pseudo-random pattern data generated by the pseudo-random pattern generation circuit with the received data, and a synchronization detection circuit 13 that detects the synchronization between the pseudo-random pattern generation circuit and the reception data. In a pseudo random pattern synchronization pull-in device, a pseudo random pattern synchronization pull-in device comprising a plurality of pseudo random pattern generation circuits in which bit positions of data fetched from received data are changed in order to synchronize with received data explained.
[0032]
Embodiment 2. FIG.
FIG. 4 shows an embodiment of a bit error measurement circuit to which the present invention is applied. FIG. 4 shows an example in which four PRBS pattern generation circuits (m = 4) are used and the number of PRBS pattern generation bits of each of the four PRBS pattern generation circuits is n / 4 (b = n / 4). Yes.
In FIG. 4, the bit error measurement circuit includes a PRBS pattern generation circuit 8b, a PRBS pattern generation circuit 9b, a PRBS pattern generation circuit 10b, a PRBS pattern generation circuit 11b, a comparison circuit 12b, a synchronization detection circuit 13b, and a count circuit 14. The
[0033]
The PRBS pattern generation circuit 8b, the PRBS pattern generation circuit 9b, the PRBS pattern generation circuit 10b, and the PRBS pattern generation circuit 11b perform the following operations when out of synchronization.
The PRBS pattern generation circuit 8b, the PRBS pattern generation circuit 9b, the PRBS pattern generation circuit 10b, and the PRBS pattern generation circuit 11b each take in a bit of the received data (n / 4 bits) divided into four, and set the value. A corresponding n / 4-bit PRBS pattern in the next n parallels is generated (output).
[0034]
FIG. 5 is a diagram showing an example of abbit partial data input to the PRBS pattern generation circuit. The PRBS pattern generation circuit 8b takes in n / 4 bits from the MSB side. Similarly, the PRBS pattern generation circuit 9b, the PRBS pattern generation circuit 10b, and the PRBS pattern generation circuit 11b each take in n / 4 bits. The bit position may be a bit arrangement at any position within the range of n / 4 bits. However, in the example of FIG. 5, four bits do not overlap. This is because the abit is extracted from each range divided into n / 4. Also, the position of the bit is not changed once it is determined. Also, the bit partial data may be n / 4-bit received data itself (all). a can take a value in a range of a ≦ (n / m).
[0035]
At this time, the PRBS pattern generation circuit 8b, the PRBS pattern generation circuit 9b, the PRBS pattern generation circuit 10b, and the PRBS pattern generation circuit 11b take in data from other PRBS pattern generation circuits as shown in FIG. Specifically, the PRBS pattern generation circuit 8b includes the circuit 1 data 1 generated by the PRBS pattern generation circuit 9b, the circuit 1 data 2 generated by the PRBS pattern generation circuit 10b, and the PRBS pattern generation circuit 11b. The circuit 1 data 3 is fetched. However, in the out-of-synchronization state, the PRBS pattern generation circuit 8b uses the input abit, but does not use the circuit 1 data 1, the circuit 1 data 2, and the circuit 1 data 3.
[0036]
The PRBS pattern generation circuit 8b, the PRBS pattern generation circuit 9b, the PRBS pattern generation circuit 10b, and the PRBS pattern generation circuit 11b use the captured abit to generate an n / 4 PRBS pattern and other PRBS pattern generation circuit data (PRBS pattern). In the case of the generation circuit 8b, circuit 2 data 1, circuit 3 data 1, and circuit 4 data 1) are generated, and n-bit data is output together with the n / 4 PRBS pattern. Of the output data, the generated n / 4 PRBS pattern is input to the comparison circuit 12b.
[0037]
Also, it is determined whether the PRBS pattern generated by itself when transitioning from the out-of-synchronization state to the synchronization state is used as an initial value, or whether an initial value pattern generated by another PRBS pattern generation circuit is used as an initial value. Thereafter, a PRBS pattern is generated using the determined pattern (either the self-generated PRBS pattern or the initial value pattern generated by another PRBS pattern generation circuit), and then the self-generated PRBS. A PRBS pattern is continuously generated based on the pattern. Whether a PRBS pattern generated by itself or an initial value pattern generated by another PRBS pattern generation circuit is selected is output from a circuit capable of detecting synchronization based on the result of the synchronization detection circuit 13b. Select data.
[0038]
The comparison circuit 12b compares the PRBS pattern (n / 4 bit data) input from each PRBS pattern generation circuit with the received data (n / 4 bit of n parallel received data) for each corresponding bit. , Output the result.
Specifically, the comparison circuit 121 in the comparison circuit 12b compares the PRBS pattern input from the PRBS pattern generation circuit 8b with the MSB (Most Significant Bit) side data of the received data divided into four equal parts. The comparison circuit 122 in the comparison circuit 12b compares the PRBS pattern input from the circuit 9b with the second data from the MSB side of the received data divided into four equal parts and the PRBS pattern input from the PRBS pattern generation circuit 10b. The comparison circuit 123 in the comparison circuit 12b compares the quarterly received data with the third data from the MSB side. The comparison circuit 123 in the comparison circuit 12b compares the PRBS pattern inputted from the PRBS pattern generation circuit 11b with the LSB of the reception data divided into four. Ratio to (Least Significant Bit) side data The comparison circuit 124 inside the comparison circuit 12b compares each bit independently and outputs the result.
[0039]
The synchronization detection circuit 13b detects whether the outputs of the four PRBS pattern generation circuits are synchronized with the reception data based on the output of the comparison circuit 12b. Specifically, the synchronization detection circuit 131 in the synchronization detection circuit 13b synchronizes the PRBS pattern generation circuit 8b and the received data, and the synchronization detection circuit in the synchronization detection circuit 13b synchronizes the PRBS pattern generation circuit 9b and the reception data. 132, the synchronization detection circuit 133 in the synchronization detection circuit 13b synchronizes the PRBS pattern generation circuit 10b and the received data, and the synchronization detection circuit 134 in the synchronization detection circuit 13b synchronizes the PRBS pattern generation circuit 11b and the reception data. , Synchronous detection is performed independently.
[0040]
If there is a synchronized PRBS pattern generation circuit, the synchronization control circuit 135 in the synchronization detection circuit 13b indicates a synchronization state for the PRBS pattern generation circuit, and a synchronization state for other PRBS pattern generation circuits. At the same time, an instruction to select the corresponding pattern as an initial value is output from the output of the PRBS pattern generation circuit in the synchronized state. Further, when the synchronization control circuit 135 does not detect the synchronization state, the synchronization control circuit 135 outputs an instruction to select the partial data (a bit) extracted from the received data as an initial value. The initial value is data used as a reference when generating PRBS pattern data.
The synchronization control circuit 135 notifies the PRBS pattern generation circuit of the selected initial value (outputs an instruction).
If two or more PRBS pattern generation circuits are synchronized, the synchronization control circuit 135 responds from the PRBS pattern generation circuit output in synchronization with the out-of-synchronization PRBS pattern generation circuit. An instruction to select a pattern as an initial value is output. For which PRBS pattern generation circuit output is to be used, priority processing is performed and one is selected.
[0041]
The count circuit 14 outputs an error by counting the output of the comparison circuit 12b.
[0042]
The PRBS pattern generation circuit selects an initial value based on the notification (instruction) of the synchronization control circuit 135, and generates the next PRBS pattern data using the selected initial value. As described with reference to FIG. 6, the PRBS pattern generation circuit has a selector circuit 5 inside, and the selector circuit 5 selects an initial value.
That is, the PRBS pattern generation circuit, based on the notification (instruction) from the synchronization control circuit 135, as an initial value, the PRBS pattern (pattern data) generated by itself and the PRBS pattern generated by another pattern generation circuit And the partial data are used to generate the next PRBS pattern (pattern data).
[0043]
FIG. 4 shows an example in which the comparison circuit 12b includes four (m) comparison circuits 121 to 124. However, this may be a single comparison circuit. . The comparison circuit 12b may be a circuit that can compare n bits (m times n / m).
Similarly, although the example in which the synchronization detection circuit 13b includes four (m) synchronization detection circuits of the synchronization detection circuits 131 to 134 is shown, it may be a single comparison circuit.
In the example of FIG. 4, unlike the example of FIG. 3, the synchronization control circuit 135 is an essential component. The synchronization control circuit 135 instructs which data is to be the initial value by the PRBS pattern generation circuit.
[0044]
As described above, in this embodiment, the pattern synchronization pull-in device includes a plurality of PRBS pattern generation circuits (pattern generation circuits) 8b to 11b, a comparison circuit (comparison unit) 12b, and a synchronization detection circuit (synchronization detection unit). 135, and further, selecting one of the received data and the pattern data generated by the pattern generation circuit detected by the synchronization detection unit as an initial value, and selecting the selected initial value for each of the plurality of pattern generation circuits. It has been described that the apparatus includes a synchronization control circuit (synchronization control unit) 135 for notifying the device.
Each of the plurality of PRBS pattern generation circuits 8b to 11b receives the pattern data generated by itself, the pattern data generated by the other PRBS pattern generation circuits 8b to 11b, and the partial data. Based on the initial value notified by the synchronization control circuit 135, the pattern data generated by itself, the pattern data generated by another pattern generation circuit, and the partial data are used to Pattern data is generated.
[0045]
Further, assuming that the parallel number of the received data is n and the number of the plurality of pattern generating circuits is m, n is equally divided by m, and each of the received data having a length of n / m divided equally is the plurality of patterns. Each of the pattern generation circuits 8b to 11b is assigned to each of the generation circuits, and generates the pattern data of n / m length using the received data of n / m length.
[0046]
In this way, in an out-of-synchronization state, a PRBS pattern is generated by capturing as an initial pattern at a plurality of positions from erroneous received data, and a synchronized PRBS pattern generating circuit is output to an unsynchronized PRBS pattern generating circuit. By capturing the PRBS pattern to be used as the initial pattern, it becomes possible to detect synchronization while avoiding error bits.
[0047]
As described above, in this embodiment, in the pseudo random pattern synchronization pull-in device, in order to synchronize with the received data, the bit position of the data fetched from the received data is changed and a plurality of prepared pseudo random pattern generating circuits are initialized. A pseudo-random pattern synchronization pull-in device having a plurality of pseudo-random pattern generation circuits capable of capturing data and initial data from other pseudo-random pattern generation circuits has been described.
[0048]
Embodiment 3 FIG.
1, 3, and 4, the PRBS pattern generation circuit, the comparison circuit, the synchronization detection circuit, the count circuit, the selector circuit, the synchronization control circuit, and the like are illustrated. However, the circuit is not limited to the circuit. Other than the circuit, for example, software, firmware, or the like may be used. Therefore, the PRBS pattern generation circuit is a PRBS pattern generation unit, the comparison circuit is a comparison unit, the synchronization detection circuit is a synchronization detection unit, the count circuit is a counter unit, the selector circuit is a selector unit, and the synchronization control circuit is a synchronization control unit. Can be shown as
[0049]
Embodiment 4 FIG.
In the first to third embodiments, the PRBS synchronization pull-in apparatus and method using the PRBS pattern generation circuit have been described. However, pattern data other than the PRBS pattern may be used.
In addition, the “retraction” of the PRBS pattern synchronization pull-in device is used for pattern synchronization. Go Refers to movement.
[0050]
【The invention's effect】
According to the pattern synchronization pulling apparatus and method of the present invention, even when there are many errors in the received data, it is possible to perform synchronization detection while avoiding error bits and accurately count bit errors.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a principle according to an embodiment of the present invention.
FIG. 2 is a diagram for explaining a relationship between received data nbit data and abit data.
FIG. 3 is a block diagram showing Embodiment 1 of an error measurement circuit according to the present invention.
FIG. 4 is a block diagram showing Embodiment 2 of an error measurement circuit according to the present invention.
FIG. 5 is a diagram showing an example of an bit input to a PRBS pattern generation circuit.
FIG. 6 is a block diagram showing an example of an error measurement circuit according to the prior art.
[Explanation of symbols]
1 PRBS pattern generation circuit, 2 comparison circuit, 3 synchronization detection circuit, 4 count circuit, 5 selector circuit, 6 FF (Flip Flop), 7 PN operation circuit, 8, 8b PRBS pattern generation circuit, 9, 9b PRBS pattern generation circuit 10, 10b PRBS pattern generation circuit, 11, 11b PRBS pattern generation circuit, 12, 12b comparison circuit, 13, 13b synchronization detection circuit, 14 count circuit, 15 selector circuit, 121 comparison circuit, 122 comparison circuit, 123 comparison circuit, 124 comparison circuit, 131 synchronization detection circuit, 132 synchronization detection circuit, 133 synchronization detection circuit, 134 synchronization detection circuit, 135 synchronization control circuit

Claims (5)

Enter the plurality of partial data extracted from the received data, based on the plurality of partial data, and a plurality of pattern generating circuit for generating a pattern data corresponding to each of a plurality of partial data,
The plurality of pattern data generated by the plurality of pattern generation circuits is acquired, the reception data and new reception data are sequentially input, and the plurality of pattern data and the reception data corresponding to the plurality of pattern data, respectively. A comparison unit that compares the partial data of
A comparison detection unit that inputs a comparison result compared by the comparison unit and detects the pattern data that is synchronized with the received data using the comparison result ; and
The comparison unit includes a plurality of comparison circuits corresponding to the plurality of pattern generation circuits,
The synchronization detection unit includes a plurality of synchronization detection circuits corresponding to the plurality of comparison circuits,
Each of the plurality of pattern generation circuits outputs the generated pattern data to a corresponding comparison circuit,
Each of the plurality of comparison circuits receives the pattern data from any one of the plurality of pattern generation circuits, and outputs the comparison result to a corresponding synchronization detection circuit.
Each of the plurality of synchronization detection circuits receives the comparison result from any one of the plurality of comparison circuits, and the received data and the pattern data are synchronized or synchronized using the comparison result. Detect whether or not, output the detected detection results,
Each of the plurality of pattern generation circuits inputs a detection result from a corresponding synchronization detection circuit among the plurality of synchronization detection circuits,
If the input detection results indicate that they are synchronized, generate new pattern data using the pattern data that you have generated,
When the input detection result indicates that they are not synchronized, corresponding partial data is input from new received data, and new pattern data is generated based on the partial data. Pattern synchronous pull-in device. The received data has a plurality of bit information,
2. The pattern synchronous pull-in device according to claim 1, wherein the plurality of partial data input by each of the plurality of pattern generation circuits is extracted from different bit positions among the plurality of bit information of the received data . The pattern synchronization pull-in device further selects any one of the partial data and the pattern data generated by the pattern generation circuit detected by the synchronization detection unit as an initial value, and selects the selected initial value as the plurality of patterns. It has a synchronization control unit that notifies each generation circuit,
Each of the plurality of pattern generation circuits inputs pattern data generated by itself, pattern data generated by another pattern generation circuit, and the partial data, and is based on an initial value notified by the synchronization control unit. The next pattern data is generated using any one of the pattern data generated by itself, the pattern data generated by another pattern generation circuit, and the partial data. Item 3. The pattern synchronous pull-in device according to either item 1 or 2 . In the pattern synchronization pull-in device, when the length of the received data is n and the number of the plurality of pattern generating circuits is m, n is equally divided by m, and each of the received data having a length of n / m is equally divided. Is assigned to each of the plurality of pattern generation circuits,
The plurality of pattern generating circuit pattern synchronizing according to 3 claim 1, characterized in that to generate the pattern data of the length of n / m by using the received data of the length of the n / m Retraction device. The plurality of pattern generating section, a pattern pull-device according to claim 1, wherein the generating the pseudo-random pattern 4 one.

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