JP3961651B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device using a ferroelectric capacitor.
[0002]
[Prior art]
In recent years, a nonvolatile memory (FRAM: Ferroelectric RAM) using a ferroelectric capacitor (Ferroelectric Capacitor) has attracted attention as one of semiconductor memories. This FRAM is non-volatile and has the advantages such as the number of rewrites of 10 12, read and write times of DRAM, low voltage operation of 3V to 5V, etc., and thus may replace the entire memory market. At the current academic level, 1 Mbit FRAM has been announced (H. Koike et al., 1996 IEEE International Solid-State Circuit Conference Digest of Technical Paper, pp. 368-369, Feb, 1996).
[0003]
The cell size of FRAM cells has been reduced by the two-transistor + 2-capacitor configuration from the initial SRAM + Shadow Memory configuration, and the simplification and miniaturization of the cell configuration with the era as in the development of DRAM. FIG. 74 (a) shows a conventional DRAM 1-transistor + 1-capacitor memory cell, and FIG. 74 (b) shows a conventional FRAM 1-transistor + 1-capacitor memory cell. Obviously, the conventional FRAM 1-transistor + 1-capacitor memory cell is no longer the same as the 1-transistor + 1-capacitor configuration in which the DRAM transistor and capacitor are connected in series.
[0004]
A different point is that a normal capacitor is used as a capacitor in the DRAM as shown in the voltage-accumulated charge relationship in FIG. 75A, whereas a voltage-polarization amount relationship in FIG. 75B is used in the FRAM. As described above, a ferroelectric material having a hysteresis characteristic is used. Therefore, the cell array configuration is the same as that of the DRAM, a folded BL configuration as shown in FIG. 74C is adopted, and the minimum cell size is 2F × 4F = 8F.²It is difficult to make it smaller. Here, F indicates a minimum processing dimension.
[0005]
Forcibly 4F²As an example of realizing the size, there are examples using vertical transistors and vertical TFTs (Thin Film Transistor) (K. Sunouchi et al, 1998 IEEE IEDM Digest of Technical Paper, pp. 23-26, Dec, 1989). Exists but is very difficult to manufacture. In addition, cell transistors are connected in series, and a capacitor is connected between them and between PL and approximately 4F.²(N. cell) has also been proposed (T. Hasegawa et al, 1993 IEEE International Solid-State Circuit Conference Digest of Technical Paper, pp. 46-47, Feb, 1993). Not very versatile.
[0006]
Thus, in the conventional FRAM cell, (1) small 4F²There is a first problem that the three points of (2) a memory cell having a size, (2) a planar transistor that is easy to manufacture, and (3) a versatile random access function cannot be achieved.
[0007]
In terms of the operation method, in the DRAM, the plate electrode at one end of the capacitor is fixed to (1/2) Vdd, but in the FRAM, the only difference is that it varies between 0 V and Vdd. Also in this regard, a method of changing the plate electrode as shown in FIG. 76 (a) (T. Sumi et al, 1994 IEEE International Solid-State Circuit Conference Digest of Technical Paper, pp. 268-269, Feb, 1994). 76), the plate electrode is fixed to (1/2) Vdd (H. Koike et al., 1996 IEEE International Solid-State Circuit Conference Digest of Technical Paper). pp.368-369, Feb, 1996, or K. Takeuchi et al., IEICE Trans, Electron., Vol. E79-C, No. 2, Feb, 1996).
[0008]
In the method of driving the plate electrode between 0 V and Vdd, since many memory cells are connected to the plate electrode, the load capacity is large, and the driving time is very long, the access time and cycle time are longer than those of the conventional DRAM. The current situation is that the operation of both is slow. The method of fixing the plate to (1/2) Vdd does not need to drive a plate having a heavy load capacity, and can therefore achieve an access time and cycle time equivalent to those of a DRAM.
[0009]
However, as shown in FIG. 74 (b), the conventional FRAM memory cell has a configuration in which a transistor and a ferroelectric capacitor are connected in series like the DRAM, and the storage node (SN) is a standby after power-on. Sometimes floating. Therefore, when “1” data is held in SN, SN falls to Vss due to a junction leak at the pn junction of the cell transistor, so that the cell information is destroyed when the pre-rate electrode is fixed to (1/2) Vdd. Therefore, in the (1/2) Vdd cell plate system, a refresh operation similar to that of the DRAM is required, and the problem of an increase in power and the cell leak specification are severe, making it difficult to manufacture.
[0010]
As described above, the conventional FRAM has the second problem that it is difficult to achieve both high-speed operation (PL potential fixed) and refresh unnecessary.
[0011]
The conventional FRAM also has the following problems. 77 (a) shows the standby state of the conventional FRAM, FIG. 77 (b) shows the operation of the PL drive system, and FIG. 77 (d) shows the locus on the hysteresis curve at the time of reading. In the conventional readout method, when the saturation polarization amount is Ps and the residual polarization amount is Pr, as shown in FIG. 77 (d), “1” data is Ps + Pr, “0” data is Ps−Pr, and the difference Is the signal amount (half of that for 1T / 1C). However, the ferroelectric capacitor has a large variation in the paraelectric component due to manufacturing variation or the like, which greatly deteriorates the read margin. For example, in “1” data, Ps−Pr of Ps + Pr is a paraelectric component, and in “0” data, the entire signal is a paraelectric component. Particularly in the case of a ferroelectric material such as PZT, since the value of the dielectric constant itself is large, the absolute value of variation is also a problem.
[0012]
FIG. 77 (c) shows a conventional method for solving this problem. At the time of reading, PL is raised from Vss to Vdd, and further lowered from Vdd to Vss, and then the sense amplifier is operated to amplify the signal. FIG. 77 (e) shows the locus on the hysteresis curve at the time of reading. The “1” data (point (2)) is inverted once and comes to the position (1), but comes to the position (3) by lowering the PL. Therefore, in the “1” data, the paraelectric component is cut back and forth, and the remanent polarization component: 2Pr is read as a signal to the bit line. Since the “0” data simply goes from the point (3) to the point (1) and returns to the point (3), no signal is read out. Eventually, the signal is only the polarization component 2Pr having no paraelectric component with many variations, and noise is eliminated.
[0013]
However, in this method, as shown in FIG. 77 (c), in order to rewrite data, it is necessary to raise and lower PL twice in order to raise PL again and lower PL. ) Has a problem that the access time and cycle time become very long.
[0014]
[Problems to be solved by the invention]
Thus, in the conventional FRAM, a small 4F²There is a first problem that it is not possible to achieve both the size memory cell, the easy-to-manufacture planar transistor, and the versatile random access function. Furthermore, it is difficult to achieve both high-speed operation (PL potential fixation) and refresh unnecessary. There was a second problem. In addition, there has been a problem that the operation becomes slow when an attempt is made to suppress variations in the paraelectric component of the ferroelectric capacitor.
[0015]
The present invention has been made in consideration of the above-mentioned circumstances, and its object is to use 4F without using a vertical transistor or the like.²An object of the present invention is to provide a nonvolatile semiconductor memory device that can realize a memory cell of a size and can also maintain a random access function.
[0016]
Another object of the present invention is to provide a semiconductor memory device capable of achieving both high-speed operation by fixing the plate potential and no need for refresh.
[0017]
Another object of the present invention is to provide a semiconductor memory device that can suppress variations in the paraelectric component of a ferroelectric capacitor without causing a decrease in operating speed.
[0018]
[Means for Solving the Problems]
(Constitution)
In order to solve the above problems, the present invention adopts the following configuration.
[0019]
  (1) A memory cell is composed of a cell transistor having a word line as a gate electrode and a ferroelectric capacitor connected in parallel between the source and drain terminals of the cell transistor, and a plurality of the memory cells are connected in series. In addition, a memory cell block selection transistor is connected to at least one end of the plurality of serially connected ones to form a memory cell block. One end of the memory cell block is connected to a bit line and the other end is connected to a plate line.A plurality of memory cell blocks are arranged to form a cell array.A semiconductor memory device,The bit lines are paired with twoConnected to the same sense amplifier circuit and connected to each of the two bit lines forming the pair.Same word line groupThe two memory cell blocks connected to each other are connected to the first plate line and the second plate line of different signals, respectively.
[0020]
(2)A memory cell is composed of a cell transistor having a word line as a gate electrode and a ferroelectric capacitor connected in parallel between the source and drain terminals of the cell transistor, and a plurality of the memory cells are connected in series, A memory cell block selection transistor is connected to at least one end of a plurality of serially connected memory cells to form a memory cell block. One end of the memory cell block is connected to a bit line and the other end is connected to a plate line. A semiconductor memory device in which a plurality of blocks are arranged to constitute a cell array, each of the memory cell blocks in which a plurality of first plate lines and second plate lines are alternately arranged in the word line direction. Connected toIt is characterized by that.
[0021]
(3)A memory cell is composed of a cell transistor having a word line as a gate electrode and a ferroelectric capacitor connected in parallel between the source and drain terminals of the cell transistor, and a plurality of the memory cells are connected in series, A memory cell block selection transistor is connected to at least one end of a plurality of serially connected memory cells to form a memory cell block. One end of the memory cell block is connected to a bit line and the other end is connected to a plate line. A semiconductor memory device in which a plurality of blocks are arranged to constitute a cell array, and each of the memory cell blocks in which a plurality of first plate lines and second plate lines are alternately arranged every two in the word line direction. Connected toIt is characterized by that.
[0022]
  (4) A memory cell is constituted by a cell transistor and a ferroelectric capacitor connected in parallel between the source and drain terminals of the cell transistor, and a plurality of the memory cells are connected in series to constitute a memory cell block. A semiconductor memory device comprising a cell array in which a plurality of the memory cell blocks are arranged, and a write buffer for writing data to the memory cell from the outside, wherein the write buffer includes a first write transistor, a first write transistor, From the writing transistorDriving forceA second writing transistor having a large current is provided, and at the time of writing, the time for starting driving the second writing transistor is delayed compared to the time for starting driving the first writing transistor.
[0023]
(Five) A memory cell is composed of a cell transistor having a word line as a gate electrode and a ferroelectric capacitor connected in parallel between the source and drain terminals of the cell transistor, and a plurality of the memory cells are connected in series, A memory cell block is formed by connecting a memory cell block selection transistor to at least one end of a plurality of serially connected ones, and one end of the memory cell block is connected to a bit line and the other end is connected to a plate line. The device is the device, wherein the plate line is formed of the same metal wiring layer as that connecting the cell transistor and the ferroelectric capacitor.It is characterized by that.
[0024]
(6)A memory cell is composed of a cell transistor having a word line as a gate electrode and a ferroelectric capacitor connected in parallel between the source and drain terminals of the cell transistor, and a plurality of the memory cells are connected in series. A memory cell block is formed by connecting a memory cell block selection transistor to at least one end of a plurality of serially connected ones, and one end of the memory cell block is connected to a bit line and the other end is connected to a plate line. The same metal wiring layer as the first metal wiring layer for word line snap, which is formed in an upper layer than the gate wiring layer of the word line and contacts the gate wiring layer at a first interval. In contact with the wiring layer of the plate line at every second intervalIt is characterized by that.
[0025]
(7)A memory cell is composed of a cell transistor having a word line as a gate electrode and a ferroelectric capacitor connected in parallel between the source and drain terminals of the cell transistor, and a plurality of the memory cells are connected in series. A memory cell block selection transistor is connected to at least one end of a plurality of serially connected memory cells to form a memory cell block. One end of the memory cell block is connected to a bit line and the other end is connected to a plate line. A semiconductor memory device comprising a plurality of blocks and constituting a cell array, wherein a drive circuit for driving the plate line is arranged in the bit line direction for every one or every two of the memory cell blocks.It is characterized by that.
[0026]
(8)A semiconductor memory device comprising a memory cell comprising an nMOS transistor, a pMOS transistor, and a ferroelectric capacitor, wherein the source of the nMOS transistor, the source of the pMOS transistor, and one end of the ferroelectric capacitor are connected, and the nMOS transistor And the other end of the ferroelectric capacitor are connected to each other.It is characterized by that.
[0027]
  (9) A memory cell is composed of a cell transistor having a word line as a gate electrode and a ferroelectric capacitor connected in parallel between the source and drain terminals of the cell transistor, and a plurality of the memory cells are connected in series. In addition, a memory cell block selection transistor is connected to at least one end of the plurality of serially connected ones to form a memory cell block, and a plurality of the memory cell blocks are arranged to form a cell array, and one end of the memory cell block is a bit. Connected to the wire, the other end is connected to the plate wire,Furthermore,Word lineConnected toSub-row decoder and the sub-row decoderConnectedA semiconductor memory device having a main word line, wherein the main word line is formed of the same wiring layer as the metal wiring layer of the plate line.
[0028]
  (10) A memory cell is composed of a cell transistor and a ferroelectric capacitor connected in parallel between the source and drain terminals of the cell transistor, the memory cells are connected in series, and the plurality of memory cells are connected in series. A semiconductor memory device in which a memory cell block is configured by connecting a memory cell block selection transistor to at least one end of the semiconductorCapacitorsA first contact connecting the lower electrode and the source terminal; a first metal wiring layer connected via a second contact from the upper electrode of the ferroelectric capacitor; and a third contact connecting the drain terminal. And at least part of the first contact and the third contact are formed by the same process.
[0029]
  (11) A memory cell is composed of a cell transistor and a ferroelectric capacitor connected in parallel between the source and drain terminals of the cell transistor, and a plurality of the memory cells are connected in series. A semiconductor memory device in which a memory cell block is configured by connecting a memory cell block selection transistor to at least one end of the semiconductorCapacitorsA first contact connecting the lower electrode and the source terminal; a first metal wiring layer connected via a second contact from the upper electrode of the ferroelectric capacitor; and a third contact connecting the drain terminal. And the first contact and the third contact are made of different materials.
[0030]
  (12) A memory cell is composed of a cell transistor and a ferroelectric capacitor connected in parallel between the source and drain terminals of the cell transistor, the memory cells are connected in series, and the plurality of memory cells are connected in series. A semiconductor memory device in which a memory cell block is configured by connecting a memory cell block selection transistor to at least one end of the semiconductorCapacitorsA first contact connecting the lower electrode and the source terminal; a first metal wiring layer connected via a second contact from the upper electrode of the ferroelectric capacitor; and a third contact connecting the drain terminal. Contact, and the first contact and the third contact are made of at least two kinds of materials.Different materials are stackedIt is formed.
[0031]
  (13) A memory cell is composed of a cell transistor and a ferroelectric capacitor connected in parallel between the source and drain terminals of the cell transistor, and a plurality of the memory cells are connected in series. A semiconductor memory device in which a memory cell block is configured by connecting a memory cell block selection transistor to at least one end of the semiconductorCapacitorsThe contact layer connecting the lower electrode and the source or drain terminal has at least two different material layers.Formed by stackingIt is characterized by that.
[0036]
(Function)
Above(1) ~ (3) Therefore, even if the PL driving method is adopted in the 1T / 1C configuration by dividing the PL line, the block selection transistor is not turned on and the cell data is not read while being connected to the selected word line. Since the PL line connected to the cell block is not driven, the potential of the floating node in the cell block from which cell data is not read does not change, and polarization data does not decrease.
[0038]
Said(Four) According to the present invention, since the writing speed is slow, noise at the time of writing data peculiar to the ferroelectric memory can be reduced.
[0039]
Said(Five) According to the above, since the PL wiring can be configured using the metal wiring connecting the cell transistor and the ferroelectric capacitor, the resistance of the PL wiring can be reduced, and the RC delay of the PL wiring in the PL driving method can be shortened.
[0040]
Said(6) According to the above, since the PL wiring can be configured using the metal wiring for word line snap, the resistance of the PL wiring can be reduced, and the RC delay of the PL wiring in the PL driving method can be shortened.
[0041]
Said(7) Accordingly, the size of the plate line drive transistor of the plate line drive circuit can be increased, the ON resistance of this transistor can be reduced, and the RC delay of the PL wiring in the PL drive system can be shortened.
[0042]
Said(8) The memory cell transistor and block selection transistor can be made full CMOS, the threshold voltage does not drop, data can be read / written without boosting the word line and block selection line to Vdd or higher, A circuit is unnecessary, and reliability can be improved and mixed loading can be facilitated.
[0043]
DETAILED DESCRIPTION OF THE INVENTION
First, the contents of the prior application already proposed by the present inventors will be described.
[0044]
For the first and second major problems described above, the present inventor is a nonvolatile ferroelectric memory, and (1) a small 4F²3 size memory cell, (2) easy-to-manufacture planar transistor, and (3) general-purpose random access function, and the PL potential is fixed. A semiconductor memory device that can be held and does not require a refresh operation has been proposed (Japanese Patent Application No. 9-153137).
[0045]
An outline of the prior application will be briefly described. 78, 79, and 80 show a configuration circuit and an operation example of the memory cell of the prior invention. In the prior application, one memory cell is constituted by parallel connection of a cell transistor and a ferroelectric capacitor, and one memory cell block is formed by connecting a plurality of parallel-connected memory cells in series, and one end is a block selection. It is connected to the bit line through the transistor, and the other end is connected to the plate. With this configuration, while using a planar transistor, 4F²A memory cell of a size is realized.
[0046]
As shown in FIG. 78A, at the time of standby, all the cell transistors are turned on, and the block selection transistors are turned off. By doing so, both ends of the ferroelectric capacitor are electrically short-circuited by the cell transistor that is turned on, so that a potential difference between both ends does not occur. Therefore, the polarization data “1” is stably held at the “1” point of the hysteresis curve in FIG. 78A, and the polarization data “0” is stably held at the “0” point of the hysteresis curve. As a result, cell data is safe regardless of whether there is any leakage current such as pn junction leakage during standby, plate driving method is 0V to Vdd driving method, or (1/2) Vdd fixed method. Retained.
[0047]
As shown in FIG. 78B, when active, only the cell transistor connected in parallel to the ferroelectric capacitor to be read is turned OFF, and the block selection transistor is turned ON. At this time, the potential difference between PL and BL is applied only to both ends of the ferroelectric capacitor connected in parallel to the OFF cell transistor, and the polarization information of the ferroelectric capacitor is read to the bit line. Therefore, even if memory cells are connected in series, by selecting an arbitrary word line, cell information of an arbitrary ferroelectric capacitor is read, and complete random access can be realized. Thereby, the open BL system can be realized by the cell block shown in FIG. 78 as described in the prior application.
[0048]
Further, two cell blocks shown in FIG. 78 are paired and each is connected to one of the bit line pairs (/ BL, BL), and two cell blocks connected to the same word line in two cell blocks. If a memory cell is assembled and 1 bit is stored in a 2 transistor / 2 ferroelectric capacitor (= 2T / 2C), a folded BL system can be realized as described in the previous application.
[0049]
Further, as shown in FIG. 79A, two block selection transistors are connected in series, and one of them is a D (Depletion) type transistor, and one of the block selection transistors (BS0, BS1) is set to “H”. Then, only the data of one of the two cell blocks is read out to the bit line, and if the other of the bit line pair is used as a reference bit line, the folded BL method can be realized.
[0050]
FIGS. 79B and 79C show an example of operation of the folded BL system. As described in the previous application, the (1/2) Vdd fixed plate electrode method (FIG. 79 (b)) and the drive plate electrode method (FIG. 79 (c)) can be applied.
[0051]
However, even in the prior application, there are inconveniences in some operation modes as shown in FIG. FIG. 80 shows a comparison table between the conventional FRAM and the prior application. In the conventional FRAM, only the PL driving method having a slow operation can be applied to both the 2T / 2C cell and the 1T / 1C cell, and the (1/2) Vdd fixed PL method requires a refresh operation. On the other hand, in the cell system of the prior application, both the high-speed (1/2) Vdd fixed PL system and the PL driving system can be applied to both 2T / 2C cells and 1T / 1C cells. However, with the 1T / 1C cell, the PL driving method has a problem of generating large noise in operation.
[0052]
This problem will be described with reference to FIG. For example, when WL2 is selected and MC1 is read / written, WL2 is changed from High to Low, the cell transistor is turned ON, BS0 is changed from Low to High, and the block selection transistor Q1 is turned ON. After that, PL is changed from Low to High.
[0053]
The PL potential is applied to one end of the ferroelectric capacitor of MC1, and the bit line (/ BL) potential is applied to the other end of the ferroelectric capacitor of MC1, so that / BL is precharged to Vss. In this case, by changing PL from Vss to Vdd, a potential difference of Vdd−Vss is applied to both ends of the ferroelectric capacitor, and polarization data is read out. At this time, BS1 is at the low level, and the block selection transistor Q2 remains OFF, so that the cell information of MC2 is not read out to the bit line BL. Therefore, the folded BL system can be taken with the BL side as the reference bit line.
[0054]
However, since one end of the ferroelectric capacitor of MC2 is connected to PL, one end of the ferroelectric capacitor of MC2 also rises from Vss to Vdd. At this time, the nodes n2 to n3 connected to the other end (n1) of MC2 and the non-selected cell transistor that is turned on become floating because the cell transistor connected to WL2 is turned off. Therefore, since parasitic capacitance (assuming the total is Ctot) always exists in n1 to n3, when PL changes from Vss to Vdd, these nodes are not connected to both ends of the ferroelectric capacitor by 0V but Ctot. A potential difference of / (CMC2 + Ctot) × Vdd is generated. That is, there is a problem that the potential of n1 to n3 does not change from Vss to Vdd due to the parasitic capacitance, and the potential is slightly lowered, resulting in noise and partial polarization data being destroyed.
[0055]
As described in the previous application, (1/2) Vdd fixed method also causes n1 to n3 to float, but because the PL potential does not move, n1 to n3 fluctuate due to leakage, etc. only during the active time. If there is no problem. Since the active time is usually tRCmax = 10 μs, this time is short and causes no problem.
[0056]
As described above, in the ferroelectric memory of the prior application, it is possible to realize high integration while facilitating manufacture and maintaining the random accelerator function, further enabling reduction of bit line capacity and low noise, and high speed. However, when the plate driving method is applied with a 1 transistor + 1 capacitor configuration, noise due to floating exists. The present invention also solves such a problem.
[0057]
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0058]
(First embodiment)
FIG. 1 is a circuit configuration diagram showing an FRAM according to the first embodiment of the present invention, and FIG. 2 is a signal waveform diagram showing a specific operation example of the embodiment. In this embodiment, as in the prior application, one memory cell is configured by parallel connection of a cell transistor and a ferroelectric capacitor, and one memory cell block includes a plurality of memory cells connected in parallel. One end is connected to the bit line via the block selection transistor, and the other end is connected to the plate. With this configuration, using a planar transistor, 4F²A memory cell of a size can be realized.
[0059]
As shown in FIG. 1, when two block selection transistors are connected in series, one of them is a D-type transistor and one of the block selection transistors (BS0, BS1) is set to High, one of the two cell blocks Only the data is read out to the bit line, and a folded BL system in which the other of the bit line pair is the reference bit line can be realized, and 1T data is stored by one cell transistor and one ferroelectric capacitor. / 1C cell can be configured.
[0060]
This embodiment is different from the prior application in that one type of plate line is separated into two types of plate lines (PLBBL, PLBL) in the present embodiment. The plate line PLBBL is connected to the cell block connected to the BBLi (BBL0, BBL1) side of the bit line pair, and the plate line PLBL is connected to the cell block connected to the BLi (BL0, BL1) side of the bit line pair. Are connected.
[0061]
By separating the plate lines in this way, as shown in FIG. 2B, when selecting a cell in the cell block on the BBLi side during operation, only PLBBL is driven from 0V → Vdd → 0V to obtain cell data. Since the plate line PLBL connected to the cell block connected to the BLi side serving as the reference bit line remains at 0V, the cell node that becomes floating remains at 0V, and the conventional polarization data is partially destroyed. This problem can be avoided in this embodiment.
[0062]
Even if the cell node is floating, if the plate line is 0V, the cell node always becomes 0V due to leakage of the pn junction between the cell node and the substrate (or well) biased to 0V. The potential difference remains 0V and the polarization data is preserved. According to the present embodiment, it is possible to realize a PL driving method capable of low voltage operation with a high density 1T / 1C configuration, while avoiding the problem of polarization data destruction due to floating.
[0063]
In the configuration of the present invention, not only the 1T / 1C configuration but also the 2T / 2C configuration can be realized. In this case, as shown in FIG. 2A, the block selection signals BS0 and BS1 are both set to a high level during operation, both the cell blocks connected to the bit line pair BBLi and BLi are selected, and both the plate line and the PLBBL and PLBL are selected. This can be achieved by operating.
[0064]
Also, the method shown in FIGS. 2A and 2B can be realized in the same chip. Thus, for example, even when a 2T / 2C configuration product is sold, there is a merit that the test can be operated in the 1T / 1C configuration and an evaluation test can be performed for each ferroelectric capacitor. When two plate lines are connected for each cell block, the chip area increases correspondingly. However, as shown in the figure, if two cell blocks adjacent in the bit line direction share the plate line, Substantially one plate line connection is made for each cell block, and an increase in area can be suppressed.
[0065]
(Second Embodiment)
FIG. 3 is a circuit configuration diagram showing an FRAM according to the second embodiment of the present invention. The difference from the first embodiment shown in FIG. 1 is that the number of cells connected to the cell block is increased from four to eight. Even in this case, the same effect as the first embodiment can be obtained. Thus, the number of cells can be arbitrarily designed as 4, 8, 16, 32, and 64. As the number of cells in the cell block increases, the effect of increasing the chip area due to plate separation can be reduced.
[0066]
FIG. 4 is a modification of FIG. 3 and shows a case where the D-type transistor is not used but this transistor is eliminated and the source side and the drain side are directly connected. Even in this case, the operation is the same as in FIG. 2, and the same effect as in FIGS. Further, the bit line capacitance can be reduced because there is a merit that the capacitance of the D-type transistor portion of the unselected cell block cannot be seen as the bit line capacitance.
[0067]
(Third embodiment)
5 to 13 show third to seventh embodiments of the present invention, which are embodiments in which a dermicel portion is added to the configuration of FIG. Of course, these embodiments can avoid the problem of polarization data destruction due to floating, as in FIG. Of course, the configurations of FIGS. 3 and 4 can be applied, and the number of cells in the cell block can be arbitrarily designed.
[0068]
FIG. 5 is a circuit configuration diagram showing an FRAM according to the third embodiment of the present invention, and shows a ferroelectric memory cell block and a Tammy cell configuration. Similarly to the memory cell, the dummy cell is composed of a parallel connection of a ferroelectric capacitor and a cell transistor, and a plurality of these are connected in parallel like the memory cell to constitute a dummy cell block. In this embodiment, one dummy cell block is shared by the bit line pair (BBLi, BLi). For example, when reading cell data to BBLi, if DBS0 is set to high level, the dummy cell is connected to BLi on the reference bit line side, and when reading cell data to BLi, when DBS1 is set to high level, the dummy cell becomes the reference bit. Connected to BBLi on the line side.
[0069]
FIG. 6 shows an operation example of the configuration of FIG. FIG. 6A shows a 1T / 1C configuration and a plate driving method. WL2 and DWL2 are set to the low level, BS0 and DBS0 are set to the high level, the memory cell and the dummy cell are connected to the bit line, one of the memory cell block plate lines (PLBBL, PLBL), and the dummy cell block plate By driving the line (DPL), cell data and dummy cell data are read out to the bit line. After reading and writing data, BS0 is lowered, WL2 is raised, and the bit line is precharged to Vss, so that "0" data is rewritten in the dummy cell by keeping DWL low and DBS0 high. Thereafter, by lowering DBS0 and raising DWL2, the active operation ends.
[0070]
If the area of the ferroelectric capacitor of the dummy cell is designed to be larger than the area of the ferroelectric capacitor of the memory cell, the “0” data of the dummy cell may be between “0” data and “1” data of the memory cell. Yes, it can be a standard.
[0071]
FIG. 6B shows the case of (1/2) Vdd fixed plate system operation, and the operation is the same as FIG. 6A except that the plate is fixed.
[0072]
(Fourth embodiment)
FIG. 7 is a circuit configuration diagram showing an FRAM according to the fourth embodiment of the present invention, and shows a ferroelectric memory cell block and a dummy cell configuration. The difference from FIG. 5 is that a reset transistor (Q3, Q4) and a reset signal (RST) are added in the dummy cell block. As an effect of this embodiment, there is a merit that the cycle time is shortened as compared with FIG. An example of the operation is shown in FIG.
[0073]
FIG. 8B shows a 1T / 1C configuration and a plate driving method. WL2 and DWL2 are set to the low level, BS0 and DBS0 are set to the high level, the memory cell and the dummy cell are connected to the bit line, one of the memory cell block plate lines (PLBBL, PLBL), and the plate line for the dummy cell block By driving (DPL), cell data and dummy cell data are read out to the bit line.
[0074]
Thereafter, before or after the operation of the sense amplifier, DBS0 is lowered, the dummy cell block and the bit line are separated, and the plate line at one end of the plurality of dummy cell blocks connected in series is kept high, and the RST line is raised. The other end is dropped to Vss1, a potential difference of Vdd is applied to both ends of the ferroelectric capacitor of the selected dummy cell, and "0" data is rewritten to the dummy cell. The reference potential can be set not only by the area of the ferroelectric capacitor of the dummy cell but also by freely designing the dummy plate potential and the reset potential (Vss1).
[0075]
Thereafter, the active operation is completed by lowering the RST line, lowering the plate line (DPL), and raising DWL2. The (re) write operation of the memory cell and the reset operation of WL2 and BS0 can be performed in parallel with the dummy cell operation, and it is not necessary to perform the rewrite operation of the dummy cell after resetting WL2 and BS0 as shown in FIG. Time can be shortened.
[0076]
FIG. 8A shows the case of (1/2) Vdd fixed plate system operation, and the operation is the same as FIG. 8B except that the plate is fixed.
[0077]
(Fifth embodiment)
FIG. 9 is a circuit configuration diagram showing an FRAM according to the fifth embodiment of the present invention, and shows a ferroelectric memory cell block and a dummy cell configuration. In this embodiment, a paraelectric capacitor is used for the dummy cell.
[0078]
When a paraelectric capacitor is used as in this embodiment, there is a demerit that the dummy cell capacitor area is large, but fatigue, relaxation (depolarization), imprint and other film degradation are small (no), and the reference potential is stable. There is merit to become. The dummy cell in FIG. 9 includes a paraelectric capacitor, transistors (Q5, Q6) that short-circuit the capacitor, a signal line (RST) that controls the paraelectric capacitor, and a selection transistor (Q7, Q8) connected to one of the bit line pairs. ), Its control lines (DWL0, DWL1), and a plate line (DPL).
[0079]
(Sixth embodiment)
FIG. 10 is a circuit configuration diagram showing an FRAM according to the sixth embodiment of the present invention, and shows a ferroelectric memory cell block and a dummy cell configuration. In this embodiment, a dummy cell using a paraelectric capacitor is used as in FIG.
[0080]
This embodiment is different from the dummy cell of FIG. 9 in that the RST signal is not used to short-circuit the paraelectric capacitor, but one end of the paraelectric capacitor is connected to the plate and the other end is connected to the RST signal. The level is to connect to an arbitrary potential Vss1 to reset the paraelectric capacitor to the potential difference of DPL-Vss1. First, FIG. 9 and FIG. 10 can perform the same operation as shown in FIG.
[0081]
FIG. 11A shows the case of the plate driving method with the 1T / 1C configuration. WL2 is set to Low level, BS0 is set to High level, the memory cell is connected to the bit line, and DWL0 is set to High level to connect the dummy cell to the reference bit line. Thereafter, one of the cell block plate lines (PLBBL, PLBL) is driven to read the cell data to the bit line. The dummy cell is driven by the dummy cell plate line (DOPL), and the capacitor coupling causes reference The bit line is set to a desired potential. Thereafter, DWL0 is lowered, the DPL line is set to Vss, and the RST line is set to a high level, whereby the potential difference of the paraelectric capacitor of the dummy cell can be reset to 0V, and the active operation ends.
[0082]
FIG. 11B shows the case of (1/2) Vdd fixed plate system operation, and the operation is the same as FIG. 11A except that the plate is fixed. However, the plate of the dummy cell is driven because it uses capacitor coupling. It is also possible to fix the dummy cell plate line to (1/2) Vdd (or an arbitrary potential). For example, in FIG. 9, during standby, DPL is set to (1/2) Vdd, and RST When DWL0 is lowered, both ends of the paraelectric capacitor are (1/2) Vdd. Therefore, when DWL0 is raised, the reference bit line potential is automatically raised by capacitor coupling, and the operation becomes possible.
[0083]
In the example of FIG. 10, in order to keep both ends of the paraelectric capacitor at (1/2) Vdd during standby, not only DPL but also Vss1 is set to (1/2) Vdd. There is a need.
[0084]
(Seventh embodiment)
FIG. 12 is a circuit configuration diagram showing an FRAM according to the seventh embodiment of the present invention, and shows a ferroelectric memory cell block and a dummy cell configuration. In this embodiment, as in FIGS. 9 and 10, a dummy cell using a paraelectric capacitor is used, but a dummy cell is formed by a plate line (DPL), a paraelectric capacitor and a selection transistor, and a reset transistor. Is omitted. The merit of FIG. 12 is that a reset transistor and a reset signal are not required and the number of elements can be minimized. An example of this operation is shown in FIG.
[0085]
FIG. 13A shows a 1T / 1C configuration and a plate driving method. WL2 is set to the L0w level and BS0 is set to the high level, and the memory cell is connected to the bit line. At the same time, among the dummy cell selection lines DWL0 and DWL1, which are both at the high level during standby, only the bit-side selection line from which cell data is read is lowered from the high level to the low level, and the paraelectric capacitor is set to the reference bit line. Connect to only.
[0086]
Thereafter, one of the cell block plate lines (PLBBL, PLBL) is driven to read the cell data to the bit line, and the dummy cell is driven by the dummy cell plate line (DPL) by capacitor coupling. The bit line is set to a desired potential. After the sensing operation, DPL is lowered, and then both dummy cell selection lines DWL0 and DWL1 are returned to High. When the bit line is precharged to Vss after writing the cell data, both ends of the paraelectric capacitor are automatically reset to 0V because DWL1 and DWL0 are High.
[0087]
FIG. 13B shows the case of (1/2) Vdd fixed plate system operation, and the operation is the same as FIG. 13A except that the plate is fixed. However, it is necessary to drive the plate line of the dummy cell.
[0088]
(Eighth embodiment)
FIG. 14 is a signal waveform diagram showing an operation method of the FRAM according to the eighth embodiment of the present invention.
[0089]
In the present embodiment, as in the previous application, one memory cell is configured by parallel connection of a cell transistor and a ferroelectric capacitor, and one memory cell block includes a plurality of memory cells connected in parallel. One end is connected to the bit line via the block selection transistor, and the other end can be applied to the memory cell connected to the plate, and controls variations in the paraelectric component of the ferroelectric capacitor compared to the previous application method. However, high speed operation is possible.
[0090]
As shown in FIG. 77, in the single plate method (FIG. 77 (b)), it is sufficient to operate the plate electrode once in the operation of Vss → Vdd → Vss, but as shown in FIG. 77 (d). As described above, when the saturation polarization amount is Ps and the residual polarization amount is Pr, the “1” data is Ps + Pr, the “0” data is Ps−Pr, and the difference is the signal amount (half of that in 1T / 1C). . However, the ferroelectric capacitor has a large variation in the paraelectric component due to manufacturing variations and the like, and this has a problem of greatly degrading the read margin.
Furthermore, in the conventional double plate method (FIG. 77 (c)) that solves this problem, the plate voltage is operated twice as Vss → Vdd → Vss → Vdd → Vss during operation, as shown in FIG. As described above, the paraelectric component can be canceled on the way back and forth, and there is a merit that the problem of variation can be canceled. However, since it is necessary to raise and lower the PL twice, there is a problem that the access time and cycle time become very long. there were.
[0091]
On the other hand, in FIG. 14, the paraelectric component can be canceled by one plate drive, as in the case of two plate drives. Two types of operations are possible. In FIG. 14A, during precharging, the plate (PL) is precharged to 0V and the bit lines (BLs) are precharged to Vdd. As a result, the potential of Vdd is applied to both ends of the selected ferroelectric capacitor without driving the plate only by lowering WL2 and lowering BS0.
[0092]
In a conventional memory cell, a cell transistor and a ferroelectric capacitor are connected in series, and since the cell node is floating during standby, cell polarization data is destroyed by junction leakage unless the plate is set to 0V. However, if the bit line potential is not set to 0 V, there is a problem that the cell polarization data is destroyed due to transistor leakage. However, in the memory cell configuration of the prior application, the cell transistor is turned on during standby. In addition, since the ferroelectric capacitor is always short-circuited, there is an advantage that the plate potential and the bit line potential are not limited. The reverse precharge of the plate potential and the bit line potential during standby according to the present embodiment takes advantage of this merit.
[0093]
With such a reading method, “1” data changes from the point (2) in FIG. 77E to the point (1), and “0” data changes from the point (3) to the transition (1). Thus, the polarization data is read out to the bit line (in FIG. 77 (e), the x-axis polarity is opposite to that of the conventional method). Thereafter, when PL is raised to Vdd for the first time, “1” data is changed from point (1) to (3) in FIG. 77 (e), and “0” data is changed from point (1) to (3). Transition to transition. As a result, the paraelectric component of data “1” is cut back and forth, and the remanent polarization component: 2Pr is read as a signal to the bit line. Since the “0” data simply goes from the point (3) to the point (1) and returns to the point (3), no signal is read out. Eventually, the signal is only the polarization component 2Pr having no paraelectric component with many variations, and noise is eliminated.
[0094]
Thereafter, the potential difference between the bit line pair is amplified by a sense amplifier circuit. If the plate is left at Vdd, "0" data is rewritten to 0V. After that, when the plate is lowered to Vss, "1" data is rewritten to Vdd. The rewriting is finished. Thereafter, BS0 is lowered, WL2 is raised, the bit line is precharged to Vdd, and the active operation ends. That is, according to the present embodiment, the plate only needs to be raised and lowered once, and both high speed and variation cancellation can be realized.
[0095]
FIG. 14B shows a case where the potentials of the plate and the bit line are completely reversed with respect to FIG. Also in this method, the paraelectric component can be canceled by one plate drive as in the case of two plate drives. When precharging, the plate (PL) is precharged to Vdd and the bit line (BLs) is precharged to Vss. As a result, the potential of Vdd is applied to both ends of the selected ferroelectric capacitor without driving the plate only by lowering WL2 and lowering BS0.
[0096]
With such a reading method, “1” data changes from the point (2) in FIG. 77E to the point (1), and “0” data changes from the point (3) to the transition (1). Thus, the polarization data is read out to the bit line. Thereafter, when PL is lowered to Vss for the first time, “1” data is changed from point (1) to (3) in FIG. 77 (e), and “0” data is changed from point (1) to (3). Transition to transition.
[0097]
As a result, the paraelectric component of data “1” is cut back and forth, and the remanent polarization component: 2Pr is read as a signal to the bit line. Since the “0” data only goes from the point (3) to the point (1) and returns to the point (3), no signal is read out. Eventually, the signal is only the polarization component 2Pr having no paraelectric component with many variations, and noise is eliminated.
[0098]
Thereafter, the potential difference between the bit line pair is amplified by a sense amplifier circuit. If the plate is left at Vss, the “1” data raised to Vdd will be rewritten, and then if the plate is raised to Vdd, the “0” data lowered to Vss will be rewritten. The rewriting is finished. Thereafter, BS0 is lowered, WL2 is raised, the bit line is precharged to Vss, and the active operation ends. In the end, according to the present invention, the plate needs only to be lowered once, and both high speed and variation cancellation can be realized.
[0099]
14 (a) and 14 (b) can be applied to the 2T / 2C method (FIG. 15 (a)) of the prior application, and the method of the present invention (FIG. 15 (b)) in which the plate electrode is separated. Is also applicable. In this case, both 1T / 1C and 2T / 2C can be realized.
[0100]
(Eighth embodiment)
FIG. 16 is a signal waveform diagram showing the operation of the FRAM according to the ninth exemplary embodiment of the present invention. FIG. 14 shows an operation scene sequence when the power supply is turned on and off when the plate and bit line reverse precharge method of FIG. 14 and FIG. 15 is applied. FIG. 16 (a) shows the case of FIG. 14 (a), and FIG. 16 (b) shows the case of FIG. 14 (b).
[0101]
In FIG. 16A, when the power supply is turned on, the power supply is completely raised and the plate potential is kept at Vss, and the internal node is stabilized, and then the bit line potential (bit line precharge power supply: VBL) is set to Vdd. Then, the cell data is not destroyed, and when the power is turned off, the cell data is not destroyed if the bit line potential (bit line precharge power supply: VBL) is lowered to Vss before Vdd is lowered to Vccmin.
[0102]
In FIG. 16B, when the power supply is turned on, the power supply is completely started up and the bit line potential (bit line precharge power supply: VBL) is kept at Vss while the internal node is stabilized, and then the plate potential is changed to Vdd. Then, the cell data is not destroyed. When the power is turned off, the cell data is not destroyed if the plate potential is lowered to Vss before Vdd is lowered to Vccmin.
[0103]
(Tenth embodiment)
FIG. 17 is a diagram showing the configuration of the sense amplifier section of the FRAM according to the tenth embodiment of the present invention. FIG. 14A shows a sense amplifier circuit applicable to the method of setting the plate to Vss and the bit line to Vdd at the time of precharge in FIG.
[0104]
A transistor for precharging the bit line is provided separately from the sense amplifier circuit, and the bit line pair can be precharged to Vdd by setting the EQL signal to a low level during precharging.
[0105]
(Eleventh embodiment)
FIG. 18 is a diagram showing the configuration of the sense amplifier section of the FRAM according to the eleventh embodiment of the present invention. FIG. 14B shows a sense amplifier circuit applicable to the method of setting the plate to Vdd and the bit line to Vss at the time of precharging in FIG. In this example, the bit line pair can be precharged to Vss by setting the EQL signal to High level during precharging.
[0106]
(Twelfth embodiment)
By the way, in the plate potential and bit line potential precharge system, as shown in the prior application, one memory cell is constituted by parallel connection of a cell transistor and a plurality of ferroelectric capacitors having different coercive voltages. In the memory cell block, a plurality of the memory cells are directly connected, one end is connected to the bit line via the block selection transistor, and the other end is configured as a memory cell connected to the plate. When applied to a method of storing multi-bit information of bits or more, it is possible to significantly improve read reliability and high-speed operation. This is because in the multi-bit cell system of the prior application, the variation in the paraelectric component of the ferroelectric capacitor appears to be larger than in the 1-bit system of the prior application, and it is important to suppress this. .
[0107]
FIG. 19 shows a multi-bit / cell cell block equivalent circuit in the prior application. In the ferroelectric capacitors Ca and Cb, a relationship of Vca <Vcb is established when the coercive voltage of Ca is Vca and the coercive voltage of Cb is Vcb. FIG. 20 shows an example of a cross-sectional view of the cell structure of FIG. 19 in the prior application. Ca and Cb can be realized by making the Ca ferroelectric capacitor thinner than Cb. FIG. 21 shows a theoretical hysteresis curve showing the operation of the multi-bit / cell system of FIG. 19, and FIG. 22 shows an actual hysteresis curve.
[0108]
The operation will be briefly described with reference to FIG. FIG. 21A shows a hysteresis curve of the ferroelectric capacitor Ca, and FIG. 21B shows a hysteresis curve of the ferroelectric capacitor Cb. FIG. 21 (c) shows a hysteresis curve when Ca and Cb are connected in parallel. One-bit information is stored in each of Ca and Cb.
[0109]
In FIG. 21 (c), the point E ″ indicates a point storing one data and one data (= 11) for each of Ca and Cb. Similarly, the point F ″ is 10, the point C ″ is 01, The A ″ point has four states as a result of 00, and stores 2-bit data.
[0110]
As a read / write operation, a voltage equal to or lower than the coercive voltage of Cb is applied to the parallel ferroelectric capacitor, data of Ca is read, and then a voltage equal to or higher than the coercive voltage of Cb is applied to the parallel ferroelectric capacitor. This data is read and rewritten, and then a voltage equal to or lower than the coercive voltage of Cb is applied to the parallel ferroelectric capacitor to rewrite Ca.
[0111]
However, in the multi-bit / cell system of the prior application, when Vca <Vcb is realized, the actual Ca and Cb hysteresis curves are as shown in FIGS. 22 (a) and 22 (b). When the thickness of the same ferroelectric capacitor material is changed, the dielectric constants are different by the thicknesses, and the Ca paraelectric capacitor component is increased. As a result, in the hysteresis curve (FIG. 22C) in which Ca and Cb are connected in parallel, two types of paraelectric capacitor components are mixed and the read margin is deteriorated. In particular, when Cb is read, a paraelectric capacitor component having a large Ca is mixed and a paraelectric capacitor component varies, which causes a serious problem.
[0112]
Even when the plate driving method is adopted in the multi-bit / cell configuration as described above, when the dummy BL is used in the folded BL configuration, the plate line is divided into two types as shown in FIG. As a result, it is possible to eliminate noise caused by the floating cell node. FIG. 23 is a cross-sectional view of an FRAM ferroelectric memory cell block according to the twelfth embodiment of the present invention, showing a case where the plate is separated into two types (PLBBL, PLBL) at 2 bits / cell. .
[0113]
In this embodiment, a case where ferroelectric capacitors having different film thicknesses and different coercive voltages are formed in the vertical direction is shown. Of course, as shown in the prior application, even when ferroelectric capacitors having different film thicknesses and different coercive voltages are stacked in the lateral direction, the plates can be easily separated.
[0114]
(13th Embodiment)
FIG. 24 shows an example of specific operation timing of multi-bit / cell operation when the plate driving method described in the previous application is applied. When WL02 at the first time becomes Low level, the plate (PL) and the bit lines (/ BL, BL) are operated with small amplitude, and only the Ca data is read and temporarily stored outside the array. Thereafter, in order to eliminate the difference between the “1” data and the “0” data of Ca, a constant voltage is applied to the ferroelectric capacitor and “0” data is written into Ca.
[0115]
When the second WL02 is set to the Low level, the plate (PL) and the bit lines (/ BL, BL) are operated with a large amplitude to read / write the Cb data. Finally, the third WL02 is set to the Low level. At that time, the Ca data temporarily stored is written in Ca again. In this case, naturally, the noise of the paraelectric capacitor component described with reference to FIG. 22 remains large. In the figure, it is possible to operate even if WL02 remains Low and BS0 remains High without resetting WL02 and BS0 one to three times shown in (1).
[0116]
FIG. 25 is an operation timing chart showing a driving method in the thirteenth embodiment of the present invention. In the present embodiment, with WL02 being low at the first to third times, BS0 is kept high, and after the first Ca data read, EQL is set high and the bit line pair (/ BL, BL) is set to Vss. Even after resetting the Ca data, the plate (PL) is kept high with a small amplitude, EQL is set low, the bit line is not equalized, and then PL is set to a high amplitude high potential. Data is being read out. This eliminates an extra plate operation compared to FIG. 24 and realizes a high-speed operation.
[0117]
(Fourteenth embodiment)
FIG. 26 is for explaining the fourteenth embodiment of the present invention, and shows a core circuit configuration for realizing the operation of FIG. 25 and other multi-bit / cell operation examples.
[0118]
As shown in FIG. 26A, by switching between φa and φb using two power sources Va and Vb, a plate operation with a small amplitude and a large amplitude as shown in FIG. 25 can be realized. Similarly, as shown in FIG. 26B, the power source line (VSAH) of the pMOS sense amplifier circuit can be connected to two power sources Va and Vb by switching between φsa and φsb. Amplitude and large amplitude bit line operation can be realized. Using a transistor connected to the signal RON and a ferroelectric capacitor, a temporary register for storing the first Ca data can be easily realized.
[0119]
As shown in FIG. 25, after the bit line is amplified in the first Ca data read operation, RON is set to High, Ca data is written to the capacitor in the register, and RON is set to Low. For example, if the RPL line is set to Va, the ferroelectric capacitor connected to the bit line on the “0” data side becomes the polarization inversion, and the “1” side becomes the non-polarization inversion, so that the data can be held. In the third Ca data write operation, after the second read / write of Cb data is completed, EQL is set to High, the bit line pair is dropped to Vss, EQL is set to Low, and the bit line pair is pre-set to Vss. After charging, RON is set to High to read the register data to the bit line. At this time, if, for example, the RPL line is set to Va potential, one of the two ferroelectric capacitors performs polarization inversion readout, and the other performs non-polarization inversion readout.
[0120]
Thereafter, the bit line is amplified and Ca data is rewritten to the memory cell. As a PL operation in data rewriting, as shown in (2) of FIG. 25, after the bit line is amplified, PL may be raised or lowered, or as shown in (1) of FIG. In a state where EQL after reading and writing is set to High, PL may be raised in advance, and PL after bit line amplification may be lowered. In addition, when reading Ca for the first time, as shown in (3) of FIG. 25, amplification may be performed while increasing φti in FIG. 26B, or as shown in (4) of FIG. May be temporarily lowered to amplify the bit line only within the sense amplifier. This eliminates the need to amplify the bit lines in the cell array and enables high speed operation.
[0121]
FIG. 25 shows an operation example of the column selection line (CSL). According to this multi-bit / cell method, the bit line of the sense amplifier section has a small amplitude and a large amplitude. However, as shown in FIG. 25, when the / DQ and DQ lines remain large amplitude, when CSL is set to High, When data is written from the external data for the first time, a potential larger than a small amplitude is written to the bit line of the sense amplifier. This can be avoided by using the circuit of FIG. 26A and preparing two types of CSL potentials of small amplitude and large amplitude as shown in (5) of FIG. Further, even if the CSL as shown in (6) of FIG. 25 is left with a large amplitude and the two types of amplitudes for writing the BDQ and DQ lines are prepared with the circuit as shown in FIG. .
[0122]
As the dummy cell, a ferroelectric capacitor may be used, or a paraelectric capacitor as shown in FIGS. In the example of FIG. 27 (c), the dummy cell potential in accordance with each cell of Ca and Cb is obtained by changing the amplitude potential of the dummy plate line (DPL) to Va ′ and Vb ′ in the first and second readings. Can be tuned. In the example of FIG. 27D, an example in which the DPL potential is changed without changing the DPL potential between the first time and the second time is shown.
[0123]
For example, when paraelectric capacitors DC0 and DC1 having different capacities are prepared and RST1 is set to High and RST0 is set to Low and DPL is set to High during the first read, the paraelectric capacitor CD0 is read to the bit line. When RST0 is set to High and RST1 is set to Low and DPL is set to High at the time of the third reading, the paraelectric capacitor DC1 is read to the bit line, and the bit line potential on the REFRENCE side can be changed. As a modification, RST1 and RST0 can be set to High and a parallel capacitor can be used.
[0124]
(Fifteenth embodiment)
FIG. 28 is an operation timing chart for explaining the operation of the FRAM according to the fifteenth embodiment of the present invention. The difference from FIG. 24 is that the plate electrode is raised and lowered twice in the first and second time. If the read data is amplified with a sense amplifier once the plate is raised and lowered, the paraelectric capacitor component can be canceled, especially the noise due to the two types of paraelectric capacitor components in the multi-bit / cell method can be canceled, Reliability can be greatly improved. As in FIG. 24, in FIG. 28, the operation can be performed even if WL02 remains Low and BS0 remains High without resetting WL02 and BS0 one to three times shown in (1). When WL02 is lowered for the third time, only rewriting of Ca is performed, so the plate only needs to be raised and lowered once.
[0125]
Thus, when the prior application and the double plate method are combined, 2F per bit of the prior application²While realizing a memory cell of a size or less, it is possible to cancel noise caused by two types of paraelectric capacitor components and variation noise of paraelectric capacitor components, which is a problem of this, and obtain high reliability. It becomes.
[0126]
(Sixteenth embodiment)
FIG. 29 and FIG. 30 are operation timing charts for explaining the operation of the FRAM according to the sixteenth embodiment of the present invention. In the prior application multi-bit / cell method, the number of times of driving the plate is reduced and the high-speed operation is performed. While realizing this, an operation that can cancel noise caused by two types of paraelectric capacitor components and noise of variation components of paraelectric capacitor components and achieve high reliability will be described. In principle, this is realized by a method in which the plate and the bit line in FIG. 14 are precharged in reverse.
[0127]
In the example of FIG. 29, during standby, the bit line is precharged to a high level with a small amplitude, and the plate is precharged to Vss. After WL02 and BS0 are selected, a voltage is applied to the ferroelectric capacitor Ca without driving the plate, and the data of Ca is read out. Thereafter, when the plate is set to a high level with a small amplitude, the paraelectric capacitor component can be canceled.
[0128]
Thereafter, PL is set to Low, BL is set to High, a constant voltage is applied to Ca to eliminate the difference between “0” and “1” data, BS0 is set to Low level, and the cell block and the bit line are separated. During this time, just by precharging the bit line to the high amplitude high level and setting BS0 to the high level for the second time, the polarization data of the Cb ferroelectric capacitor is read to the bit line, and the PL is set to the high level. Then, the paraelectric capacitor component is eliminated, and then the sensing operation is performed, and PL is set to the low level in order to rewrite data. In the third time, since only Ca rewriting is performed, it is only necessary to raise and lower PL once. In addition, as shown by the line (1) in the figure, it is possible to omit raising WL02 from the first time to the third time.
[0129]
FIG. 30 realizes this in the same manner as FIG. 29 by precharging the plate and bit line of FIG. 14 in reverse. The example of FIG. 30 is the same as FIG. 29 except that the potentials of the plate and the bit line are reversed. During standby, the bit line is precharged to a low level, and the plate is precharged to a high level with a small amplitude. After WL02 and BS0 are selected, a voltage is applied to the ferroelectric capacitor Ca without driving the plate, and the data of Ca is read out. Thereafter, when the plate is set to the Vss level, the paraelectric capacitor component can be canceled.
[0130]
Thereafter, PL is set to High, BL is set to Low, a constant voltage is applied to Ca to eliminate the difference between “0” and “1” data, BS0 is set to Low level, and the cell block and the bit line are separated. During this time, just by precharging the plate line to the high amplitude high level and setting BS0 to the high level for the second time, the polarization data of the Cb ferroelectric capacitor is read to the bit line, and the PL is set to the low level. Then, the paraelectric capacitor component is eliminated, and then the sensing operation is performed, and in order to rewrite data, PL is set to the high level. In the third time, since only Ca rewriting is performed, it is naturally only necessary to lower PL once. In addition, as shown by the line (1) in the figure, it is possible to omit raising WL02 from the first time to the third time.
[0131]
(Seventeenth embodiment)
FIGS. 31 and 32 are operation timing charts for explaining the operation of the FRAM according to the seventeenth embodiment of the present invention. While realizing the effects of FIGS. 29 and 30, the number of times of PL driving is further reduced. High speed is realized.
[0132]
In the example of FIG. 31, at the time of standby, the bit line is precharged to a high level of small amplitude, and the plate is precharged to Vss. After WL02 and BS0 are selected, a voltage is applied to the ferroelectric capacitor Ca without driving the plate, and the data of Ca is read out. Thereafter, when the plate is set to a high level with a small amplitude, the paraelectric capacitor component can be canceled.
[0133]
After that, with the PL high, the BL pair is set low, a constant voltage is applied to the Ca to eliminate the difference between “0” and “1” data, the BS0 is set to the low level, and the cell block and the bit line are separated. To do. During this time, just by setting the plate line to the high amplitude high level and the second time BS0 to the high level, the polarization data of the Cb ferroelectric capacitor is read to the bit line, and the PL is set to the low level. In order to eliminate the dielectric capacitor component and then perform a sensing operation to rewrite data, PL is set to a high level. Then, BS0 is set low, the bit line is precharged to Vss, and the plate is set to the high level with a small amplitude. Set BS0 to High for the third time. Ca can be rewritten only by changing PL from High of small amplitude to Vss. In addition, as shown by the line (1) in the figure, it is possible to omit raising WL02 from the first time to the third time.
[0134]
In the example of FIG. 32, during standby, the plate line is set to a high level with a small amplitude, and the bit line is precharged to Vss. After WL02 and BS0 are selected, a voltage is applied to the ferroelectric capacitor Ca without driving the plate, and the data of Ca is read out. Thereafter, when the plate is set to the Vss level, the paraelectric capacitor component can be canceled.
[0135]
After that, while keeping PL low, the BL pair is set to high level with small amplitude, a constant voltage is applied to Ca to eliminate the difference between “0” and “1” data, BS0 is set to low level, Separate the bit lines. During this time, just by setting the bit line pair to the high amplitude high level and the second time BS0 to the high level, the polarization data of the ferroelectric capacitor of Cb is read to the bit line, and PL is set to the high amplitude high level. Then, the paraelectric capacitor component is eliminated, and then the sensing operation is performed, and PL is set to the Vss level in order to rewrite data. Then, BS0 is set to Low, and the bit line is precharged to a high level with a small amplitude. Set BS0 to High for the third time. Ca can be rewritten only by changing PL from the Vss level to a high level with a small amplitude. In addition, as shown by the line (1) in the figure, it is possible to omit raising WL02 from the first time to the third time.
[0136]
(Eighteenth embodiment)
FIG. 33 is an operation timing chart for explaining the operation of the FRAM according to the eighteenth embodiment of the present invention. This shows a combination of a bit line and plate line reverse precharge method and a double plate method.
[0137]
In FIG. 33, for reading Ca, a method is applied in which the bit line is precharged to a high level with a small amplitude, and the plate line is precharged in reverse to Vss. This is done after precharging and the double plate method is applied. In rewriting Ca, rewriting is performed by raising and lowering the plate. The feature of this embodiment is that the raising and lowering of BS0 and WL02 can be omitted between the first time and the third time.
[0138]
(Nineteenth embodiment)
FIG. 34 is an operation timing chart for explaining the operation of the FRAM according to the nineteenth embodiment of the present invention. This shows a combination of a bit line and plate line reverse precharge method and a double plate method.
[0139]
In FIG. 34, for reading Ca, a method is used in which the plate line is precharged to a high level with a small amplitude and the bit line is precharged in reverse to Vss. This is done after precharging and the double plate method is applied. In rewriting Ca, rewriting is performed only by raising the plate. The feature of this embodiment is that the raising and lowering of BS0 and WL02 can be omitted between the first time and the third time.
[0140]
(20th embodiment)
FIG. 35 is a diagram showing other problems in the prior application. One memory cell of the prior application is configured by parallel connection of a cell transistor and a ferroelectric capacitor, and one memory cell block is reverse to the read data in a configuration in which a plurality of parallel-connected memory cells are connected in series. When writing data, in a non-selected memory cell in a selected cell block, in principle, a non-selected ferroelectric capacitor is short-circuited by a non-selected ON cell transistor to maintain a stable state. It should be. However, in practice, due to the presence of the ON resistance of the non-selected cell transistor, a voltage is applied across the non-selected ferroelectric capacitor for a short time.
[0141]
The prior application states that this noise is reduced when the number of memory cells in the cell block is increased, but this is not sufficient. FIG. 35 shows the noise relationship and the rise / fall transition time of the bit line at the time of reverse data writing of the prior application. As described above, in order to safely hold the non-selected memory cell data, it is necessary to always increase the write time to some extent.
[0142]
FIG. 36 is for explaining the twentieth embodiment of the present invention which solves the above problem, and shows a write time relaxation method. Here, two methods are included.
[0143]
In the first method, transistors (Q9, Q10) are inserted between bit lines (BBL, BL) in the memory cell array and bit lines (BBLSA, BLSA) in the sense amplifier section. When writing reverse data from the write buffer of the main amplifier (Main Amp), the flip-flop of the sense amplifier section is inverted through the BDQ and DQ lines, and the inverted data is written to BBL and BL. . In this case, the transition time for writing BBL and BL is reduced by the RC time constant between the ON resistance of the transistors (Q9 and Q10) and the capacity of the bit lines (BBL and BL) on the cell array side having a large capacity. Thereby, noise can be reduced.
[0144]
In the second method, when writing reverse data from the write buffer of the main amplifier (Main Amp), the write buffer has two or more types of drivers having different driving capabilities, and each of the two or more types of drivers. This is a method of shifting the time for driving. In the example of this embodiment, the BDQ and DQ lines are first driven with a weak driving force by a driver having a small driving capability, and the high level of the bit lines (BBLSA, BLSA, BBL, BL) is lowered to a certain level and the Low level is raised. Next, the time is shifted, a large driver is driven, the bit line is inverted, and the bit line is gently inverted to perform data writing, thereby reducing the above-described writing noise.
[0145]
In addition, it is effective to use three or more types of buffers or to use buffers of the same size while shifting the time. Furthermore, using one type of buffer, the gate voltage of the buffer drive transistor may be increased gradually or in stages, and before the reverse data is written, the BDQ, DQ or bit line is once shorted. Then, reverse data may be written, or the above methods may be combined.
[0146]
(21st Embodiment)
FIG. 37 is a diagram for explaining a twenty-first embodiment of the present invention. This shows a more specific configuration example of the write buffer of FIG. FIG. 37 (a) shows two types of clocked inverters having different transistor sizes, and FIG. 37 (b) shows an example of a delay circuit of a signal line that is driven by delaying the time. FIG. 37 (c) shows these timing charts.
[0147]
(Twenty-second embodiment)
FIG. 38 is a diagram for explaining an FRAM according to the twenty-second embodiment of the present invention, and shows a specific layout diagram of a memory cell block that realizes an equivalent circuit of the embodiment of FIG. In FIG. 38, the bit line (M2 layer), word line (GC layer), diffusion layer (AA layer), cell wiring layer (MI layer), ferroelectric capacitor lower electrode (BE layer), upper electrode (TE layer) , D-type transistor ion implantation layer layer (Dimp layer), M1-M2 contact, TE-M1 contact, and BE-M1 contact.
[0148]
39 and 40 are divided and displayed so that the layout in FIG. 38 can be easily understood. 41 shows a cross-sectional example between AA ', BB', CC ', and DD' in the layout of FIG. TE and BE are connected from the M1 layer formed thereon via a TE-M1 contact and a BE-M1 contact. The M1 layer is connected to the AA layer via the AA-M1 contact.
[0149]
As shown in FIG. 38, M2-M1 is connected to the AA-M1 contact and the M1-M2 contact via the M1 layer. 38 to 41, since the cell internal node connection wiring M1 is formed after the ferroelectric capacitor forming step, a resistance metal wiring can be applied, and this M1 wiring can also be applied to the plate wiring. Yes. In the plate drive system, metalization of the plate wiring is indispensable in order to drive a plate line with a large load capacity, but this cell structure can easily reduce the resistance of the plate wiring and shorten the plate drive time. Can be planned.
[0150]
In particular, in the configurations of FIGS. 38 to 41, M1 Al wiring or Cu wiring is possible, and the access time and cycle time can be greatly shortened. The main reason is that in conventional memory cells in which a cell transistor and a ferroelectric capacitor are connected in series, a plate wiring is required for each cell, and the wiring layer for connecting nodes inside the cell and the plate wiring layer are shared within the cell. This is a loss in terms of area, and if the plate line is constituted by a BE layer or the like without sharing it, the plate drive time is very long due to high resistance. Providing a metal wiring exclusively for the plate has a problem that the process cost increases.
[0151]
In the memory cell of the prior application, the number of plate wirings is 0.5 (shared with the neighbor) for each cell block, and only one or two. As shown in FIGS. 38 to 41, the M1 layer of the two plate lines PLBBL and PLBL can easily be connected to the lower electrode (BE) and the BE-M1 contact for each bit line as shown in FIG. An equivalent circuit can be realized. As shown in the cross-sectional view of FIG. 41, if the BE layer is connected to cell blocks adjacent in the bit line direction, sharing of the plate line between adjacent cell blocks can be easily realized.
[0152]
(23rd embodiment)
FIG. 42 is a diagram for explaining an FRAM according to the twenty-third embodiment of the present invention. In the layer configuration and device structure of FIG. 38, when plate separation is not performed, that is, the equivalent circuit of FIG. The specific layout figure of the memory cell block implement | achieved is shown. Except for the plate line and the periphery of the connecting portion, the effect is the same as in FIG.
[0153]
42 shows a bit line (M2 layer), a word line (GC layer), a diffusion layer (AA layer), a cell wiring layer (M1 layer), a ferroelectric capacitor lower electrode (BE layer), and an upper electrode (TE layer). ), A D-type transistor ion implantation layer layer (Dimp layer), an M1-M2 contact, a TE-M1 contact, and a BE-M1 contact.
[0154]
43 and 44 are displayed separately for easy understanding of the layout in FIG. 45 shows a cross-sectional example between AA ′ and BB ′ in the layout of FIG. TE and BE are connected from the M1 layer formed thereon via a TE-M1 contact and a BE-M1 contact. The M1 layer is connected to the AA layer via the AA-M1 contact.
[0155]
As shown in FIG. 38, M2-M1 is connected to the AA-M1 contact and the M1-M2 contact via the M1 layer. 42 to 45, since the cell internal node connection wiring M1 is formed after the ferroelectric capacitor forming step, low resistance metal wiring can be applied, and this M1 wiring can also be applied to plate wiring. Yes. In the plate drive system, metalization of the plate wiring is indispensable in order to drive a plate line having a large load capacity. However, in this cell structure, the resistance of the plate wiring can be easily reduced and the plate driving time can be shortened. .
[0156]
In particular, in the configurations of FIGS. 43 to 45, M1 Al wiring or Cu wiring is possible, and the access time and cycle time can be greatly shortened. The main reason is that in a conventional memory cell in which a cell transistor and a ferroelectric capacitor are connected in series, a plate line is required for each cell, and the cell internal node connection wiring layer and the plate wiring layer are shared in the cell. This is a loss in terms of area, and if the plate line is constituted by a BE layer or the like without sharing it, the plate drive time is very long due to high resistance. Providing a metal wiring exclusively for the plate has a problem that the process cost increases.
[0157]
In the memory cell of the prior application, the number of plate wirings is 0.5 (shared with the adjacent) or one for each cell block. If the M1 layer of one plate line PL has a BE-M1 contact with the lower electrode (BE) as in the plate wiring portion of FIGS. 43 to 45, the equivalent circuit of FIG. 79 can be easily realized. As shown in the cross-sectional view of FIG. 45, if the BE layer is connected to cell blocks adjacent in the bit line direction, sharing of plate lines between adjacent cell blocks can be easily realized.
[0158]
(24th Embodiment)
46 is a view for explaining an FRAM according to the twenty-fourth embodiment of the present invention. In the layer configuration and device structure of FIG. 38, plate separation is not performed as in FIG. The specific layout figure of the memory cell block which implement | achieves 79 equivalent circuits is shown. The effect is also the same as in FIG. 46 shows a bit line (M2 layer), a word line (GC layer), a diffusion layer (AA layer), a cell wiring layer (M1 layer), a ferroelectric capacitor lower electrode (BE layer), and an upper electrode (TE layer). , D-type transistor ion implantation layer layer (Dimp layer), M1-M2 contact, TE-M1 contact, and BE-M1 contact.
[0159]
47 and 48 are displayed separately for easy understanding of the layout in FIG. The difference from FIG. 42 is that, as shown in FIG. 46, the cell block connected to the bit line BBL is the same as that of FIG. 42. In the cell block connected to the bit line BL, The point of (BE) is shifted in the bit line direction by one cell. Compared with FIG. 42, since the distance between the lower electrode, the upper electrode, and the contacts between adjacent cell blocks is longer in FIG. 46, when the cell size is regulated by these rules, FIG. In this case, the cell size can be reduced.
[0160]
(25th Embodiment)
FIG. 49 is a diagram for explaining the FRAM according to the twenty-fifth embodiment of the present invention, and shows a specific layout diagram for realizing the equivalent circuit of the dummy cell block of the embodiment of FIG. The layer configuration and cell structure are the same as those in FIG. 49 shows a bit line (M2 layer), a word line (GC layer), a diffusion layer (AA layer), a cell wiring layer (M1 layer), a ferroelectric capacitor lower electrode (BE layer), and an upper electrode (TE layer). ), A D-type transistor ion implantation layer layer (Dimp layer), an M1-M2 contact, a TE-M1 contact, and a BE-M1 contact.
[0161]
50 and 51 are divided and displayed so that the layout in FIG. 49 can be easily understood. 49 to 51, since the cell internal node connection wiring M1 is formed after the ferroelectric capacitor forming process, a low resistance metal wiring can be applied. This M1 wiring is used as a plate wiring for a dummy cell block. Can also be applied to drive the dummy cell plate at high speed.
[0162]
(26th Embodiment)
FIG. 52 is a diagram for explaining an FRAM according to the twenty-sixth embodiment of the present invention, and shows a specific layout diagram of a memory cell block that realizes an equivalent circuit of the embodiment of FIG. 52 shows a bit line (M2 layer), a word line (GC layer), a diffusion layer (AA layer), a cell wiring layer (M1 layer), a ferroelectric capacitor lower electrode (BE layer), and an upper electrode (TE layer). , D-type transistor ion implantation layer layer (Dimp layer), M1-M2 contact, TE-M1 contact, and BE-M1 contact.
[0163]
53 and 54 are divided and displayed so that the layout in FIG. 52 can be easily understood.
[0164]
FIG. 55 shows a cross-sectional example between AA ', BB', CC ', and DD' in the layout of FIG. TE and BE are connected from the M1 layer formed thereon via a TE-M1 contact and a BE-M1 contact. The M1 layer is connected to the AA layer via the AA-M1 contact. As shown in FIG. 52, M2-M1 is connected to the AA-M1 contact and the M1-M2 contact via the M1 layer.
[0165]
52 to 55, since the cell internal node connection wiring M1 is formed after the ferroelectric capacitor forming step, a low-resistance metal wiring can be applied, and the plate drive speed can be increased. 52 to 55, the D-type ion implantation mask is not necessary. This is because, as shown in FIG. 55, the source and drain of the passing block selection transistor are connected using the M1 wiring. Since there is no inversion layer capacitance of the D-type transistor, there is an effect that the bit line capacitance of the non-selected cell block portion is reduced. Further, as shown in FIG. 55, if the passing block selection transistor is changed to a field transistor, the capacitance can be further reduced.
[0166]
(Twenty-seventh embodiment)
FIG. 56 is a cross-sectional view showing the configuration of the memory cell block of the FRAM according to the twenty-seventh embodiment of the present invention. The equivalent circuit is the same as FIG. On the word line, metal wiring such as Al and Cu (Metal 1 in the figure) is arranged at the same pitch, and shunts (also referred to as snaps) are taken at regular intervals from the word line. Delay can be reduced. The metal wiring for the word line shunt can be used as it is as plate wiring. Furthermore, by connecting the upper electrode with the adjacent cell block, PLBBL and PLBL are shared by the adjacent cell block.
[0167]
FIG. 56 shows an example of the method of FIG. 3 in which the plate is divided into two types, PLBBL and PLBL. The upper diagram (a) and the lower diagram (b) in the figure alternate for each bit line, or alternate for every two bit lines. This can reduce the plate drive delay without increasing the process cost. Even if it is applied to the method of fixing the plate to (1/2) Vdd, it can contribute to the stabilization of the potential of the plate electrode.
[0168]
(Twenty-eighth embodiment)
FIG. 57 is a cross-sectional view showing the configuration of the memory cell block of the FRAM according to the twenty-eighth embodiment of the present invention. The equivalent circuit is the same as FIG. The difference from FIG. 56 is that the formation process of the metal wiring for metal (Bit2) and the metal wiring (Metal1) is reversed.
[0169]
(Twenty-ninth embodiment)
FIG. 58 is a sectional view showing the structure of the memory cell block of the FRAM according to the twenty-ninth embodiment of the present invention. The equivalent circuit is the same as FIG. The difference from FIG. 56 is that a ferroelectric capacitor is formed after forming the bit line layer, and a metal wiring layer for both word line shunt and plate wiring is formed after that.
[0170]
(Thirty embodiment)
FIG. 59 is a cross-sectional view showing the configuration of the memory cell block of the FRAM according to the thirtieth embodiment of the present invention. The equivalent circuit is the same as FIG. The difference from FIG. 58 is the case where the hierarchical word line method is adopted using the main row decoder and the sub row decoder instead of using the word line shunt method. Thereby, the metal wiring (Metal1) is used as the main word line, and the pitch of Metal1 can be relaxed to 2 to 8 times the word line pitch. (4 times in the example in the figure). Of course, also in this example, the main word line and the plate wiring can share the same Metal1.
[0171]
(Thirty-first embodiment)
FIG. 60 is a cross-sectional view showing the configuration of the memory cell block of the FRAM according to the thirty-first embodiment of the present invention. This is an example in which a metal wiring for word line shunt (Metal1) is employed in the equivalent circuit of FIG. Even in this case, Metal1 can be used for the plate wiring.
[0172]
The two lower figures in FIG. 60 show cross-sectional views (AA ′ and BB ′) in the word line direction when cut at two locations (word line portion and plate portion) in the upper drawing. The word line is in contact with the word line layer and the Metal1 layer at the shunt portion, and the plate portion is in contact with Metal1 and the plate electrode for each bit line.
[0173]
(Thirty-second embodiment)
FIG. 61 is a cross-sectional view showing the configuration of the memory cell block of the FRAM according to the thirty-second embodiment of the present invention. This is an example in which a metal wiring for word line shunt (Metal1) is employed in the equivalent circuit of FIG. The difference from FIG. 60 is that a bit line layer is formed between Metal 1 and the ferroelectric capacitor. Even in this case, Metal1 can be used for the plate wiring.
[0174]
The lower two diagrams of FIG. 61 show cross-sectional views (AA ′ and BB ′) in the word line direction when cut at two locations (word line portion and plate portion) in the upper diagram. The word line is in contact with the word line layer and Metal1 at the shunt portion, and the plate portion is also in contact with Metal1 and the plate electrode at the shunt portion.
[0175]
(Thirty-third embodiment)
62 and 63 are cross-sectional views showing the structure of the memory cell block of the FRAM according to the thirty-third embodiment of the present invention.
[0176]
FIG. 62 shows a case where a hierarchical word line and a metal wiring layer (CSL) for a column selection line are added in the equivalent circuit of FIG. Of course, the plate separation method of FIG. 3 can also be realized. FIG. 63 shows the equivalent circuit of FIG. 79 in which a word line shunt method and a metal wiring layer (CSL) for column selection lines are further added. Of course, the plate separation method of FIG. 3 can also be realized.
[0177]
(Thirty-fourth embodiment)
FIG. 64 is a cross-sectional view showing the cell structure of the FRAM according to the thirty-fourth embodiment of the present invention. The examples of FIGS. 56 to 63 show only the conceptual illustration of the structure and wiring connection of the ferroelectric capacitor unit, but FIGS. 64A to 64F of the present embodiment show examples of FIGS. The detailed wiring structure of the ferroelectric capacitor part applicable to the prior application example is shown.
[0178]
(A) shows an example in which the upper electrode 62 is formed on the ferroelectric film 61 and then the wiring 63 for connecting the cell transistor and the upper electrode is formed. (B) shows an example in which, in addition to (a), after formation of a transistor, a plug 64 such as a Si plug or a W plug is formed, and a lower electrode 65 is formed thereon. (C) shows an example in which, in addition to (b), a barrier layer 66 is formed between the plug and the lower electrode 65 to prevent the ferroelectric material from diffusing.
[0179]
In the examples of (a) to (c), after the upper electrode 62 is formed, an insulating film is applied, and the connection between the upper electrode 62 and the wiring 63 is performed after the contact opening with the cell transistor or before the opening, etch back or CMP. In this way, the insulating film is removed to expose the upper electrode to form the wiring 63, and the wiring 63 and the upper electrode 62 are connected to each other. On the other hand, in the example of (d), after the insulating film is formed, contact holes are opened on the upper electrode and the diffusion layer of the cell transistor, and are connected by the wiring 63.
[0180]
In the example of (e), after the formation of the plug of (c), the plug 67 is also formed at the connection portion between the wiring 63 and the diffusion layer of the cell transistor to reduce the contact hole aspect ratio. In the example of (f), in addition to the example of (e), an example in which ferroelectric capacitor films are connected by adjacent cells is shown. This can be applied when the ratio of the ferroelectric film thickness / the distance between the upper electrodes is small or when the anisotropy of the polarization amount is large. In the examples of (a) to (f), the case where various modifications are sequentially added is shown, but the present invention is not limited to this, and various modifications can be freely combined.
[0181]
(Thirty-fifth embodiment)
65 to 68 are cross-sectional views showing the configuration of the memory cell block of the FRAM according to the thirty-fifth embodiment of the present invention.
[0182]
FIG. 65 shows a case where adjacent cell nodes are formed simultaneously and a ferroelectric capacitor is formed between them in the equivalent circuit of FIG. FIG. 66 shows a case where adjacent cell nodes are formed at the same time and a ferroelectric capacitor is formed between them in the equivalent circuit of FIG. 79, and further, metal wiring for both word line shunt and plate wiring is formed.
[0183]
FIG. 67 is the equivalent circuit of FIG. 4 in which adjacent cell nodes are formed at the same time and a ferroelectric capacitor is formed between them, and further, a main word line of a hierarchical word line and a metal wiring combined with plate wiring are formed. Indicates. FIG. 68 is an equivalent circuit of FIG. 79 in which adjacent cell nodes are formed at the same time and a ferroelectric capacitor is formed between them, and further, a main word line of a hierarchical word line and a metal wiring combined with plate wiring are formed. Indicates.
[0184]
(Thirty-sixth embodiment)
FIG. 69 is a diagram for explaining an FRAM according to a thirty-sixth embodiment of the present invention, and shows a memory cell array and a plate driving circuit block. This can be applied to the method of FIG. Since two plate driving circuits are required for one cell block and the plate lines are shared by adjacent cell blocks, only one plate driving circuit is required for one cell block after all. As in the conventional divided plate system, the number of plate driving circuits can be greatly reduced for one word line as compared with the case where one plate driving line is required, and the chip size can be reduced.
[0185]
Furthermore, the plate driving delay can be further reduced in the present embodiment in addition to the plate delay reducing effect due to the significant reduction of the plate wiring resistance shown in FIGS. The plate delay is determined by the RC delay of the load capacitance and the resistance, and the load capacitance is determined by the capacitance of the ferroelectric capacitor having a larger capacity than the parasitic capacitance in the cell. In other words, the load capacity is not changed between the conventional cell, the prior application in which a plurality of cells are connected in series, and the cell of the present invention. This is because in the prior application and the cell of the present invention, the non-selected cell is short-circuited and the capacity cannot be seen. In comparison, the resistance component is determined by the wiring resistance of the plate line and the ON resistance of the driver transistor at the final stage of plate line driving of the plate driving circuit.
[0186]
In the present embodiment, it is possible to increase the size of the driver transistor of the plate driving circuit by reducing the resistance of the plate line wiring and greatly reducing the plate driving circuit, and to significantly reduce the ON resistance. . Eventually, the RC delay C is almost unchanged, and R can be greatly reduced.
[0187]
(Thirty-seventh embodiment)
FIG. 70 is for explaining an FRAM according to the thirty-seventh embodiment of the present invention, and shows a memory array, a row decoder, and a plate driving circuit. This embodiment can be applied to the case where the plate is driven by the 2T / 2C method in which the plates are not separated. In this case, compared to FIG. 69, the number of plate driving circuits can be halved, and the number of plate driving circuits can be arranged at a ratio of one in two cell blocks, the driver transistor size of the plate driving circuit can be increased, and further speedup can be realized.
[0188]
(Thirty-eighth embodiment)
FIG. 71 is a diagram showing a circuit configuration of an FRAM according to the thirty-eighth embodiment of the present invention. This shows a case where the nMOS and the pMOS are configured in parallel instead of the conventional nMOS as the memory cell transistor and the block selection transistor.
[0189]
With such a configuration, the word line and the block selection line can be operated without increasing the voltage to Vdd or more, and this is effective when used as a low voltage operation or as a mixed memory with logic or others. In this example, a method of storing 1-bit data with two ferroelectric capacitors is shown, and there is one type of block selection line. Note that / WLi and WLi, and / BS and BS are complementary signals of reverse voltages.
[0190]
(39th Embodiment)
FIG. 72 is a diagram showing a circuit configuration of the FRAM according to the thirty-ninth embodiment of the present invention. This shows a case where the nMOS and the pMOS are configured in parallel instead of the conventional nMOS as the memory cell transistor and the block selection transistor.
[0191]
With such a configuration, it is possible to operate without boosting the word line and the block selection line to Vdd or higher, which is effective when used as a low voltage operation or as a mixed memory with logic and others. In this example, a single ferroelectric capacitor stores 1 bit of data, and there are two types of block selection lines. Note that / WLi and WLi, and / BS and BS are complementary signals of reverse voltages. One type of plate line as shown in FIG. 79 ((1/2) Vdd fixed plate type) and two types of plate lines as shown in FIG. 4 (plate driving type) can be applied.
[0192]
(40th embodiment)
FIG. 73 is a diagram showing a circuit configuration of the FRAM according to the fortieth embodiment of the present invention. This shows the case of a small memory in which the cell block has only one array in the word line direction. In this case, the block selection transistor can be omitted.
[0193]
The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the invention.
[0194]
【The invention's effect】
As described above in detail, according to the present invention, it is non-volatile, can be easily manufactured with a planar transistor, and while maintaining a random accelerator function, 4F²While realizing high integration of size, (1) 1T / 1C type, plate driving method can be applied, and high voltage and low voltage operation is possible. Further, (2) high-speed operation is possible while suppressing variations in the paraelectric component of the ferroelectric capacitor. Furthermore, (3) noise during writing can be reduced. Furthermore, (4) the plate driving method also enables high-speed operation while keeping the process cost and chip size small. (5) Furthermore, boosting of the word lines and block selection lines can be made unnecessary by making the cells CMOS.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram showing an FRAM according to a first embodiment.
FIG. 2 is a timing chart showing a specific operation example of the first embodiment.
FIG. 3 is a circuit configuration diagram showing an FRAM according to a second embodiment.
4 is a circuit configuration diagram showing a modified example of FIG. 3;
FIG. 5 is a circuit configuration diagram showing an FRAM according to a third embodiment.
6 is a timing chart showing an operation example of the configuration of FIG.
FIG. 7 is a circuit configuration diagram showing an FRAM according to a fourth embodiment.
FIG. 8 is a timing chart showing an operation example of the configuration of FIG.
FIG. 9 is a circuit configuration diagram showing an FRAM according to a fifth embodiment.
FIG. 10 is a circuit configuration diagram showing an FRAM according to a sixth embodiment.
FIG. 11 is a timing chart showing an operation example of the configuration of FIGS. 9 and 10;
FIG. 12 is a circuit configuration diagram showing an FRAM according to a seventh embodiment.
13 is a timing chart showing an operation example of the configuration of FIG.
FIG. 14 is a timing chart showing the operation method of the FRAM according to the eighth embodiment.
FIG. 15 is a circuit configuration diagram showing the configuration of the 2T / 2C system of the prior application.
FIG. 16 is a timing chart showing the operation of the ninth embodiment.
FIG. 17 is a diagram showing a configuration of a sense amplifier section of an FRAM according to a tenth embodiment.
FIG. 18 is a diagram showing a configuration of a sense amplifier section of an FRAM according to an eleventh embodiment.
FIG. 19 is a cell block equivalent circuit diagram of a multi-bit / cell system in the prior application.
20 is a diagram showing an example of a cross section of the cell structure of FIG. 19;
FIG. 21 is a diagram showing a hysteresis curve in the multi-bit / cell operation of FIG. 19;
FIG. 22 is a diagram showing an actual hysteresis curve.
FIG. 23 is a sectional view showing a memory cell block configuration of an FRAM according to a twelfth embodiment;
FIG. 24 is a timing chart showing a specific operation example of multi-bit / cell operation when the plate driving method described in the previous application is applied.
FIG. 25 is a timing chart showing the operation of the thirteenth embodiment.
FIG. 26 is a diagram showing a core part circuit configuration for explaining a fourteenth embodiment;
FIG. 27 is a diagram showing a core part circuit configuration for explaining a fourteenth embodiment;
FIG. 28 is a timing chart showing the operation of the fifteenth embodiment.
FIG. 29 is a timing chart showing the operation of the sixteenth embodiment.
FIG. 30 is a timing chart showing the operation of the sixteenth embodiment.
FIG. 31 is a timing chart showing the operation of the seventeenth embodiment.
FIG. 32 is a timing chart showing the operation of the seventeenth embodiment.
FIG. 33 is a timing chart showing the operation of the eighteenth embodiment.
FIG. 34 is a timing chart showing the operation of the nineteenth embodiment.
FIG. 35 is a diagram showing other problems in the prior application.
FIG. 36 is a diagram showing a write time relaxation method in the twentieth embodiment;
FIG. 37 is a diagram showing a more specific configuration example of a write buffer according to the twenty-first embodiment.
FIG. 38 is a specific layout diagram of a memory cell block for realizing the twenty-second embodiment and realizing the equivalent circuit of the embodiment of FIG. 3;
FIG. 39 is a diagram showing the layout in FIG. 38 separately for easy understanding.
FIG. 40 is a diagram showing the layout in FIG. 38 separately for easy understanding.
41 is a diagram showing a cross-sectional example between AA ′, BB ′, CC ′, and DD ′ in the layout of FIG. 38;
FIG. 42 is a specific layout diagram of the memory cell block of the FRAM according to the twenty-third embodiment.
43 is a diagram showing the layout in FIG. 42 separately for easy understanding.
44 is a diagram showing the layout in FIG. 42 separately for easy understanding.
45 is a diagram showing a cross-sectional example between AA ′ and BB ′ in the layout of FIG. 42;
FIG. 46 is a specific layout diagram of the memory cell block of the FRAM according to the twenty-fourth embodiment.
47 is a diagram showing the layout in FIG. 46 separately for easy understanding.
FIG. 48 is a diagram showing the layout in FIG. 46 separately for easy understanding.
49 is a specific layout diagram for realizing the equivalent circuit of the dummy cell block of FIG. 5 for describing the FRAM according to the twenty-fifth embodiment.
FIG. 50 is a diagram showing the layout in FIG. 49 separately for easy understanding.
FIG. 51 is a diagram showing the layout in FIG. 49 separately for easy understanding.
52 is a specific layout diagram of a memory cell block for realizing the equivalent circuit of FIG. 4 for describing an FRAM according to a twenty-sixth embodiment;
FIG. 53 is a diagram showing the layout in FIG. 52 separately for easy understanding.
54 is a diagram showing the layout in FIG. 52 separately for easy understanding.
FIG. 55 is a diagram showing a cross-sectional example between AA ′, BB ′, CC ′, and DD ′ in the layout of FIG. 52;
FIG. 56 is a cross-sectional view showing a configuration example of a memory cell block of an FRAM according to a twenty-seventh embodiment. .
57 is a sectional view showing a configuration example of a memory cell block of the FRAM according to the twenty-eighth embodiment; FIG.
58 is a sectional view showing a configuration example of a memory cell block of an FRAM according to a twenty-ninth embodiment; FIG.
FIG. 59 is a cross-sectional view showing a configuration example of a memory cell block of an FRAM according to the thirtieth embodiment.
60 is a cross-sectional view showing a configuration example of a memory cell block of the FRAM according to the thirty-first embodiment; FIG.
61 is a sectional view showing a configuration example of a memory cell block of an FRAM according to a thirty-second embodiment; FIG.
FIG. 62 is a sectional view showing a configuration example of a memory cell block of an FRAM according to the thirty-third embodiment;
FIG. 63 is a sectional view showing a configuration example of a memory cell block of an FRAM according to a thirty-third embodiment;
FIG. 64 is a sectional view showing the cell structure of the FRAM according to the thirty-fourth embodiment;
FIG. 65 is a cross-sectional view showing a configuration example of a memory cell block of an FRAM according to the thirty-fifth embodiment.
66 is a sectional view showing a configuration example of a memory cell block of an FRAM according to the thirty-fifth embodiment. FIG.
67 is a cross-sectional view showing a configuration example of a memory cell block of an FRAM according to a thirty-fifth embodiment. FIG.
68 is a sectional view showing a configuration example of a memory cell block of an FRAM according to a thirty-fifth embodiment; FIG.
FIG. 69 is a diagram showing a configuration of an FRAM memory cell array and plate driving circuit according to a thirty-sixth embodiment;
FIG. 70 is a diagram showing a configuration of an FRAM memory array, row decoder, and plate driving circuit according to a thirty-seventh embodiment;
71 is a circuit configuration diagram showing an FRAM according to a thirty-eighth embodiment; FIG.
72 is a circuit configuration diagram showing an FRAM according to a thirty-ninth embodiment; FIG.
FIG. 73 is a circuit configuration diagram showing the FRAM according to the forty embodiment;
FIG. 74 is a diagram showing a conventional DRAM memory cell, a conventional FRAM memory cell, and a folded BL configuration;
75 is a graph showing the relationship between voltage and accumulated charge and the relationship between voltage and polarization amount; FIG.
FIG. 76 is a timing chart showing an operation example in a conventional FRAM.
FIG. 77 is a diagram for explaining the operation of a conventional FRAM;
78 is a diagram showing a configuration circuit and an operation example of a memory cell according to the invention of the prior application; FIG.
FIG. 79 is a diagram showing a configuration circuit and an operation example of a memory cell according to the invention of the prior application;
FIG. 80 is a diagram showing a configuration circuit and an operation example of a memory cell according to the invention of the prior application;
[Explanation of symbols]
BSi, BSij, / BSi ... block selection line
Pwell ... p-type well
n⁺... n-type diffusion layer
SA ... sense amplifier
Φti: Cell array-sense amplifier separation signal
EQL ... Bit line equal signal
CSL ... Column selection line
DWLi: Dummy word line
SEN: nMOS sense amplifier control line
/SEP...pMOS sense amplifier control line
Ci: Coupling capacity
VBL: Bit line precharge signal
DBSi ... Dummy cell block selection line
F ... Minimum processing dimension
Ps: Saturation Polarization
Pr: Remnat Polarization
Vc: Coercive Voltage
RST ... Reset line
WQni, WQmi ... Transistor channel width
BDQ, DQ ... Data line
WENB, / WENB, / WENBD, WENBD ... Data write control signal

Claims (29)

A memory cell is composed of a cell transistor having a word line as a gate electrode and a ferroelectric capacitor connected in parallel between the source and drain terminals of the cell transistor, and a plurality of the memory cells are connected in series, despite plurality connected in series constitute a memory cell block by connecting the memory cell block selection transistors in at least one end, one end of said memory cell block is connected to the bit line, the other end is connected to a plate line, the memory cell A semiconductor memory device in which a plurality of blocks are arranged to constitute a cell array ,
Two bit lines are paired and connected to the same sense amplifier circuit, and are connected to each of the two bit lines forming the pair and connected to the same word line group. Are connected to a first plate line and a second plate line of different signals, respectively. A memory cell is composed of a cell transistor having a word line as a gate electrode and a ferroelectric capacitor connected in parallel between the source and drain terminals of the cell transistor, and a plurality of the memory cells are connected in series, A memory cell block selection transistor is connected to at least one end of a plurality of serially connected memory cells to form a memory cell block. One end of the memory cell block is connected to a bit line and the other end is connected to a plate line. A semiconductor memory device in which a plurality of blocks are arranged to constitute a cell array,
A semiconductor memory device, wherein a first plate line and a second plate line are alternately connected to each of the plurality of memory cell blocks arranged in the word line direction. A memory cell is composed of a cell transistor having a word line as a gate electrode and a ferroelectric capacitor connected in parallel between the source and drain terminals of the cell transistor, and a plurality of the memory cells are connected in series. A memory cell block selection transistor is connected to at least one end of a plurality of serially connected memory cells to form a memory cell block. One end of the memory cell block is connected to a bit line and the other end is connected to a plate line. A semiconductor memory device in which a plurality of blocks are arranged to constitute a cell array,
A semiconductor memory device, wherein a first plate line and a second plate line are alternately connected to every two of the memory cell blocks arranged in the word line direction every two.   4. The semiconductor memory device according to claim 1, wherein each of the first and second plate lines is shared by two memory cell blocks adjacent in the bit line direction. A semiconductor memory device.   4. The semiconductor memory device according to claim 1, wherein the first and second plate lines are at a potential of 0 V during standby after power is turned on.   4. The semiconductor memory device according to claim 1, wherein the first and second plate lines are at a first potential higher than 0 V during standby after power is turned on. Semiconductor memory device.   4. The semiconductor memory device according to claim 1, wherein the bit line is at a potential of 0 V during standby after power-on.   4. The semiconductor memory device according to claim 1, wherein the bit line is at a first potential higher than 0V during standby after power-on.   4. The semiconductor memory device according to claim 1, wherein during one cycle operation, one of the first plate line and the second plate line connected to the selected memory cell block is: A semiconductor memory device, wherein an amplitude operation is performed in a range of 0 V potential to a first potential higher than 0 V potential, and the other remains at 0 V potential.   4. The semiconductor memory device according to claim 1, wherein during one cycle operation, one of the first plate line and the second plate line connected to the selected memory cell block is: A semiconductor memory device, wherein a potential different from that during standby is applied and the same potential as that during standby is applied to the other.   4. The semiconductor memory device according to claim 1, wherein during one cycle operation, one of the first plate line and the second plate line connected to the selected memory cell block is: A semiconductor memory device, wherein the semiconductor memory device is driven from a 0 V potential to a first potential higher than 0 V, then driven from the first potential to 0 V, and the other remains at a 0 V potential.   4. The semiconductor memory device according to claim 1, wherein during one cycle operation, one of the first plate line and the second plate line connected to the selected memory cell block is: A semiconductor memory device, wherein the semiconductor memory device is driven from a first potential higher than 0 V potential to 0 V potential, then driven from 0 V potential to the first potential, and the other is kept at the first potential. A memory cell is formed from a cell transistor and a ferroelectric capacitor connected in parallel between the source and drain terminals of the cell transistor, and a plurality of the memory cells are connected in series to form a memory cell block. A semiconductor storage device comprising a cell array in which a plurality of cell blocks are arranged, and a write buffer for writing data to the memory cell from the outside,
The write buffer includes a first write transistor and a second write transistor having a driving force larger than that of the first write transistor, and at the time of writing, the second write transistor is compared with the time for starting driving the first write transistor. A semiconductor memory device characterized in that a time for starting driving a transistor is delayed. A memory cell is composed of a cell transistor having a word line as a gate electrode and a ferroelectric capacitor connected in parallel between the source and drain terminals of the cell transistor, and a plurality of the memory cells are connected in series, A memory cell block is formed by connecting a memory cell block selection transistor to at least one end of a plurality of serially connected ones, and one end of the memory cell block is connected to a bit line and the other end is connected to a plate line. A device,
The semiconductor memory device, wherein the plate line is formed of the same metal wiring layer as a metal wiring layer connecting the cell transistor and the ferroelectric capacitor.   15. The semiconductor memory device according to claim 14, wherein the metal wiring layer is formed in an upper layer after the ferroelectric capacitor is formed, and is connected to an upper electrode or a lower electrode of the ferroelectric capacitor via a contact. A semiconductor memory device. A memory cell is composed of a cell transistor having a word line as a gate electrode and a ferroelectric capacitor connected in parallel between the source and drain terminals of the cell transistor, and a plurality of the memory cells are connected in series. A memory cell block is formed by connecting a memory cell block selection transistor to at least one end of a plurality of serially connected ones, and one end of the memory cell block is connected to a bit line and the other end is connected to a plate line. A device,
The plate line is formed of the same metal wiring layer as the first metal wiring layer for word line snap that is formed above the gate wiring layer of the word line and contacts the gate wiring layer at first intervals. A semiconductor memory device characterized in that contacts are made with the wiring layer at every second interval.   17. The semiconductor memory device according to claim 16, wherein a contact interval between the first metal wiring layer and the plate line wiring layer is 1 bit line, 2 bit lines, 4 bit lines, or a word line snap interval. A semiconductor memory device, characterized in that A memory cell is composed of a cell transistor having a word line as a gate electrode and a ferroelectric capacitor connected in parallel between the source and drain terminals of the cell transistor, and a plurality of the memory cells are connected in series. A memory cell block selection transistor is connected to at least one end of a plurality of serially connected memory cells to form a memory cell block. One end of the memory cell block is connected to a bit line and the other end is connected to a plate line. A semiconductor memory device in which a plurality of blocks are arranged to constitute a cell array,
2. A semiconductor memory device according to claim 1, wherein a drive circuit for driving the plate line is arranged for each one or every two of the memory cell blocks in the bit line direction.   An nMOS transistor, a pMOS transistor, and a ferroelectric capacitor constitute a memory cell, the source of the nMOS transistor, the source of the pMOS transistor, and one end of the ferroelectric capacitor are connected, and the drain of the nMOS transistor and the pMOS transistor A drain of the semiconductor memory device and the other end of the ferroelectric capacitor are connected.   20. The semiconductor memory device according to claim 19, wherein a plurality of the memory cells are connected in series to constitute a memory cell block.   21. The semiconductor memory device according to claim 20, wherein one end of the memory cell block is connected to a bit line via at least one memory cell block selection transistor, and the other end is connected to a plate line. Semiconductor memory device.   22. The semiconductor memory device according to claim 21, wherein the nMOS transistor and the pMOS transistor of the memory cell are connected to word lines of different signals. A memory cell is composed of a cell transistor having a word line as a gate electrode and a ferroelectric capacitor connected in parallel between the source and drain terminals of the cell transistor, and a plurality of the memory cells are connected in series. A memory cell block selection transistor is connected to at least one end of a plurality of serially connected ones to form a memory cell block, and a plurality of the memory cell blocks are arranged to form a cell array. One end of the memory cell block is connected to a bit line. is, the other end is connected to a plate line, a further and Sabouraud decoder connected to the word line, semi conductor memory device Ru comprising a main word line connected to the sub-row decoder,
The semiconductor memory device, wherein the main word line is formed of the same wiring layer as the metal wiring layer of the plate line.   24. The semiconductor memory device according to claim 23, wherein one main word line is provided for each memory cell block. 4. The semiconductor memory device according to claim 1, wherein the ferroelectric capacitor film is formed in a direction perpendicular to a surface of a wafer on which the cell transistor is formed . A memory cell is composed of a cell transistor and a ferroelectric capacitor connected in parallel between the source and drain terminals of the cell transistor, and a plurality of the memory cells are connected in series, and at least of the plurality of the series connected A semiconductor memory device in which a memory cell block selection transistor is connected to one end to form a memory cell block,
A first contact connecting the lower electrode of the ferroelectric capacitor and the source terminal; a first metal wiring layer connected from the upper electrode of the ferroelectric capacitor via a second contact; and the drain terminal. 3. A semiconductor memory device, comprising: a third contact to be connected, wherein at least a part of the first contact and the third contact are formed by the same process. A memory cell is composed of a cell transistor and a ferroelectric capacitor connected in parallel between the source and drain terminals of the cell transistor, and a plurality of the memory cells are connected in series, and at least of the plurality of the series connected A semiconductor memory device in which a memory cell block selection transistor is connected to one end to form a memory cell block,
A first contact connecting the lower electrode of the ferroelectric capacitor and the source terminal; a first metal wiring layer connected from the upper electrode of the ferroelectric capacitor via a second contact; and the drain terminal. A semiconductor memory device comprising: a third contact to be connected, wherein the first contact and the third contact are made of different materials. A memory cell is composed of a cell transistor and a ferroelectric capacitor connected in parallel between the source and drain terminals of the cell transistor, and a plurality of the memory cells are connected in series, and at least of the plurality of the series connected A semiconductor memory device in which a memory cell block selection transistor is connected to one end to form a memory cell block,
A first contact connecting the lower electrode of the ferroelectric capacitor and the source terminal; a first metal wiring layer connected from the upper electrode of the ferroelectric capacitor via a second contact; and the drain terminal. 3. A semiconductor memory device comprising: a third contact to be connected, wherein the first contact and the third contact are formed by stacking at least two kinds of different materials . A memory cell is composed of a cell transistor and a ferroelectric capacitor connected in parallel between the source and drain terminals of the cell transistor, and a plurality of the memory cells are connected in series, and at least of the plurality of the series connected A semiconductor memory device in which a memory cell block selection transistor is connected to one end to form a memory cell block,
The semiconductor memory device, wherein the contact layer connecting the lower electrode of the ferroelectric capacitor and the source or drain terminal is formed by laminating at least two different material layers.

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