JP3946849B2 - Nonvolatile semiconductor memory device and erase method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electrically rewritable nonvolatile semiconductor memory device and an erasing method thereof.
[0002]
[Prior art]
In recent years, various flash memories using cell transistors having a floating gate structure have been proposed. In this type of flash memory, a thin insulating film of about 10 nm is interposed between the substrate and the floating gate, and writing and erasing are performed by injecting and extracting electrons through the insulating film. As the flash memory, a NOR type and a NAND type have already been developed. The NAND flash memory has an advantage that the size of the memory cell can be reduced as compared with the NOR type, and the cost is reduced. Further, the NAND flash memory has a feature that since a write current at the time of writing is small, a memory cell of several k bits can be simultaneously written and the writing speed is high. Various documents relating to the NAND flash memory are known. For example, U.S. Pat. S. P. 5,297,029 describe basic operations such as reading, writing, and erasing.
[0003]
FIG. 10 is a circuit diagram schematically showing a circuit portion related to a read operation of the memory cell and its periphery in the NAND flash memory described above.
In the NAND flash memory, current paths of a plurality of memory cells MC1 to MCn are connected in series, and a source select gate (select transistor) ST1 and a drain select gate are connected to the source end and drain end of the series connected current paths, respectively. (Selection transistor) ST2 is connected to each other to have a plurality of NAND bundles 11. The source end of the current path in the NAND bundle 11 is connected to the power supply Vss, and the drain end is connected to the bit line BL. Between the bit line BL and the voltage supply source VPR, a current path of a precharge transistor PT that is on / off controlled by a signal SA is connected. The bit line BL is connected to one end of a current path of a transistor DT that is on / off controlled by a signal SB, and the other end of the current path of the transistor DT is a sense amplifier constituted by inverters INV1 and INV2. It is connected to the register circuit 12.
[0004]
Although not shown, a plurality of NAND bundles are connected to the bit line BL in the row direction, a plurality of bit lines are arranged in the column direction, and a plurality of NAND bundles are arranged in the row direction on each of these bit lines. It is connected to the. Each bit line is connected to a precharge transistor PT, a transistor DT, and a sense amplifier register circuit 12 as in FIG.
[0005]
Word lines WL1 to WLn arranged in a direction orthogonal to the bit lines BL are connected to the control gates of the memory cells MC1 to MCn in the NAND bundle 11 for each row, and the gates of the selection transistors ST1 and ST2 are connected. The selection lines SGS and SGD are connected to each row. When the power supply voltage Vcc is applied to the selection lines SGS and SGD, the selection transistors ST1 and ST2 are turned on, and a group of NAND bundles arranged in the column direction is selected. The selected word line WLm (m is one of 1 to n) is 0 V, the unselected word line in the NAND bundle is the power supply voltage Vcc, in other words, the control gate of the selected memory cell. The power supply voltage Vcc is applied to the control gates of 0V and unselected memory cells. As a result, when the threshold voltage of the selected memory cell is positive, the memory cell is turned on, and when it is negative, the memory cell is turned off. On the other hand, 0V is supplied to the control gates of the memory cells of the non-selected NAND bundle and the gates of the non-selected selection transistors, respectively.
[0006]
In the above configuration, the read operation is performed as shown in the timing chart of FIG.
First, at the start of reading (time t0), the signal SA becomes “H” level (the signal SB is “L” level at this time), the precharge transistor PT is turned on, the transistor DT is turned off, and the bit line BL is turned on. Precharged with supply source VPR. After that, the signal SA becomes “L” level at time t1 and the precharge transistor PT is turned off, and the signal SB becomes “H” level and turns on the transistor DT at time t2. Depending on the threshold voltage of the memory cell (depending on whether the selected memory cell is in the write state or the erase state), the potential of the bit line BL changes. When the signal SB becomes “H” level at time t2, the transistor DT is turned on to connect the bit line BL and the sense amplifier register circuit 12, and the potential of the bit line BL is amplified and latched in the sense amplifier register circuit 12. .
[0007]
When electrons are injected into the floating gate of the selected memory cell MCm (write state), the threshold voltage of the memory cell MCm is high, and the memory cell MCm maintains the off state. Therefore, no current flows to the power source Vss through the NAND bundle selected from the bit line BL, and the potential of the bit line BL does not decrease. On the other hand, when electrons are extracted from the floating gate (erased state), the threshold voltage of the selected memory cell MCm is low, so that MCm is turned on (at this time, the non-selected state). The memory cell is also on). Therefore, a current flows from the bit line BL to the power supply Vss through the selected NAND bundle, and the potential of the bit line BL is lowered. The potential of the bit line BL at time t2 is supplied to the sense amplifier register circuit 12, and is latched as storage data of the selected memory cell MCm.
Here, the operation until the data stored in the memory cell MCm is latched in the sense amplifier register circuit 12 is defined as a page read operation.
[0008]
Normally, a sense amplifier register circuit 12 is connected to each bit line BL. In the case of a 16 Mbit NAND type EEPROM, about 2000 sense amplifier register circuits 12 are arranged. The operation of reading the memory cell data stored in the sense amplifier register circuit 12 to the outside is called a serial read operation, and a column gate transistor (not shown) connected to the sense amplifier register circuit 12 is selectively selected. By turning on, the contents of the sense amplifier register circuit 12 at a predetermined address can be read out to the outside.
[0009]
By the way, in the NAND flash memory as described above, when writing and erasing operations are repeated, electrons are trapped in the insulating film under the floating gate, and the threshold voltage of the memory cell after erasing becomes shallow ( Is approaching 0V). FIG. 12 shows the dependence of the threshold voltage on the number of writing and erasing after erasing the memory cell. According to FIG. 12, the threshold voltage of the memory cell after the erasing operation increases from the number of times of writing and erasing to about 100,000 times, and it becomes impossible to erase sufficiently deeply. come. Therefore, if an attempt is made to erase to a threshold voltage of the same level as 100,000 or less after 1 million times of writing and erasing, it is necessary to lengthen the erasing time. For this reason, in the conventional NAND flash memory, there is a problem that when writing and erasing are repeated up to the wear region of the oxide film of the memory cell, the erasing time is significantly increased and cannot be used up to 1 million times in practice.
[0010]
FIG. 13 shows the relationship between the threshold voltage after erasing the memory cell and the page read time.
Normally, the bit line has a capacity of about several pF, and the read time is determined by the speed at which the charge stored in this capacity is discharged. The discharge speed depends on the threshold voltage of the erased memory cell. Therefore, if the read speed is set to be slow, a bit line capacitance of several pF can be discharged even with a small cell current, and even a memory cell with a shallow threshold voltage is determined to be in the erased state. Conversely, if the read speed is set high, a large cell current is required for discharging the bit line capacitance, and a deep threshold voltage is required to be regarded as an erased state.
[0011]
As described above, in order to prevent the erasing time from becoming long even after one million times of writing and erasing, the reading time is set to be long so that even a memory cell having a shallow threshold voltage is regarded as an erasing state. Just do it. However, if the reading speed is slowed down in advance in accordance with the shallow threshold voltage after 1 million times of writing and erasing, the access time to the memory chip becomes long and the performance of the NAND flash memory is deteriorated.
[0012]
[Problems to be solved by the invention]
As described above, the conventional nonvolatile semiconductor memory device and the erasing method thereof have a problem that the threshold voltage of the memory cell after erasing becomes shallow when the writing and erasing operations are repeated, and the erasing time is significantly increased. .
[0013]
An object of the present invention is to provide a non-volatile semiconductor memory device and an erasing method thereof that can perform optimum erasing according to the number of times of writing and erasing, and can suppress an increase in erasing time as the number of erasing times increases. It is in.
[0014]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the present invention has taken the following measures.
A nonvolatile semiconductor memory device according to a first aspect of the present invention includes a plurality of blocks each including a plurality of NAND cells in which current paths of a plurality of nonvolatile memory cells that can be electrically written and erased are connected in series. A memory cell array, and a block erase circuit for simultaneously erasing the plurality of nonvolatile memory cells included in the plurality of blocks for each block; The number of erasures of the nonvolatile memory cell included in one block, By the block erase circuit The nonvolatile memory cell erased at the same time An erasure count storage section for storing the erasure count, and a read time setting circuit for extending the read time with an increase in the erasure count stored in the erasure count storage section when reading data stored in the nonvolatile memory cell, It is characterized by comprising. According to the first aspect, the nonvolatile semiconductor memory device stores the number of erase operations performed in the past in the erase number storage unit, and the readout time is controlled by the readout time setting circuit according to the number of erases. The read time can be set according to the number of times of writing and erasing of the semiconductor memory device, and an increase in the erasing time can be suppressed.
[0015]
In the nonvolatile semiconductor memory device according to the first aspect described above, preferred embodiments are as follows.
(1) The erase count storage unit includes an erase count counter that is incremented according to the erase count.
(2) The erasure count storage unit is assigned to a part of the plurality of blocks, and the erasure count of other blocks is stored in the partial block. thing.
[0016]
A nonvolatile semiconductor memory device according to a second aspect of the present invention includes a plurality of blocks including a plurality of NAND cells in which current paths of a plurality of nonvolatile memory cells that can be electrically written and erased are connected in series. In a memory cell array, a block erase circuit for simultaneously erasing the plurality of nonvolatile memory cells included in the plurality of blocks for each block, and in erase verify read, all nonvolatile memory cells included in the erase block are sufficiently erased An erase verify number storage unit that stores the number of erase operations and verify operations that are repeated until it is determined that the data has been erased, and the number of erase times stored in the erase verify number storage unit when reading the data stored in the nonvolatile memory cell. With increase When reading a page And a readout time setting circuit for extending the readout time. According to this configuration, the number of erase operations and verify operations that are repeated until it is determined that the nonvolatile memory cell has been sufficiently erased is stored in the erase verify number storage unit, and the erase operation stored in the erase verify number storage unit Since the read time is set by the read time setting circuit based on the number of verify operations, the read time can be set according to the time required for erasing, and an increase in the erasing time can be suppressed.
[0018]
A nonvolatile semiconductor memory device according to a third aspect of the present invention includes a plurality of blocks including a plurality of NAND cells in which current paths of a plurality of nonvolatile memory cells that can be electrically written and erased are connected in series. A memory cell array; an erase count storage unit for storing the erase count for each of the plurality of blocks; a sense amplifier circuit that senses and amplifies data of the memory cell via a bit line; and the sense amplifier circuit; Along with an increase in the number of erases stored in the erase number storage unit When reading a page And a current supply circuit for lengthening the time for charging the bit line.
[0019]
In the nonvolatile semiconductor memory device according to the third aspect of the present invention, preferred embodiments are as follows.
(1) A read time setting circuit for setting a read time based on the number of erases stored in the erase number storage unit when reading data stored in the nonvolatile memory cell is further provided.
(2) A read time setting circuit for setting a read time based on the number of erases stored in the erase number storage unit when reading data stored in the nonvolatile memory cell is further provided.
(3) The read time setting circuit extends a page read time as the number of erases stored in the erase number storage unit increases.
[0020]
In the nonvolatile semiconductor memory device according to the first to third aspects described above, preferred embodiments are as follows.
(1) A memory cell array is configured by arranging the nonvolatile memory cells in a matrix, and the memory cell array has a predetermined value related to a data storage area for storing normal data and the number of times the memory cell has been erased in the past. And an erasure count storage area. Since the erase count storage area is provided in a part of the memory cell array to store the erase count, an increase in circuit scale can be suppressed.
(2) A predetermined numerical value related to the number of times the memory cells in each block have been erased in the past is stored for each block. Since the number of times of erasure is stored for each block, the read time can be finely controlled for each block according to the blocks with a large number of erases and the blocks with a small number of erases.
(3) The read time setting circuit includes a pulse generation circuit that generates a basic pulse of a predetermined time, a counter circuit that counts the number of occurrences of the pulse, an output of the counter circuit, and a predetermined number corresponding to the past number of erasures And a comparison circuit that outputs a read end signal if the comparison results match, and outputs a signal for generating the next basic pulse from the pulse generation circuit if they do not match.
( 4 ) The read time setting circuit extends the page read time as the number of erases stored in the erase number storage unit increases. Since the page read time is extended when the nonvolatile memory cell starts to deteriorate and the number of times of erasure increases, it is possible to prevent the erasure time from becoming long.
[0021]
The nonvolatile semiconductor memory device according to the fourth aspect of the invention is electrically writable and erasable A plurality of NAND type cells in which current paths of a plurality of nonvolatile memory cells are connected in series Are arranged in a matrix, a memory cell array having a data storage area for storing normal data and an erase count storage area for storing how many times it has been erased in the past, a row address buffer to which a row address signal is supplied, A row decoder that decodes an output signal of the row address buffer to select a nonvolatile memory cell in the memory cell array for each page, and amplifies and latches page read data from the nonvolatile memory cell selected by the row decoder A sense amplifier register circuit, a column address buffer to which a column address signal is supplied, a column decoder for decoding the output signal of the column address buffer to control the sense amplifier register circuit, and a control signal input from the outside Based on the above row decoder, column decoder Over Da, and the control circuit and the erase count stored in the erase count storage region for controlling the sense amplifier register circuit With the increase of Page read operation of the sense amplifier register circuit Extension And an erasing operation control circuit. The number of erase operations performed in the past by the nonvolatile semiconductor memory device is stored in an erase count storage area provided in a part of the memory cell array, and the page read time of the sense amplifier register circuit is lengthened by the erase operation control circuit according to the erase count. Therefore, it is possible to suppress the erasure time from becoming longer even if the nonvolatile memory cell starts to deteriorate and the number of times of erasure increases.
[0022]
The nonvolatile semiconductor memory device preferably further includes a voltage generation circuit that boosts a power supply voltage to generate a high voltage, an intermediate voltage, and a write-protect drain voltage, and supplies the generated voltage to the memory cell array. Since the voltage generation circuit is provided, voltages necessary for various operations can be generated inside the chip.
[0024]
Since the nonvolatile semiconductor memory device stores a predetermined value corresponding to the number of erase operations performed in the past and controls the read time according to the predetermined value, the nonvolatile semiconductor memory device performs a write and erase operation more than the predetermined number of times. In the case of performing the above, it is possible to prevent the erasing time from being extended by extending the reading time.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a schematic configuration of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. 1 includes a memory cell array 13, a row decoder 14, a row address buffer 15, a sense amplifier register circuit 16, a column decoder 17, a column address buffer 18, an input / output circuit 19, a control circuit 20, An erase operation control circuit 21, a command register 22, a command decoder 23, and a voltage generation circuit 24 are shown.
[0026]
The memory cell array 13 includes, for example, n memory cells in which current paths are connected in series, and source select gates and drain select gates (select transistors) provided at the source end and drain end of the series connected current paths, respectively. Thus, one NAND bundle is formed, and this NAND bundle is arranged in a matrix.
[0027]
A row address signal (page address) RAdd is supplied from the input / output circuit 19 to the row address buffer 15. The row address signal RAdd fetched into the row address buffer 15 is decoded by the row decoder 14, and this decoded signal is supplied to the memory cell array 13 via the word line and the selection line. As a result, one NAND bundle in the memory cell array 13 and one row (one page) of memory cells in the NAND bundle are selected.
[0028]
A column address signal CAdd is supplied from the input / output circuit 19 to the column address buffer 18. The column address signal CAdd taken into the column address buffer 18 is decoded by the column decoder 17, and the sense amplifier register circuit 16 is driven by this decoded signal. Data read from the memory cell array 13 to the sense amplifier register circuit 16 via the bit line is output on a page basis via the input / output circuit 19.
[0029]
Various commands are input to the command register 22 from the outside via the input / output circuit 19, and the command fetched into the command register 22 is decoded by the command decoder 23 and supplied to the control circuit 20. Various control signals are input to the control circuit 20 from the outside, and the sense amplifier register circuit 16, the row decoder 14, and the column decoder 17 are based on these control signals and the command supplied from the command decoder 23. The voltage generation circuit 24 and the like are controlled.
[0030]
The voltage generation circuit 24 boosts the power supply voltage to generate a high voltage VPP (about 20 V), an intermediate voltage VPI (about 10 V), and a write inhibit drain voltage VDPI (about 10 V), and supplies them inside the chip.
[0031]
In the present invention, the control circuit 20 is provided with an erase operation control circuit 21. The erase operation control circuit 21 controls the page read time by controlling the sense amplifier register circuit 16 in accordance with the erase count counted by the erase count counter. When the write and erase operations are performed more than a predetermined number of times, the page read time is controlled. Extend the readout time.
[0032]
FIG. 2 is a block diagram showing a configuration example of the memory cell array 13 shown in FIG.
The memory cell array 13 includes a data storage area and an erase count storage area. The data storage area is an area for storing normal data and is divided into N blocks. The erase count storage area stores how many times each corresponding block of the data storage area has been erased in the past.
[0033]
FIG. 3 is a circuit diagram showing a detailed configuration example focusing on one block in FIG.
The basic memory cell configuration of the data storage area and the erase count storage area is the same as that of a normal NAND flash memory, and only the stored data is different. That is, each of the bit lines BL1, BL2,... In the data storage area has NAND bundles 26-1, 26 each configured by connecting the current paths of the selection transistor ST1, the memory cells MC1 to MCn, and the selection transistor ST2 in series. 2, ... are connected. Similarly, NAND bundles 26a and 26b configured by connecting current paths of the selection transistor ST1, the memory cells MC1 to MCn, and the selection transistor ST2 in series are also connected to the bit lines BLa and BLb in the erase count storage area. ing. A selection line SGS is connected to the gates of the selection transistors ST1 arranged in the same row, and word lines WL1 to WLn are connected to the control gates of the memory cells MC1 to MCn arranged in the same row. A selection line SGD is connected to each of the selection transistors ST2 arranged in the row. The selection line SGS, the word lines WL1 to WLn, and the selection line SGD are driven by the row decoder 14, respectively.
[0034]
Sense amplifier register circuits 16-1, 16-2,..., 16a, 16b comprising inverters INV1 and INV2 are connected to the bit lines BL1, BL2,. The outputs of the sense amplifier register circuits 16a and 16b in the erase count storage area are supplied to the erase operation control circuit 21. The erase operation control circuit 21 includes a temporary storage unit 27, a data input control circuit 28, and a flag data conversion circuit 29. The outputs of the sense amplifier register circuits 16a and 16b are supplied to the temporary storage unit 27. The output signal of the temporary storage unit 27 is supplied to the data input control circuit 28. The data input control circuit 28 controls the sense amplifier register circuit 16 based on the output signal of the flag data conversion circuit 29 for converting the flag data of the status flag and the output signal of the temporary storage unit 27. When the write and erase operations are performed more than the number of times, the page read time is extended.
[0035]
In the first embodiment, two NAND bundles are assigned to the erase count storage area in one block of the memory cell array 13. Assuming that one NAND bundle is composed of 16-bit memory cells, 2 bits out of 32 bits of 2 NAND bundles are allocated for reading time control data storage, and the remaining 20 bits are allocated for erasure count storage. . The 20 bits for storing the number of times of erasure are rewritten every time the data is erased. Also, a flag for defining a read time calculated from the number of erasures is stored in 2 bits for reading time control data storage (2 bits for reading). For example, in the example shown in FIG. 3, four pieces of information are stored using memory cells MCa and MCb in two bits for reading. Block erase counts up to 100,000 times are assigned to state 1, 100,000 times to 300,000 times are assigned to state 2, 300,000 to 1,000,000 times are assigned to state 3, and 1 million times or more are assigned to state 4. The number of erasures is stored by associating up to 4 with the data states of the memory cells MCa and MCb.
[0036]
Next, a method for storing the number of erasures and a control method at the time of reading using the nonvolatile semiconductor memory device configured as described above will be described.
FIG. 4 is a flowchart showing a sequence of internal operations when performing block erase.
Normally, in a NAND flash memory, a command input from the outside via the input / output circuit 19 is received by the command register 22, decoded by the command decoder 23 and supplied to the control circuit 20 (step A1), and the input / output circuit from the outside An erase address is input via 19 and the row address is latched in the row address buffer 15 to select an erase block (step A2).
In order to read information on the number of times of erasure stored in the selected block, first, a page read operation is performed, and read data is latched in the sense amplifier register circuits 16a and 16b. This operation is repeated to read a total of 32-bit data from the first page to the Nth page. The page read information is transferred to the temporary storage unit 27 for temporarily storing this information every time and is held in the primary storage unit 27 until the erasing operation is completed. By repeating this operation for the erase block, all the data in the erase count storage area of each erase block is transferred to the temporary storage unit 27 (step A3).
Next, in the case of NAND flash, erasing is performed by applying a high voltage pulse to the memory cell for about 5 msec (step A4). After the erase operation, it is checked in the verify mode operation whether or not the threshold voltage of all the memory cells in the selected block has been erased to a predetermined negative threshold voltage (step A5). If all the memory cells are erased to a predetermined threshold voltage as a result of the verification, a flag signal is output and the verification operation ends. On the other hand, if there is a memory cell that is not sufficiently erased, the process returns to step A4 and the erase operation is performed again, and the erase and verify are repeated until the verify is performed and a sufficient erase state is achieved. When it is detected that the erased state is sufficient as a result of the verification, the erase count of the selected block held in the temporary storage unit 27 is incremented by one (step A6), and the erase count storage area of the erased block is incremented. The erase count storage operation for writing back to (1) is performed (step A7). In this case, the erase count information incremented by 1 is written in the 20 bits for storing the erase count, and a status flag corresponding to the erase count is stored in the read 2 bits (memory cells MCa, MCb). .
The flag data conversion circuit shown in FIG. 3 is a circuit that generates flag data based on this incremented erase count storage information. The output data of the flag data conversion circuit 29 and the erase count information incremented by one are data. Input to the input control circuit 28. Based on the output data of the data input control circuit 28, the data of the sense amplifier register in the erase count storage area is set, and the erase count and read time control data are stored in the erase count storage area.
[0037]
Next, the reading sequence will be described with reference to the flowchart of FIG.
After inputting the read command (step B1), a page address to be read is input from the outside (step B2). First, the status flag data stored in page N of the block including this page address is read (step B3).
The page read time is determined based on the value of the status flag stored in the memory cells MCa and MCb (step B4). For example, when the status flag is “1”, the number of erases is 100,000 or less, so the erase cell is sufficiently erased to a predetermined threshold voltage Vth, and the page read time is set to Tr. When the status flag is 2, the number of erases is 300,000 or less. Therefore, by setting the page read time to 2Tr, which is twice as long, even a memory cell with a shallow threshold voltage is regarded as “1” data. To do. When the status flag is 3 or 4, the page read time is set to 5Tr or 10Tr, so that even a memory cell with a shallower threshold voltage can be regarded as “1” data.
Thereafter, a page read operation (step B5) and a serial read operation (step B6) are performed based on the page read time set in step B4.
[0038]
FIG. 6 shows one configuration example of a circuit for setting the page read time in accordance with the value of the state flag described above, and FIG. 7 is a timing chart of each signal in the circuit shown in FIG.
This circuit is supplied with a time control circuit 31 to which a status flag read from each block is input, a delay circuit 32 to which a page read start signal A is input, and a delay signal from the delay circuit 32 is supplied as a counter increment signal B. The counter circuit 33 and the time control circuit 31 are compared with the output signal of the counter circuit 33, and the trigger signal C of the delay circuit 32 or the page read end signal D is output.
[0039]
The delay circuit 32 is configured such that the internal signal becomes high level when triggered by the page read start signal A, and the internal signal becomes low level after a predetermined time Tr. In response to the low level of the internal signal, the delay circuit 32 outputs a counter increment signal (pulse signal) B. With this signal B, the count value of the counter circuit 33 is incremented. The counter circuit 33 outputs the number of counts.
The time control circuit 31 is a circuit that outputs a numerical value for controlling the page read time Tr based on the value of the state flag read in step B3 and stored in the temporary storage unit 27, and when the state flag is “1”. Outputs “1”, “2” when the status flag is “2”, and 5 and 10 when the status flag is 3 and 4, respectively. The count output of the counter circuit 33 and the value of the time control circuit 31 are compared by the comparison circuit 34, and if they do not match, the trigger signal C for starting the delay circuit 32 is output again. If they match, a page read end signal D is output from the comparison circuit 34 instead of the trigger signal C, the bit line data read ends, and the level of the bit line BL is latched in the sense amplifier register circuit 16. The For example, as shown in FIG. 6, when the status flag N is four times, the page read end signal D is output when the output M of the counter circuit 33 reaches 10.
[0040]
FIG. 8 is a flowchart showing an erase sequence for explaining the nonvolatile semiconductor memory device and the erase method thereof according to the second embodiment of the present invention. Since the configuration of this embodiment is the same as that of the first embodiment, illustration and description thereof are omitted.
[0041]
In the first embodiment, the number of erasures performed in the past is stored in the erasure count storage area and the page read time is set. In the second embodiment, the time required for erasure (all the times in the block) The page read time is set by monitoring the time until the memory cell is completely erased. That is, after the command is input (step C1), “1” is set as the count value N to the internal counter that temporarily stores the number of times of erasure (step C2). Thereafter, the erase block address is input to select the erase block (step C3).
An erase operation is performed for a predetermined time (step C4), and then verification is performed to determine whether all memory cells have been erased (step C5). In this verify operation, when an insufficiently erased memory cell is detected, the internal counter is incremented by 1 (step C6), and re-erasure is performed. This erase and verify operation is performed until all memory cells are erased. When it is determined that all memory cells have been erased by the verify operation, a predetermined value based on the count value N of the internal counter is stored in the nonvolatile storage unit (step C7).
As this nonvolatile storage unit, a memory cell adjacent to a normal data storage area may be used, or a nonvolatile memory may be arranged in a peripheral circuit other than the data storage area. . This predetermined value is set as follows, for example.
If the number of times of writing and erasing is less than 100,000 times, the threshold voltage of the memory cell becomes sufficiently deep by one erasing. Therefore, a sufficient erasing state is detected by the first verification, and the count value N of the internal counter Indicates “1”. If the number of times of writing and erasing is 100,000 times or more and less than 300,000 times, the number of times of erasing is required twice, and the count value N of the internal counter indicates 2. Further, if the number of times of writing and erasing is 300,000 times or more and less than 1 million times, the number of times of erasing is required 3 to 5 times, and if it is 1 million times or more, the number of erasing times is 6 times or more. Therefore, when the count value N is “1”, “1” is stored in the nonvolatile storage unit, and when the count value N is “2”, “2” is stored. When N is 3 to 5, 5 is stored, and when N is 6 or more, 10 is stored. The data in the nonvolatile storage unit is read at the time of reading, and this read data is given in place of the output signal of the time control circuit 31 shown in FIG. 6, so that the page read time is set according to the number of erasures for each block. it can.
[0042]
In such a configuration and erasing method, the total number of times of erasing is not counted, but how many erasing operations are performed in a certain time until all the memory cells in the block are completely erased. By counting whether it has been performed, the total number of times of erasure can be predicted, so that the same effect as the first embodiment can be obtained.
[0043]
FIG. 9 shows a schematic configuration according to the third embodiment when a current detection type sensing method is adopted as the sensing method in the first and second embodiments. 9, the same parts as those in FIG. 10 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0044]
In FIG. 9, an n-channel transistor NT with a predetermined constant voltage CV supplied to the gate is inserted between the bit line and the sense node A. The transistor NT functions as an amplifying transistor at the node A. Further, the n-channel transistor PT is connected to the node A as a load transistor for controlling the current flowing through the memory cell. Further, a transistor DT is connected between the node A and the sense amplifier register circuit 12 as in FIG.
[0045]
Conventionally, only on / off of the precharge transistor PT has been controlled. In the present invention, the bias voltage setting circuit 17 changes the voltage applied to the gate of the load transistor PT to thereby change the current flowing through the load transistor PT. I have control. Since the potential of the node A is determined by the balance between the current flowing through the load transistor PT and the current flowing through the memory cell, the current flowing through the load transistor PT can be changed to cope with the change in the threshold value of the memory cell MC. .
[0046]
For example, when the gate voltage of the load transistor PT is controlled to control the current flowing through the load transistor PT to I2, if the current I1 flowing through the memory cell MC in the erased state is larger than I2, the potential at the node A becomes low. Conversely, if data is written into the memory cell MC and the current I1 flowing through the memory cell MC becomes smaller than I2, the potential at the node A becomes high. In this case, if the current flowing through the load transistor PT is made as small as possible, the erase state can be determined even if the current flowing through the memory cell MC is small. However, if the current I2 of the load transistor PT is set to a small value, the time for charging the capacity of the bit line BL becomes long, so that the page read time becomes long.
[0047]
In order to solve this problem, in the present embodiment, the bias voltage by the bias voltage setting circuit 17 that controls the gate voltage of the load transistor PT is controlled by the result of the number of times of writing / erasing. The bias voltage setting circuit 17 receives the status flag data shown in the first and second embodiments, and the bias voltage setting circuit 17 changes the gate voltage of the load transistor PT based on the status flag data. Thus, the current value I2 of the load transistor PT is controlled. While the number of times of writing / erasing is small, the current value I2 of the load transistor PT is set to be larger. However, when the number of times of writing / erasing exceeds a predetermined value, the current value I2 of the load transistor PT is set to be smaller. That is, the bias voltage setting circuit 17 sets the gate voltage so that the current value I2 of the load transistor PT is set to a larger value while the number of times of writing / erasing is small, but the number of times of writing / erasing exceeds a predetermined value. Then, the gate voltage is set so that the current value I2 of the load transistor PT becomes small. At the same time, the page read time is set longer as in the first and second embodiments. As a result, the problem that the erasing time is extended even if the number of times of writing / erasing increases is solved.
[0048]
In the above embodiment, an example is described in which the page read time Tr is set to double when the number of times of writing and erasing is 300,000 times or less, 5 times when the number is 1,000,000 times or less, and further 10 times when the number of times is 1 million times or more. However, since this value actually changes depending on the oxide film thickness, oxide film quality, etc. of the memory cell, it is preferably optimized for each device.
[0049]
As described above, according to the present invention, even if the nonvolatile memory cell deteriorates and cannot be erased sufficiently, the erasing time can be shortened, and the lifetime of the nonvolatile semiconductor memory device can be extended.
The present invention is not limited to the embodiment of the invention described above, and it is needless to say that various modifications can be made without departing from the scope of the invention.
[0050]
【The invention's effect】
As described above, according to the present invention, a nonvolatile semiconductor memory device that can perform optimum erasure according to the number of times of writing and erasing, and can suppress an increase in erasing time as the number of times of erasing increases, and erasing the same A method is obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a nonvolatile semiconductor memory device according to a first embodiment of the invention.
2 is a block diagram illustrating a configuration example of a memory cell array illustrated in FIG. 1;
FIG. 3 is a circuit diagram showing a detailed configuration example focusing on one block in FIG. 2;
FIG. 4 is a flowchart showing a sequence of internal operations when performing block erasure.
FIG. 5 is a flowchart showing a read sequence.
FIG. 6 is a circuit diagram showing a configuration example of a circuit for setting a page read time based on a value of a status flag.
7 is a timing chart of each signal in the circuit shown in FIG.
FIG. 8 is a flowchart showing an erase sequence for explaining a nonvolatile semiconductor memory device and an erase method thereof according to a second embodiment of the present invention.
FIG. 9 is a diagram showing a schematic configuration of a third embodiment when a current detection type sensing method is adopted as a sensing method in the first and second embodiments of the present invention.
FIG. 10 is a circuit diagram schematically showing a circuit portion related to a memory cell and its peripheral read operation in a NAND flash memory.
11 is a timing chart for explaining a reading operation in the circuit shown in FIG. 10;
FIG. 12 is a graph showing the dependence of the threshold voltage after erasing a memory cell on the number of writing and erasing.
FIG. 13 is a diagram showing a relationship between a threshold voltage after erasure of a memory cell and a page read time.
[Explanation of symbols]
13 ... Memory cell array
14 ... Row decoder
15 ... Row address buffer
16 Sense amplifier register circuit
16-1, 16-2, 16a, 16b... Sense amplifier register
17 ... Column decoder
18 ... Column address buffer
19 ... I / O circuit
20 ... Control circuit
21 ... Erase operation control circuit
22 ... Command register
23 ... Command decoder
24 ... Voltage generation circuit
26-1, 26-2, 26a, 26b ... NAND bundle
27 ... Temporary memory circuit
28: Data input / output circuit
29. Flag data conversion circuit
31. Time control circuit
32 ... Delay circuit
33 ... Counter circuit
34. Comparison circuit
MC1 to MCn ... memory cells
ST1, ST2 ... selection transistor (select gate transistor)
WL1 to WLn ... Word line
SGS, SGD ... selection line
BL1, BL2, BLa, BLb ... bit lines

Claims (11)

A memory cell array including a plurality of blocks each including a plurality of NAND-type cells in which current paths of a plurality of nonvolatile memory cells that can be electrically written and erased are connected in series;
A block erasing circuit for simultaneously erasing the plurality of nonvolatile memory cells included in the plurality of blocks for each block;
An erase count storage unit for storing the erase count of the nonvolatile memory cells included in one block, the number of erases of the nonvolatile memory cells simultaneously erased by the block erase circuit;
A read time setting circuit for extending a read time with an increase in the number of erases stored in the erase number storage unit when reading the data stored in the nonvolatile memory cell;
A non-volatile semiconductor memory device comprising:   2. The non-volatile semiconductor memory device according to claim 1, wherein the erase count storage section includes an erase count counter that is incremented in accordance with the erase count. 3. The nonvolatile semiconductor memory device according to claim 1, wherein the erasure count storage unit is assigned to a part of the plurality of blocks, and erasure of another block is performed on the part of the blocks. A non-volatile semiconductor memory device, wherein the number of times is stored . A memory cell array including a plurality of blocks each including a plurality of NAND-type cells in which current paths of a plurality of nonvolatile memory cells that can be electrically written and erased are connected in series;
A block erasing circuit for simultaneously erasing the plurality of nonvolatile memory cells included in the plurality of blocks for each block;
In erase verify read, an erase verify number storage unit that stores the number of erase operations and verify operations that are repeated until it is determined that all the nonvolatile memory cells included in the erase block are sufficiently erased;
A read time setting circuit for extending a read time with an increase in the number of erases stored in the erase verify number storage unit when reading the stored data of the nonvolatile memory cell;
A non-volatile semiconductor memory device comprising: A memory cell array including a plurality of blocks each including a plurality of NAND-type cells in which current paths of a plurality of nonvolatile memory cells that can be electrically written and erased are connected in series;
An erase count storage unit for storing the erase count for each of the plurality of blocks;
A sense amplifier circuit that senses and amplifies data of the memory cell via a bit line;
A current supply circuit that is connected to the sense amplifier circuit and increases the time to charge the bit line at the time of page reading with an increase in the number of erases stored in the erase number storage unit;
A nonvolatile semiconductor memory device comprising:   6. The non-volatile semiconductor memory device according to claim 5, further comprising a read time setting circuit that sets a read time based on the erase count stored in the erase count storage section when reading data stored in the nonvolatile memory cell. A non-volatile semiconductor memory device comprising:   7. The nonvolatile semiconductor memory device according to claim 6, wherein the read time setting circuit extends a page read time with an increase in the number of erases stored in the erase number storage unit. Semiconductor memory device. 8. The non-volatile semiconductor memory device according to claim 5 , wherein a memory cell array is configured by arranging the non-volatile memory cells in a matrix, and the memory cell array stores data normally. A non-volatile semiconductor memory device comprising: an area and an erase count storage area for storing a predetermined numerical value related to the number of times the memory cell has been erased in the past.   9. The nonvolatile semiconductor memory device according to claim 8, wherein a predetermined numerical value related to the number of times the memory cells in each block are erased in the past is stored for each block. .   10. The nonvolatile semiconductor memory device according to claim 1, wherein the read time setting circuit includes a pulse generation circuit that generates a basic pulse for a predetermined time, The counter circuit that counts the number of pulse generations is compared with the output of this counter circuit and a predetermined number corresponding to the past number of erasures. If the comparison results match, a read end signal is output. A non-volatile semiconductor memory device comprising a comparison circuit that outputs a signal for generating a next basic pulse from a pulse generation circuit. A plurality of NAND-type cells in which current paths of a plurality of nonvolatile memory cells that can be electrically written and erased are connected in series are arranged in a matrix, and a data storage area for storing normal data and how many times in the past are erased A memory cell array having an erase count storage area for storing
A row address buffer to which a row address signal is supplied;
A row decoder that decodes an output signal of the row address buffer and selects a nonvolatile memory cell in the memory cell array for each page;
A sense amplifier register circuit that amplifies and latches page read data from the nonvolatile memory cell selected by the row decoder;
A column address buffer to which a column address signal is supplied;
A column decoder for controlling the sense amplifier register circuit by decoding the output signal of the column address buffer, and a control circuit for controlling the row decoder, the column decoder, and the sense amplifier register circuit based on a control signal input from the outside When,
An erase operation control circuit for extending the page read operation of the sense amplifier register circuit with an increase in the erase count stored in the erase count storage area;
A non-volatile semiconductor memory device comprising:

Images