JP3818191B2 - Source-synchronous software macro and information processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention, source over scan synchronous software macros, and relates to an information processing apparatus, in particular, Luso over scan Synchronous soft macro to implement the distribution of the source clock with high precision, and relates to an information processing apparatus.
[0002]
[Prior art]
The source synchronous transfer method is used particularly for high-speed data transfer between computer LSIs. The source synchronous transfer method is a method in which a data signal and a source clock signal (strobe signal) are simultaneously output from a sending LSI, transmitted through the same wiring board and cable, and the source clock signal to which data is transmitted by the receiving LSI. This is a transfer method that is synchronized with the receiving clock after sampling at.
[0003]
Therefore, since the delay delay of the LSI and the delay variation of the wiring board, cable, connector, etc. can be taken into account by the relative delay difference, this method is more effective than the synchronous transfer method at high-speed transfer. From the viewpoint of reducing delay variation, it is ideal to send the source clock signal and the data signal on a one-to-one basis. However, since this increases the number of LSI pins, generally the source clock signal Several data signals are transferred together for one.
[0004]
For example, the invention described in “JP 2000-347993 A” relates to a source synchronous transfer system.
[0005]
FIG. 14 is a block diagram showing an example of the source synchronous transfer system of the above publication.
[0006]
Referring to FIG. 14, the F / F 43 holds one bit of data in synchronization with the sending clock, and the F / F 44 generates a source clock from the sending clock. The write address generation circuit 49 generates a write address signal from the source clock, the write selector 48 selects one bit of data according to the write address signal, and the data holding circuit 50 samples one bit of data with the source clock. The read address generation circuit 53 receives the synchronization signal from the synchronization circuit 51 and generates a read address signal synchronized with the receiving clock, and the read selector 52 generates one bit of data in the data holding circuit 50 according to the read address signal. The F / F 54 samples and outputs one bit of data with the receiving clock.
[0007]
In this way, in the source synchronous transfer method, in order to realize high-speed transfer by reducing delay variation, it is necessary to make the clock distribution delay and source clock distribution delay in the source synchronous function macro as similar as possible. Therefore, it is general to design with a macro unit layout (hard macro) having the function.
[0008]
Further, the invention described in “Japanese Patent Application Laid-Open No. 11-119854” generates the group including a division unit that divides a plurality of Nth-stage macros arranged in an LSI into groups, and an Nth-stage macro. Thereafter, the clock path generation device includes a generation unit that generates a macro of the (N-1) th stage for supplying a clock signal to the macros in the group for each group.
[0009]
[Problems to be solved by the invention]
The problem of the above-described conventional technique is that the number of macro design man-hours and various design libraries increase.
[0010]
The reason for this is that the data bit width used for transfer between LSIs is not uniform and there are many types. When creating source-synchronous hard macros corresponding to these, the same number of source-synchronous hard macros are created. This is because it needs to be created.
[0011]
The second problem is that physical verification such as DRC and LVS needs to be performed in units of macros.
[0012]
This is because the layout is made in units of macros.
[0013]
An object of the present invention is to design a source I / O block for data and a source clock I / O block, and to realize source synchronous macros with various bit widths only by combining them.
[0014]
[Means for Solving the Problems ]
[0016]
The first source synchronous software macros of the present invention is equipped with one or more 1st driver for distributing a clock signal to the outside, including first output terminal for distributing the clock signal of the 1st driver distributable and comprising a wiring channel region laid out source clock I / O block, equipped with one or more 2nd driver for distributing a clock signal to the internal, for receiving a clock signal from the 1st driver One or more data I / O blocks laid out with a second distribution wiring channel region including an input terminal of the 2nd driver, the first distribution wiring channel region and the second distribution wiring The output channel and the input terminal are connected to each other by adjacent wiring channel regions .
[0017]
A second source-synchronous soft macro of the present invention is the first source-synchronous soft macro, which includes the first distribution wiring channel region including an output terminal for distributing a read address. A source clock I / O block; and the data I / O block including the second distribution wiring channel region including a read address distribution input terminal; and the read address distribution output terminal and A lead address distribution input terminal is connected by wiring.
[0019]
A third source-synchronous soft macro according to the present invention includes one or more 1st drivers for distributing a clock signal to the outside, and a 2nd driver including an output terminal for distributing the clock signal of the 1st driver; A source clock I / O block laid out with a distribution wiring channel region for wiring in a straight line and one or more 2nd drivers for distributing a clock signal therein are mounted, and the clock signal from the first driver the 2nd and a the 1st driver and layout data for I / O block includes a distribution wire channel region for interconnection with straight line including an input terminal of the driver, the first distribution wire channels for receiving the The output terminal and a region adjacent to the second distribution channel region Characterized in that connecting the fill power terminal in straight lines.
[0022]
First information processing apparatus of the present invention is equipped with one or more 1st driver for distributing a clock signal to the outside, distributable output terminal including a first for distributing a clock signal of the 1st driver A source clock I / O block laid out with a wiring channel region and one or more 2nd drivers for distributing a clock signal therein, and the 2nd driver for receiving a clock signal from the 1st driver Including one or more data I / O blocks laid out with a second distribution wiring channel region including a plurality of input terminals, and the first distribution wiring channel region and the second distribution wiring channel region. configured to include a source synchronous software macros and said input terminal and said output terminal are adjacent to hardwired bets And wherein the door.
[0023]
A second information processing apparatus according to the present invention includes the second source-synchronous soft macro.
[0025]
A third information processing apparatus according to the present invention includes one or more 1st drivers for distributing a clock signal to the outside and wiring in a straight line with a 2nd driver including an output terminal for distributing the clock signal of the 1st driver. A source clock I / O block laid out with a distribution wiring channel region and one or more 2nd drivers for distributing a clock signal therein and receiving a clock signal from the first driver The first driver including the input terminal of the 2nd driver and a data I / O block laid out with a distribution wiring channel region for wiring in a straight line, the first distribution wiring channel region and the Adjacent to the second distribution wiring channel region, the output terminal and the input terminal are straight lines. Characterized in that it is configured to include a source synchronous software macros wired.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings.
[0027]
In the embodiment of the present invention, an I / O macro for source-synchronous data transfer system, which is one of high-speed data transfer systems between LSIs, is not an I / O macro layout (hard macro) having that function. / O This relates to a soft macro in which layout is performed for each single block, and these are collected as a functional block.
[0028]
FIG. 1 is a block diagram showing the configuration of the embodiment of the present invention.
[0029]
Referring to FIG. 1, an embodiment of the present invention is a source synchronous soft macro 120.
[0030]
For example, the source-synchronous soft macro 120 is a balanced signal in which data is 10 bits and the source clock is positive / negative (true / complement), and the I / O block is vertically stacked in three stages. The source synchronous soft macro 120 includes a data I / O block 11, a data I / O block 12, a data I / O block 13, a data I / O block 14, a data I / O block 15, data I / O block 16 for data, I / O block 17 for data, I / O block 18 for data, I / O block 19 for data, I / O block 20 for data, and I / O block 21 for source clock Consists of
[0031]
The first stage includes a data I / O block 11, a data I / O block 14, a data I / O block 16, and a data I / O block 18, and the second stage includes a data I / O block. The block 12 includes a source clock I / O block 21 and a data I / O block 19. The third stage is a data I / O block 13, a data I / O block 15, and a data I / O block. 17, composed of a data I / O block 20.
[0032]
Intra-macro distribution signals from the source clock I / O block 21 (intra-macro distribution signals such as a source clock signal, a system clock signal, a write address signal, and a read address signal) are respectively for the data I / O blocks 11 to 11. It is supplied to the I / O block 20.
[0033]
In order to suppress delay variation, it is necessary to make the distribution delay times of the source clock signal and the system clock signal out of the distribution signals in the macro as equal as possible. Therefore, the source clock I / O block 21 is arranged near the center of the source synchronous macro, and the data I / O block 11 to the data I / O block 20 are arranged around it.
[0034]
In the source clock I / O block 21, a 1st driver 2110, a 1st driver 2111, and a 1st driver 2112 are mounted for distribution within a macro. Further, in the data I / O block 11 to the data I / O block 20, a 2nd driver 1120 that distributes signals distributed from the 1st driver 2110, 1st driver 2111, and 1st driver 2112 in the I / O block, respectively. 2nd driver 1220, 2nd driver 1320, 2nd driver 1420, 2nd driver 1520, 2nd driver 1620, 2nd driver 1720, 2nd driver 1820, 2nd driver 1920, and 2nd driver 2020 are mounted.
[0035]
The source clock I / O block 21 is provided with a 2nd driver 2120 and a 2nd driver 2121 for distributing the signal distributed from the first driver 2112 into the I / O block.
[0036]
In the macro wiring, the distribution wiring channel region 300, the distribution wiring channel region 301, and the distribution wiring channel region 302 provided at the end of each I / O block are wired in a straight line. Match the coordinates of the terminals. In addition, it is desirable to shield the periphery of this wiring so as not to be affected by other wiring.
[0037]
The source clock signal distribution and system clock distribution signal should be distributed with the same delay value for both macros with a small number of data bits and macros with a large number of data bits. The 2nd driver also has a plurality of dummy loads for adjusting the load. The distribution wiring delay is adjusted by changing the number of dummy loads of the 1nd driver's driving capability 2nd driver.
[0038]
About this combination, it determines using circuit simulations, such as SPICE, and the information is made into the library of a soft macro. The distribution wiring in the macro is automatically wired by the CAD tool based on this library.
[0039]
The source-synchronous soft macro 120 as a combination of blocks physically manufactures transistors, wirings, and the like as a whole. Thus, the signal is not divided at the end of each block, but across blocks.
[0040]
Next, the operation of the embodiment of the present invention will be described with reference to the drawings.
[0041]
FIG. 2 is an explanatory diagram showing the concept of signal distribution within a macro.
[0042]
FIG. 3 is an explanatory diagram showing the concept of signal distribution within a macro.
[0043]
FIG. 4 is a circuit diagram showing the configuration of the dummy load.
[0044]
Referring to FIG. 2, the source clock I / O block 21 has a drive capability twice (× 2), three times (× 3), and four times (× 4) of the standard for the source clock and the system clock. Equivalent 1st drivers are installed, and 2nd drivers including dummy ones are installed 4x2. FIG. 2 shows an example in which the number of data bits is relatively small. In this example, a 1st driver having a driving capability equivalent to twice the standard is used, and three dummy loads are added. Signals are also connected to dummy 2nd drivers of the data I / O block 22 and the data I / O block 23.
[0045]
Referring to FIG. 3, this is an example in which the number of data bits is large. A 1st driver having a driving capability equivalent to four times the standard is used, and no signal is connected to the dummy load.
[0046]
The input capacity of the 2nd driver is preferably as small as possible in consideration of suppressing variations. Further, the dummy load is configured as shown in FIG. 4 so that no through current flows even when the input is opened.
[0047]
Next, connection in the distribution wiring channel region between drivers will be described.
[0048]
FIG. 5 is an explanatory diagram showing the connection of the 1st driver output unit and the 2nd driver input unit.
[0049]
Referring to FIG. 5, from the first driver (× 2) of the source clock I / O block 21, four 2nd drivers of the data I / O block 22 (dummy load is 3) from the distribution wiring channel region wiring. Connected). A circle surrounded by a square indicates a terminal. For example, a source clock I / O block and a data I / O block are wired from this terminal via a VIA (via) hole, for example, in an upper distribution channel region.
[0050]
The driving ability can be changed by changing the connection position of the 1st driver output terminal. Further, load adjustment can be performed by changing the number of connections of the 2nd driver input terminals.
[0051]
FIG. 6 is an explanatory diagram showing the configuration of the distribution wiring channel region.
[0052]
Referring to FIG. 6, the distribution wiring channel region is composed of four types of regions: source clock distribution, read address distribution, write address distribution, and system clock distribution, which are separated by shield wiring. It is not inevitable to include read address distribution and write address distribution in this distribution wiring channel region.
[0053]
In order to reduce the wiring resistance and capacity of the intra-macro wiring and simplify the automatic wiring by the CAD tool, it is desirable to wire in a straight line. In order to realize this, it is desirable to arrange the input / output terminals for each intra-macro wiring as shown in FIG. FIG. 6 shows an example in which both the read address and the write address are 4 bits.
[0054]
Next, the layout of the data I / O block and the source clock I / O block will be described.
[0055]
FIG. 7 is an explanatory diagram showing the layout of the data I / O block.
[0056]
FIG. 8 is an explanatory diagram showing the layout of the source clock I / O block.
[0057]
Referring to FIG. 7, in the data I / O block, for example, a source clock 2nd driver unit and a system clock 2nd driver unit are arranged in a distribution wiring channel region, and the first driver of the source clock I / O block is arranged. The shape of the part is deleted to a square.
[0058]
Referring to FIG. 8, the source clock I / O block includes, for example, a source clock 2nd driver unit, a system clock 2nd driver unit, a source clock 1st driver unit, and a system clock 1st driver in a distribution wiring channel region. The first clock driver portion for the source clock and the first clock driver portion for the system clock are arranged in a protruding manner.
[0059]
Next, combinations of data I / O blocks and source clock I / O blocks will be described.
[0060]
FIG. 9 is an explanatory diagram showing a layout of the source synchronous software macro 120.
[0061]
Referring to FIG. 9, the source-synchronous soft macro 120 includes a combination of a data I / O block and a source clock I / O block. That is, the data I / O block 11, the data I / O block 12, the data I / O block 13, the data I / O block 14, the data I / O block 15, the data I / O block 16, The data I / O block 17, the data I / O block 18, the data I / O block 19, the data I / O block 20, and the source clock I / O block 21 are configured.
[0062]
In FIG. 1 and FIG. 9, the I / O block constitutes a source-synchronous soft macro as three vertically stacked, but it may be one or two. Further, although the source clock is a positive / negative (True / Complement) balanced signal, it may be a single signal as long as source synchronous transfer is possible.
[0063]
In FIGS. 2 and 3, three types of drive capacity are provided for the 1st driver, equivalent to 2 times, 3 times, and 4 times the standard, and the number of dummy loads of the 2nd driver is 3, but source synchronous software Since it is necessary to select an optimal driving capability and an optimal number of dummy loads depending on the macro configuration, it is not necessary to be constrained by the configurations in FIGS.
[0064]
The terminal positions in FIG. 6 are also arbitrary. The layout of the I / O block shown in FIGS. 7 and 8 is arbitrary as long as the present design method can be performed.
[0065]
Next, various layout examples will be described with reference to the drawings.
[0066]
FIG. 10 is an explanatory diagram showing an example of the layout of the source synchronous software macro.
[0067]
FIG. 11 is an explanatory diagram showing an example of the layout of the source synchronous software macro.
[0068]
FIG. 12 is an explanatory diagram showing an example of the layout of the source synchronous software macro.
[0069]
FIG. 13 is an explanatory diagram showing an example of the layout of the source synchronous software macro.
[0070]
FIG. 10 shows an example of a source synchronous software macro 120 having a balance signal of 10 bits of data and a source clock of True / Comp, and an I / O block of three stages. FIG. 11 shows an example of a source synchronous soft macro 121 having a 20-bit data, a source clock of True / Complement, and an I / O block of three stages stacked vertically. The data I / O block 11 to the data I / O block 20 in FIG. 10, the data I / O block 11 to the data I / O block 20, and the data I / O blocks 31 to 40 in FIG. Are the same.
[0071]
Similarly, the source clock I / O block 21 in FIG. 10 and the source clock I / O block 21 in FIG. 11 are the same.
[0072]
The examples of FIGS. 12 and 13 are also source-synchronous software having the same functional configuration as that of FIG. 11 in which the I / O block is a three-tiered I / O block with a balance signal of 20 bits of data and True / Complement of the source clock. A macro 122 and a source-synchronous soft macro 123. The difference between FIGS. 11 to 13 is only the macro layout shape.
[0073]
An information processing apparatus in which a logic circuit is configured by the source-synchronous soft macro described above is possible.
[0074]
【The invention's effect】
The first effect of the present invention is that source synchronous macros with various bit configurations can be created more easily than designing them as hard macros that are laid out in macro units.
[0075]
The reason is that when designing with a hard macro configuration, it is necessary to create as many source-synchronous hard macros as the bit configuration changes, but when designing with a soft macro configuration, data I / O and source This is because only the clock I / O needs to be designed and then combined.
[0076]
The second effect is that the LSI capacity is improved.
[0077]
This is because the macro shape can be made flexible.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing a configuration of an embodiment of the present invention.
FIG. 2 is an explanatory diagram showing a concept of signal distribution within a macro;
FIG. 3 is an explanatory diagram showing a concept of signal distribution within a macro;
FIG. 4 is a circuit diagram showing a configuration of a dummy load.
FIG. 5 is an explanatory diagram showing connections of a 1st driver output unit and a 2nd driver input unit.
FIG. 6 is an explanatory diagram showing a configuration of a distribution wiring channel region;
FIG. 7 is an explanatory diagram showing a layout of a data I / O block.
FIG. 8 is an explanatory diagram showing a layout of an I / O block for source clock.
9 is an explanatory diagram showing a layout of a source synchronous software macro 120. FIG.
FIG. 10 is an explanatory diagram showing an example of a layout of source synchronous software macro.
FIG. 11 is an explanatory diagram illustrating an example of a layout of source synchronous software macro;
FIG. 12 is an explanatory diagram showing an example of a layout of source synchronous software macro;
FIG. 13 is an explanatory diagram illustrating an example of a layout of source synchronous software macro;
FIG. 14 is a block diagram illustrating an example of a source synchronous transfer method.
[Explanation of symbols]
11 Data I / O Block 12 Data I / O Block 13 Data I / O Block 14 Data I / O Block 15 Data I / O Block 16 Data I / O Block 17 Data I / O Block 18 Data I / O block 19 Data I / O block 20 Data I / O block 21 Source clock I / O block 22 Data I / O block 23 Data I / O blocks 31-40 Data I / O Block 43 F / F
44 F / F
48 write selector 49 write address generation circuit 50 data holding circuit 51 synchronization circuit 52 read selector 53 read address generation circuit 54 F / F
120 Source-synchronous soft macro 121 Source-synchronous soft macro 122 Source-synchronous soft macro 123 Source-synchronous soft macro 300 Distribution-wiring channel area 301 Distribution-wiring channel area 302 Distribution-wiring channel area 1120 2nd driver 1220 2nd driver 1320 2nd driver 1420 2nd driver 1520 2nd driver 1620 2nd driver 1720 2nd driver 1820 2nd driver 1920 2nd driver 2020 2nd driver 2110 1st driver 2111 1st driver 2112 1st driver 2120 2nd driver 2121 2nd driver

Claims (6)

A first driver including one or more 1st drivers for distributing a clock signal to the outside, wherein the first driver is composed of a plurality of drivers having different driving forces, and includes an output terminal for distributing the clock signal of the first driver. A source clock I / O block laid out with a distribution wiring channel region and one or more 2nd drivers for distributing a clock signal therein, and a plurality of dummy connected to the input of the 2nd driver Including one or more data I / O blocks arranged with a load distribution and a second distribution wiring channel region including an input terminal of the second driver for receiving a clock signal from the first driver, Adjacent the first distribution wiring channel region and the second distribution wiring channel region Source synchronous soft macro, characterized in that the said input terminal and said output terminal are connected by wires so. The source clock I / O block including the first distribution wiring channel region including the output terminal for read address distribution, and the second distribution wiring channel region including the input terminal for read address distribution. 2. The source synchronous software according to claim 1, wherein said read address distribution output terminal and said read address distribution input terminal are connected by wiring. macro. One or more 1st drivers for distributing clock signals to the outside, the 2nd driver including an output terminal for distributing the clock signals of the 1st driver , wherein the 1st driver is composed of a plurality of drivers having different driving powers And a source clock I / O block laid out with a distribution wiring channel region for wiring in a straight line, and one or more 2nd drivers for distributing clock signals therein , and input to the 2nd driver A plurality of dummy loads to be connected and a distribution wiring channel region for wiring in a straight line with the 1st driver including the input terminal of the 2nd driver for receiving a clock signal from the 1st driver were laid out. Data I / O block, and the first distribution Source synchronous soft macro, characterized in that the connection between the input terminal and the output terminal with a linear wiring is adjacent to the line for the channel region and said second distribution wiring channel region. A first driver including one or more 1st drivers for distributing a clock signal to the outside, wherein the first driver is composed of a plurality of drivers having different driving forces, and includes an output terminal for distributing the clock signal of the first driver. A source clock I / O block laid out with a distribution wiring channel region and one or more 2nd drivers for distributing a clock signal therein, and a plurality of dummy connected to the input of the 2nd driver Including one or more data I / O blocks for loading and loading and including a second distribution wiring channel region including an input terminal of the second driver for receiving a clock signal from the first driver, Adjacent the first distribution wiring channel region and the second distribution wiring channel region The information processing apparatus characterized by being configured to include a source synchronous software macros and said input terminal and said output terminal are connected by wires so.   An information processing apparatus comprising the source-synchronous soft macro according to claim 2. One or more 1st drivers for distributing clock signals to the outside, the 2nd driver including an output terminal for distributing the clock signals of the 1st driver , wherein the 1st driver is composed of a plurality of drivers having different driving powers equipped with one or more 2nd driver for distributing the source clock I / O block which is laid with the distribution wiring channel region for wiring, a clock signal internally in a straight line and the input of the 2 nd driver A distribution wiring channel region for wiring in a straight line with the 1st driver including the input terminal of the 2nd driver for receiving a clock signal from the 1st driver is mounted. Data I / O block, and the first distribution A source-synchronous soft macro comprising a wiring channel region and the second distribution wiring channel region adjacent to each other and the output terminal and the input terminal connected by a straight wiring is provided. Information processing device.

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