JP3812361B2 - Image display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image display apparatus that can be configured at low cost and can perform high-speed / high-resolution display.
[0002]
[Prior art]
FIG. 4 is a block diagram showing a configuration example of a conventional image display apparatus based on the UMA (Unified Memory Architecture) system. In this figure, reference numeral 100 is a CPU (central processing unit), 101 is a DMAC (direct memory access controller) provided in the CPU 100, 110 is a system RAM that is read / written by the CPU 100, and 120 is a line. An LCDC (liquid crystal display controller) or CRTC (CRT display controller) 130 having a built-in buffer 121 is a bus line.
[0003]
In such a configuration, the display data is written in the frame memory 111 set in the system RAM 110 by the CPU 100 by the bit map method, and the display data in the frame memory 111 is transferred to the line buffer 121 by the DMAC 101, and the LCDC ( Or output to the display device by CRTC) and displayed.
[0004]
FIG. 5 is a block diagram showing an example of the configuration of a conventional image display apparatus using a dedicated frame memory system. In this figure, 100 is a CPU, 150 is a system RAM, 151 is a frame memory, and 152 is a VDP (video display processor). , 130 is a bus line. In this apparatus, display data is written to the frame memory 151 by the VDP 152 in a bitmap manner. The display data in the frame memory 151 is read by the VDP 152 in accordance with the display timing and output to the display device.
[0005]
[Problems to be solved by the invention]
The UMA type image display apparatus shown in FIG. 4 does not require a dedicated frame memory, so that the cost can be reduced. However, since the bus line 130 is occupied for display data transfer and drawing, much of the time of the CPU 100 is used for display, and the performance of the CPU 100 is degraded. Further, since reading / writing of the frame memory 111 is performed by the CPU 100, it takes time to rewrite the frame memory 111. Therefore, there is a drawback that high-speed / high-resolution display cannot be performed.
[0006]
In the dedicated frame memory type image display apparatus shown in FIG. 5, since the VDP 152 performs writing / reading of the frame memory 151 and the CPU 100 is not involved, the performance of the CPU 100 can be improved, and the frame memory 151 can be rewritten. Since it can be performed at high speed, there is an advantage that advanced display is possible. However, if high resolution / multicolor display is to be performed, a large-capacity memory is required as the frame memory 151, which increases the cost.
The present invention has been made in view of such circumstances, and an object of the present invention is to provide an image display apparatus capable of performing high-speed / high-resolution display at low cost.
[0007]
[Means for Solving the Problems]
The present invention has been made to solve the above-described problems, and the invention according to claim 1 includes a central processing unit,
A system memory that is read / written by the central processing unit and includes a frame memory area for storing first display data for displaying a background, and the central processing unit, the system memory, and a video display processor An image display device for displaying an image, wherein the video display processor stores a moving image display memory for storing second display data for displaying a moving image and a third display data for displaying a background. A background display memory, a buffer memory to which the first display data in the frame memory is transferred by a direct memory access method, a first display data in the buffer memory, and a moving image display memory Second display data and the background display memory Comprising a synthesizing means for forming a third display data and the display data combining to the inside Li, the first display data for background, as compared to the third display data for background The number of colors that can be displayed is large, and the synthesizing unit synthesizes the display data in the order of priority of the second display data, the third display data, and the first display data. An image display device.
[0008]
According to a second aspect of the present invention, in the portable terminal device according to the first aspect, the frame memory includes a plurality of memory areas set corresponding to a plurality of display frames. The
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the image display apparatus according to the embodiment. In this figure, 100 is a CPU, 101 is a DMAC, 110 is a system RAM, and a frame memory 111 is set in the system RAM 110. Reference numeral 10 denotes a VDP. To explain the general configuration, an SRAM (static RAM) 20 based on a bitmap, a flash memory 30 in which sprite data is stored, and an image composition circuit 40 are provided.
[0010]
FIG. 3 is a block diagram showing details of the VDP 10. In this figure, 11 is a CPU interface, 12 is a DMA controller, and 13 is a line buffer. Display data is transferred from the frame memory 111 of the system RAM 110 to the line buffer 13 by DMA and written therein. Reference numerals 20 and 30 denote the above-described SRAM and flash memory, respectively, and display data output from the CPU 100 is written via the interface 11, and internal data is read by the synthesis circuit 40.
[0011]
A timing generator 14 generates a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and the like according to a display clock pulse, and outputs them to each unit. Reference numeral 17 denotes a PLL circuit that forms and outputs a display clock pulse. The combining circuit 40 superimposes the display data of the line buffer 13, the display data of the SRAM 20, and the sprite data of the flash memory 30 to form display data. Further, the display data is converted into RGB data by an LUT (lookup table) 41. Convert and output. In this case, logical operations such as transparent processing, blending processing capable of semi-transparent display, and color inversion are performed on the transparent designated pixel portion. Reference numeral 16 denotes a DAC (digital / analog conversion circuit) that converts RGB data output from the synthesis circuit 40 into an analog signal, and reference numeral 15 denotes an LCD interface that converts the output of the synthesis circuit 40 for an LCD (liquid crystal display).
[0012]
In the configuration described above, the frame memory 111 includes two frame memories 111a and 111b as shown in FIG. 2, and display data based on a bitmap is written by the CPU 100 in each of the frame memories 111a and 111b. Also, color display data of 16 colors, 256 colors, or 64K colors is written in these frame memories 111a and 111b. In addition, the SRAM 20 is written with color display data based on a bitmap of 16 colors or 256 colors. The SRAM 20 is used for background display when the number of colors is small, while the frame memories 111a and 111b are used for background display of complex images with a large number of colors.
[0013]
The flash memory 30 stores sprite data. Here, the sprite is a movable image such as a human image in a game, and coordinate data indicating a display position is supplied from the CPU 100 to the interface 11, and the synthesis circuit 40 sends the sprite data to the flash memory 30 at a timing based on the coordinate data. Read from and display.
[0014]
The following priorities are determined for each memory described above.
(1) Flash memory 30
(2) SRAM 20
(3) Frame memory 111b
(4) Frame memory 111a
Then, the synthesis circuit 40 reads the display data in each memory, superimposes them as shown in FIG. 2, and displays them according to the priority order.
[0015]
As described above, in the image display apparatus shown in FIG. 1, the VDP 10 displays a sprite image that operates at high speed. Therefore, the time of the CPU 100 is not taken by the sprite display. On the other hand, background display is performed using the frame memory 111 in the system RAM 110, thereby enabling high resolution / multicolor display. In this case, since the background display does not change at high speed, the CPU 100 does not spend much time on the background display, and there is no problem even if high-speed display processing cannot be performed.
[0016]
In the above embodiment, the SRAM 20 and the flash memory 30 are formed inside the VDP 10, but they may be provided outside the VDP 10.
[0017]
【The invention's effect】
As described above, according to the present invention, the background display is performed using the frame memory set in the system RAM, and the display control means (VDP) performs the sprite display that moves at high speed. This eliminates the need for a large-capacity external frame memory, thereby enabling high-resolution display at a low cost and, since the display control means performs sprite display, has the effect of enabling high-speed display.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.
FIG. 2 is an explanatory diagram for explaining a display operation according to the embodiment;
FIG. 3 is a block diagram showing details of the VDP 10 in the same embodiment.
FIG. 4 is a block diagram illustrating a configuration example of a conventional image display apparatus.
FIG. 5 is a block diagram illustrating another configuration example of a conventional image display device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... VDP, 20 ... SRAM, 30 ... Flash memory, 40 ... Composition circuit, 100 ... CPU, 101 ... DMAC, 110 ... System RAM, 111, 111a, 111b ... Frame memory.

Claims (2)

A central processing unit;
A system memory that includes a frame memory area that is read / written by the central processing unit and that stores first display data for displaying a background ;
An image display device for displaying an image with the central processing unit, the system memory and a video display processor,
The video display processor is
A moving image display memory for storing second display data for displaying a moving image;
A background display memory for storing third display data for displaying the background;
A buffer memory to which the first display data in the frame memory is transferred by a direct memory access method ;
A combining unit configured to combine the first display data in the buffer memory, the second display data in the moving image display memory, and the third display data in the background display memory to form display data; ,
Comprising
The first display data for background has a larger number of displayable colors than the third display data for background, and the combining means includes second display data, third display data, and third display data. An image display device comprising: combining display data in the order of priority of display data and first display data .   The image display device according to claim 1, wherein the frame memory includes a plurality of memory areas set corresponding to a plurality of display frames.

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