JP3809035B2 - MIS type transistor and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an MIS transistor and a manufacturing method thereof, and more particularly to an MIS transistor having a large driving current and a small parasitic capacitance and a manufacturing method thereof.
[0002]
[Prior art]
As the demand for miniaturization of transistors having a metal, insulating film, and semiconductor (MIS) structure increases, miniaturization of transistors having a MIS structure is steadily progressing. The miniaturization of the MIS transistor is performed using a technique called a scaling law that forms source / drain regions in proportion to the gate length. Specifically, when the gate length is reduced, this MIS transistor is reduced. This is done by reducing the junction depth of the impurity diffusion regions that become the source and drain, so-called diffusion layers, as the gate length becomes smaller.
[0003]
However, in a fine transistor whose gate length is less than 0.2 μm, the diffusion depth (Xj) becomes too shallow, the resistance at the gate increases, and the parasitic resistance of the entire transistor increases, which is substantially increased. There was a problem that the drive current decreased. Therefore, in order to reduce this parasitic resistance, it may be possible to reduce the junction depth when the introduced source and drain are silicidated, but the junction depth may be reduced. There is a problem in that the junction is not stayed in the diffusion layer but penetrates to the substrate side, causing junction leakage, because it is hard to make it shallow.
[0004]
When the junction is shallow, the problem of increased resistance or difficulty in silicidation has been solved by techniques called elevated source drain, concave transistor, reset channel transistor, etc. A structure in which the surface of the source and drain is formed higher than the channel surface of the transistor is provided (for example, SMSze Physics of Semiconductor Devices second edition, 1981, pp490). FIG. 14 shows an MIS type transistor having such a concave MOS structure, which is provided on the semiconductor substrate 1, the source / drain region 2, the channel formation surface 7 positioned therebetween, and the channel formation surface 7. SiO₂Film 51 and this SiO₂And a gate electrode 6 provided to face the channel formation surface 7 with a film 51 interposed therebetween.
[0005]
In FIG. 14, the source / drain region 2 includes a first impurity diffusion region 2 a belonging to the semiconductor substrate 1 with respect to the channel formation surface 7 and a second layer stacked on the outer side (upper side in the drawing) than the channel formation surface 7. Impurity diffusion region 2b, and such second impurity diffusion region 2b is made of SiO 2.₂The structure surrounding the gate electrode 6 with the film 5 interposed therebetween can be considered as a structure in which a groove is formed in the source / drain region 2 or a structure in which the second impurity diffusion region 2b is raised (elevated). .
[0006]
[Problems to be solved by the invention]
However, in the conventional MIS transistor having the structure shown in FIG.₂The structure is surrounded by the source / drain diffusion layer 2 with the (insulating) film 51 interposed therebetween. For this reason, the gate-drain capacitance and the source-drain capacitance increase, and the operation speed of the transistor is greatly deteriorated. There was a problem.
[0007]
As described above, the conventional MIS transistor has a problem that it is impossible to simultaneously solve the reduction of the diffusion layer resistance of the source / drain and the reduction of the gate parasitic capacitance.
[0008]
The present invention has been made to solve the above problems, and provides a MIS transistor capable of simultaneously reducing the resistance of the diffusion layer of the source / drain and the gate parasitic capacitance, and a method of manufacturing the same. Objective.
[0009]
[Means for solving the problems]
In order to achieve the above object, a MIS transistor according to the first basic configuration of the present invention includes a semiconductor substrate, a source / drain region formed on the substrate, and a channel region between the source / drain regions. And the upper surface of the source / drain formed on the semiconductor substrate is positioned closer to the gate electrode than the channel formation surface of the semiconductor substrate, and the upper surface of the source / drain is Positioned on the channel formation surface side of the boundary surface between the gate insulating film and the gate electrode provided on the channel formation surface, and the dielectric constant of the gate insulating film is higher than the dielectric constant of silicon oxide. It is characterized by being formed.
[0010]
In the MIS transistor according to the first basic configuration, a groove is formed on the upper surface of the semiconductor substrate, the bottom surface of the groove is used as the channel forming surface, and a protective film is interposed in the opening of the groove. The gate insulating film is formed, a gate electrode is positioned on the gate insulating film, and the source / drain is positioned on both sides of the channel forming surface, so that the upper surface of the source / drain region, the channel forming surface, and the boundary You may comprise so that a surface may become a predetermined positional relationship, respectively.
[0011]
In the MIS transistor according to the first basic configuration, an upper surface of a source / drain layer in which a portion sandwiching a channel formation surface in the semiconductor substrate is positioned on the gate electrode side with respect to the channel formation surface, and the channel The upper surface of the source / drain may be positioned closer to the channel formation surface than the boundary surface between the gate insulating film formed on the formation surface via a protective film and the gate electrode.
[0012]
In the MIS transistor according to the first basic configuration, an upper surface of the source / drain region provided across the channel formation surface is raised above the channel formation surface and positioned on the gate electrode side. The upper surface of the source / drain region includes a substantially flat surface that is raised and located on the gate electrode side, and an inclined surface that is inclined from the level of the flat surface to the level of the channel formation surface. You may do it.
[0013]
In the above structure, the shape of the gate electrode surrounded by the gate insulating film provided on the upper side of the channel formation surface may be a T-shaped cross section with the lower side tapered through the stepped portion. .
[0014]
Further, in the MIS transistor according to the first basic configuration, the shape of the gate electrode surrounded by the gate insulating film provided on the upper side of the channel formation surface has a cross section T in which the lower side is tapered through the step portion. It may be in the shape of a letter.
[0015]
In the above structure, the gate insulating film may be formed of a metal oxide film.
[0016]
In the above structure, the gate insulating film may be composed of at least one of a titanium oxide film, an aluminum oxide film, and a tantalum oxide film.
[0017]
In the above configuration, the dielectric constant of the gate oxide film may be set higher than the dielectric constant of the aluminum oxide film.
[0019]
  First of the present invention2The manufacturing method of the MIS transistor according to the basic configuration ofTheSource / drain regions formed on the substrate;TheAnd a gate electrode provided above the channel region between the source and drain regions, and a method of selectively forming an oxide film on the semiconductor substrate. Forming a groove by etching using the oxidized film as a mask, and laminating a polycrystalline semiconductor layer in the groove, and then polishing the upper surface of the oxide film and the polycrystalline semiconductor film, and then removing the oxide film A step of diffusing impurities on the surface of the semiconductor substrate using the polycrystalline semiconductor film as a mask to form a groove-like impurity diffusion region including the bottom side of the groove; and the groove-like impurity diffusion region Forming a gate insulating film made of a high dielectric film in the groove portion of the impurity diffusion region so that an upper surface thereof is located on a side farther from the semiconductor substrate than an upper surface of the impurity diffusion region other than the groove portion; It is characterized by comprising a step of forming a gate electrode on the upper surface of the gate insulating film.
[0020]
  Furthermore, the present invention3The manufacturing method of the MIS transistor according to the basic configuration ofTheSource / drain regions formed on the substrate;TheAnd a gate electrode provided above the channel region between the source and drain regions, and a method of selectively forming a polycrystalline semiconductor layer on the semiconductor substrate, An impurity diffusion region raised above the channel formation surface to be formed on the masked semiconductor substrate surface by diffusing impurities on the surface of the semiconductor substrate using the polycrystalline semiconductor layer formed in the mask as a mask Forming an impurity diffusion region; forming an oxide film on the surface of the raised impurity diffusion region; polishing the oxide film surface using the polycrystalline semiconductor layer as a stopper; and removing the polycrystalline semiconductor layer And a gate insulating film made of a high dielectric film in a region surrounded by the raised impurity diffusion layer and the oxide film. A step of the boundary surface between the oxide film and band formed to a height away from the substrate, is characterized in that it comprises a step of forming a gate electrode on the upper surface of the gate insulating film.
[0022]
As described above, in the MIS transistor according to the present invention, the gate insulating film using the high dielectric film and the trench or source / drain elevated structure are used to divide the actual film thickness of the gate insulating film by the average dielectric constant. Diffusion of the source and drain by providing the lower surface of the gate electrode at a position higher than the surface of the semiconductor substrate by an amount larger than the actual film thickness of the gate electrode having a capacitor equivalent film thickness equal to the required capacitor equivalent film thickness and the source / drain insulating film It is possible to simultaneously realize a reduction in layer resistance and a reduction in gate parasitic capacitance.
[0023]
In the MIS transistor according to the present invention, in the MOS transistor, the average dielectric constant of the first insulating film material used as the gate insulating film is the average dielectric constant of the second insulating film that insulates between the upper surface of the groove and the gate material. You may comprise so that it may become higher than a rate.
[0024]
Further, in such a MOS transistor, the first insulating film as the gate insulating film is constituted by a laminated structure of an insulating film having a dielectric constant higher than that of the SiO 2 film and a buffer insulating film for protecting the insulating film. Also good.
[0025]
Also, in the MIS transistor, the gate insulating film is divided by the average dielectric constant and the amount equivalent to the capacitor equivalent film thickness obtained by dividing the capacitor equivalent film thickness is larger than the actual film thickness of the second insulating film. You may comprise so that the lower surface of a gate electrode may be located in a position higher than the semiconductor substrate surface. As described above, according to the present invention, it is possible to simultaneously reduce the resistance of the diffusion layer of the source / drain and the gate parasitic capacitance.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of an MIS transistor and a method for manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.
[0027]
FIG. 1 is a cross-sectional view showing a schematic configuration of a MIS transistor according to the first embodiment of the present invention. In the figure, hatching representing a cross section is omitted for the sake of clarity. Further, the constituent elements denoted by the same reference numerals as those in FIG. 14 indicate the same or corresponding constituent elements as those of the conventional MIS transistor.
[0028]
In FIG. 1, reference numeral 1 denotes a semiconductor substrate, and an impurity region 2 used as a source / drain through a channel region 7 is provided on the surface side of the semiconductor substrate 1. The impurity region 2 is used as a drain electrode and the other as a source electrode when operating as a transistor, and a recess or a groove 4 is formed in a portion of the impurity region 2 that extends over the channel formation surface 7 between them. ing. A high dielectric gate insulating film 5 is provided in the groove 4 via a protective film 3, and a gate electrode 6 is provided on the upper side of the high dielectric gate insulating film 5. The impurity region 2 used as the source / drain and the gate electrode 6 are insulated by an insulating film 13. The high dielectric gate insulating film 5 is made of SiO in the conventional MIS type transistor shown in FIG.₂The dielectric constant of the film 5 is higher than 3.9.
[0029]
What is important in the above configuration is that the level La of the upper surface of the source / drain between the second impurity diffusion region 2b and the insulating film 13 is located farther from the semiconductor substrate 1 than the level Lb of the channel formation surface 7. At the same time, it is located closer to the semiconductor substrate 1 than the level Lc on the lower surface of the gate electrode 6.
[0030]
As in the conventional MIS type transistor shown in FIG. 14, the impurity region 2 has a first impurity diffusion region 2a belonging to the semiconductor substrate 1 with respect to the channel formation surface 7 and an outer side with respect to the channel formation surface 7 (FIG. In FIG. 2, the second impurity diffusion region 2b is stacked on the upper side. The protective film 3 is formed of, for example, SiN or an oxynitride film to protect the gate insulating film 5, and a first protective film located between the channel forming surface 7 and the gate insulating film 5. 3a and a second protective film 3b located between the second impurity diffusion region 2b.
[0031]
In the above configuration, the MIS transistor according to the first embodiment of the present invention is used as a source / drain from the channel formation surface 7 on which a channel through which a current flows is formed, like the conventional MIS transistor of FIG. The impurity diffusion region 2 to be formed is formed on the opposite side of the semiconductor substrate 1 by the thickness of the second impurity diffusion region 2b. Therefore, compared to the case where the source / drain regions are formed only in the first impurity diffusion region 2a below the channel formation surface 7, the diffusion layer resistance can be lowered, and nickel (Ni) Also, when forming silicide with titanium (Ti) or the like, it is possible to avoid occurrence of junction leakage caused by silicidation to the junction surface.
[0032]
Further, by providing the lower surface 8 of the gate electrode 6 at a position higher than the upper surface of the impurity diffusion region 2 used as the source / drain, that is, on the side farther from the semiconductor substrate 1 side, the gate electrode and the source / drain causing degradation in performance. The capacitance can be significantly reduced as compared with the conventional concave MOS shown in FIG.
[0033]
Furthermore, the distance between the gate electrode 6 and the source / drain electrode 2b can be made larger than in the conventional example, and the electric field can be kept small. Therefore, the leakage current between them can be reduced and dielectric breakdown can be prevented. This feature applies to all embodiments described below.
[0034]
Although not shown in the figure, in a conventional MIS transistor in which the channel formation surface is flush with the upper surfaces of the source / drain regions, the gate insulating film between the gate electrode and the channel formation surface is made of SiO 2.₂If it is formed of a film, the lower surface 8 of the gate electrode 6 is made of this SiO.₂The insulating film 13 is provided to be higher from the surface 7 than the thickness of the film and insulates the gate electrode from the source / drain.₂By using a film, the parasitic capacitance can be reduced as compared with a planar conventional MOS transistor.
[0035]
For example, in the conventional technique, when the gate length is 0.1 micron, the thickness of the gate oxide film is scaled to about 3 nm. However, the present invention is applied to Ta2O5 having a relative dielectric constant of about 25 and SiN having a relative dielectric constant of 7 nm. .5) When the device is designed with the protective film, in order to make the surface charge amount Qs of the transistor equal, SiO₂If the equivalent film thickness of 3 nm is maintained, the actual SiN film thickness of the first protective film 3a is 1 nm, and SiO 2₂The equivalent film thickness is “1 nm × 3.9 / 7.5 = 0.52” nm, and the SiO 2 equivalent film thickness of the high dielectric gate insulating film 5 (Ta 2 O 5) is “3 nm−0.52 nm = 2.48 nm”. The actual film thickness is “2.48 nm × 25 / 3.9 = 15.9 nm”.
[0036]
That is, if the depth of the groove of the impurity diffusion region 2 to be the source / drain is “15.9 nm (for the gate insulating film 5) +1 nm (for the protective film 3a) = 16.9 nm”, the lower surface 8 of the gate electrode 6 Becomes the same height as the surface of the source / drain, and if it is 13.9 nm, the parasitic capacitance is about the same as that of a MOS transistor using a 3 nm oxide film on the conventional scaling trend. Here, according to the conventional scaling, the depth of the diffusion layer of the transistor is about 40 nm even if it is a 0.1 micron transistor, and the parasitic resistance is lowered by increasing the thickness of the 13.9 nm or 35% diffusion layer. be able to.
[0037]
Where SiO₂The relative dielectric constant of ε, SiO₂The film thickness is TSiO₂The relative dielectric constant of the high dielectric gate insulating film 5 is ε₅, T₅, The relative dielectric constant of the protective film 3 is ε₃, T₃Then, TSiO₂Thickness SiO₂The film thickness that gives the parallel plate capacity equivalent to the film is
TSiO₂/ ΕSiO₂  = T₃/ Ε₂  + T₅/ Ε₅
Should be satisfied. A 1 nm thick SiN film is used as the protective film, and SiO₂, SiN having a relative dielectric constant of 3.9 and 7.5, respectively,
T5 = ε₅(TSiO₂/3.9-1/7.5) (nm) and the thickness on the conventional scaling trend TSiO₂And the redness of the trench, which is equivalent to the parasitic capacitance, is the insulating film material between the gate and the source and drain.₂Or if it has an equivalent dielectric constant,
Dconcave = ε₅(TSiO₂/3.9-1/7.5)-TSiO₂
Given by. If the groove is shallower than this, the parasitic capacitance becomes smaller.
[0038]
In the case of using a titanium oxide film TiO2 film having a relative dielectric constant of about 80 and being thermally stable and requiring no protective film from that point, the same calculation with the protective film portion removed,
Dconcave = ε₅× TSiO₂/3.9-TSiO₂
If the groove depth is 58.5 nm, the parasitic capacitance is the same as that of a conventional MOS transistor using a 3 nm oxide film, and 58.5 nm, that is, a conventional diffusion layer having a depth of 40 nm is used. In comparison, the parasitic resistance can be reduced by increasing the thickness of the 150% diffusion layer.
[0039]
Next, a method of manufacturing the MIS transistor according to the first embodiment of the present invention will be described with reference to FIGS. First, as shown in FIG. 2A, SiO 2 is formed on a silicon substrate 1 as a semiconductor substrate.₂A film 9 is deposited and etched by lithography. Next, SiO₂The groove 4 is formed by reactive ion etching (RIE-Reactive Ion Etching-) using the film 9 as a mask (FIG. 2B).
[0040]
Next, as shown in FIG.₂After depositing a thin sacrificial oxide film 11 on the surface of the film 9 and the groove 4 of the silicon substrate 1, a polysilicon 10 is deposited, and a chemical mechanical polishing method (-CMP-Chemical Mechanical Polishing) or an etch back technique is performed. Use SiO₂The top surface of the film 9 is flattened. At this time, the thin sacrificial oxide film 11 is laminated in order to separate the polysilicon 10 and the silicon substrate 1.
[0041]
Next, as shown in FIG. 2 (d), the silicon oxide (SiO₂After the film 9 is removed, the source / drain region 2 is formed by using the polysilicon 10 as a mask and using an ion implantation technique or a solid phase diffusion technique. Next, the polysilicon 10 and the sacrificial oxide film 11 are removed by, for example, chemical dry etching (CDE-Chemical Dry Etching-). Thereafter, as shown in FIG. 2E, a SiN film 3 as a protective film is formed by deposition or thermal nitridation. Next, a high dielectric film 5 is formed by sputtering or the like, and a gate electrode 6 is further deposited. Finally, a silicon (Si) oxide film 12 is formed, and a semiconductor device having the same structure as the MIS transistor shown in FIG. 1 is manufactured.
[0042]
Next, the manufacturing method and configuration of the MIS transistor according to the second embodiment of the present invention will be described with reference to FIGS. First, a method for manufacturing a MIS transistor will be described with reference to FIGS. A dummy polysilicon 10 is formed on the semiconductor substrate 1 shown in FIG. 3A via the sacrificial oxide film 11 and patterned, and is further oxidized to wrap the dummy polysilicon 10 with an oxide film, and then FIG. As shown in FIG. 2B, the source / drain region 2 is formed by ion implantation or the like.
[0043]
Next, after the silicon is elevated by a selective epitaxial growth technique, impurities are again implanted and diffused into the raised portion by additional ion implantation. In the manufacturing method of the MIS transistor according to the first embodiment, since the groove 4 is first formed and impurities are implanted and diffused into the groove from above, it is difficult to control the depth of the source / drain region 2. In the MIS transistor manufacturing method according to the second embodiment, the depth of the source / drain region 2 below the channel formation surface 7 is determined by the degree of impurity implantation from the channel formation surface 7. The effect is easy.
[0044]
Next, a silicon (Si) oxide film 12 is first deposited on the source / drain region 2 while leaving the polysilicon 10, and the silicon oxide film 12 is formed on the upper surface of the polysilicon 10 by CMP using the polysilicon 10 as a stopper. Until flat. Here, as shown in FIG. 3C, the polysilicon 10 and the sacrificial oxide film 11 are peeled off by CDE or the like, and silicon nitride (SiN) extends from the side surfaces of the silicon oxide film 12 and the source / drain regions to the upper surface of the channel formation surface 7. A protective film 3 is deposited.
[0045]
Next, as shown in FIG. 3D, a high dielectric gate insulating film 5 is deposited to a position higher than the upper surface of the source / drain region 2 by sputtering, CVD or the like. When employing such a process, if the thickness of the high dielectric gate insulating film 5 is shallower than the depth of the trench, the insulation between the gate electrode and the source / drain must be maintained by the protective film 3. Compared with the case where the high dielectric gate insulating film 5 is provided higher than the groove 4 as in the present embodiment, the thickness of the protective film 3 must be increased.
[0046]
Next, as shown in FIG. 3 (e), a gate electrode 6 is deposited on the high dielectric gate insulating film 5 up to substantially the same height as the silicon oxide film 12 by sputtering, CVD or the like. Further, as described above, if the film thickness of the high dielectric gate insulating film 5 is shallower than the depth of the groove, the distance between the gate electrode 6 and the upper surface of the source / drain region 2 is separated via the protective film 3. In this state, the electrical characteristics of this part become critical because the withstand voltage of this part becomes critical.
Dconcave = ε₅(TSiO₂/3.9-1/7.5)-TSiO₂
I was trying to satisfy. Therefore, it is desirable to make the groove portion shallower in order to improve the breakdown voltage of the transistor. Alternatively, it is desirable to increase the thickness of the protective film 3 in the upper part of the groove from the lower part in order to improve the breakdown voltage. For this purpose, CDE or the like is performed in the step shown in FIG. 3D, so that the space between the high dielectric gate insulating film 5 and the source / drain region 2 is slightly etched back and filled.
[0047]
According to the manufacturing method of the MIS transistor according to the second embodiment as described above, SiO 2₂Transistors having substantially the same configuration can be obtained through steps different from the manufacturing method according to the first embodiment in which the trench 4 is formed using the film as a mask and then the source / drain region 2 is formed. However, a difference between whether the groove 4 is formed on the upper surface of the substrate 1 or whether the source / drain region 2 is further increased from the level of the channel forming surface 7 by forming the source / drain region 2 on the substrate 1 is different. There is only there.
[0048]
In each of the MIS transistors according to the first and second embodiments, the protective film 3 is formed between the high dielectric gate insulating film 5 and the source / drain region 2. In some cases, the protective film 3 is not necessary by adjusting the temperature of the material 5 or the low temperature of the process. FIG. 4 shows the MIS transistor according to the third embodiment when the protective film 3 is not provided as described above. In FIG. 4, the protective film (protective film 3a in FIG. 1) is not provided between the channel forming surface 7 of the silicon substrate 1 as the semiconductor substrate and the high dielectric gate insulating film 5, and the gate insulating film 5 The protective film 3b is provided only between the side wall of the first electrode and the second impurity diffusion region 2b.
[0049]
Next, a manufacturing method of the MIS transistor according to the fourth embodiment of the present invention will be described with reference to FIGS. The steps from FIG. 5A to FIG. 5C are basically formed in substantially the same manner as the MIS transistor manufacturing method according to the first or second embodiment. Next, the sacrificial oxide film 11 and polysilicon 10 shown in FIG. 5B are peeled off by CDE or the like, and silicon nitride (SiN) extends from the side surfaces of the silicon oxide film 12 and the source / drain region 2 to the upper surface of the channel formation surface 7. ) A protective film 3 is deposited, and a high dielectric gate insulating film 5 is deposited by CVD or sputtering.
[0050]
Next, as shown in FIG. 5C, the high dielectric gate insulating film 5 deposited by CVD or sputtering is planarized to the upper surface of the oxide film 12 using CMP technology. In the MIS type transistor manufacturing method according to the third embodiment, the thickness of the high dielectric gate insulating film 5 is determined by the thickness of the silicon oxide film 12 and the depth of the groove 4. There is an excellent effect that the film thickness is easy to control.
[0051]
However, in the MIS transistor manufacturing method according to the fourth embodiment, since the gate electrode 6 is formed by performing lithography again, it is difficult to self-align the gate electrode 6 in the groove 4. For this reason, as shown in FIG.5 (e), it forms larger than the opening area of the groove | channel 4. As shown in FIG. Therefore, although the parasitic capacitance of the gate electrode 6 is somewhat increased, the silicon oxide film 12 is sufficiently thick and the dielectric constant of the silicon oxide film 12 is small, so that it is not greatly affected. .
[0052]
FIG. 6 shows a cross section of a MIS transistor according to the fourth embodiment manufactured by the manufacturing method shown in FIGS. 5 (a) to 5 (e). In FIG. 6, the MIS type transistor includes a silicon substrate 1 as a semiconductor substrate, a first impurity diffusion region 2 a located on the substrate 1 side with respect to the channel formation surface 7, and a gate electrode 6 side on the channel formation surface 7. A source / drain region 2 including a second impurity diffusion region 2b, a silicon oxide film 12, and a protective film 3 provided on the inner wall of the trench 4 formed in the silicon oxide film 12 and the second impurity diffusion region 2b, The high dielectric gate insulating film 5 formed in the trench 4 with the protective film 3 interposed therebetween, and a wider area than the range surrounded by the protective film 3 on the gate insulating film 5. And a gate electrode 6.
[0053]
The MIS transistor according to the first to third embodiments described above is described as being configured such that the width of the gate electrode 6 is the same as that of the gate insulating film 5 located in the trench 4. The MIS transistor according to the fourth embodiment has been described as being formed so that the gate electrode 6 has a wider range than the gate insulating film 5 because of difficulty in self-alignment. Of course, the present invention can also be applied to a type of transistor in which a side wall is provided on the gate electrode 6 in an LDD (Lightly Doped Drain) structure as in the fifth embodiment shown in FIG.
[0054]
In FIG. 7 showing the MIS transistor according to the fifth embodiment, reference numeral 1 is a silicon substrate as a semiconductor substrate, 7 is a channel formation surface, 2 includes a first impurity diffusion region 2a and a second impurity diffusion region 2b. Source / drain region, 3 is a protective film, 5 is a high dielectric gate insulating film, 6 is a gate electrode, 8 is silicon dioxide (SiO 2) provided around the gate electrode 6₂).
[0055]
FIGS. 8A to 8E are process diagrams showing a method for manufacturing a MIS transistor according to the fifth embodiment. As shown in FIGS. 8A and 8B, a SiN film 3a serving as a gate insulating film on the semiconductor substrate 1 and, for example, Ta₂O₅A high dielectric film 5 made of TiN, TiN and polysilicon 6 serving as gate electrodes are sequentially deposited, and a portion serving as a gate electrode is formed from the polysilicon 6 by etching as shown in FIG. 8C. Next, as shown in FIG. 8D, SiO or the like is formed around the gate electrode 6 by CVD or the like.₂The gate insulating film 5 is formed by CDE or the like using the gate electrode 6 and the side wall 8 as a mask.
[0056]
Finally, as shown in FIG. 8E, after etching using the polysilicon gate electrode 6 and the laminated structure of the sidewall 8 and the gate insulating film 5 as a mask, the sidewall insulating film 3b is formed, and the source After the drain is raised to form the impurity diffusion region 2b, the source / drain region 2 is formed by ion implantation, solid phase diffusion, or the like. As in the first to fourth embodiments, the source / drain region 2 includes a first impurity diffusion region 2 a formed so as to be located on the inner side of the substrate 1 with respect to the channel formation surface 7, and the channel formation surface 7. And the second impurity diffusion region 2b, which is closer to the gate electrode 6 side and whose upper surface is lower than the lower surface of the gate electrode 6.
[0057]
The MIS transistor according to the fifth embodiment formed by the steps shown in FIGS. 8A to 8E has the structure shown in FIG. 7, and the periphery of the high dielectric gate insulating film 5 is as follows. At least the lower surface side and the side wall side are surrounded by the protective film 3, and the first protective film 3a is formed between the lower side of the gate insulating film 5 and the channel forming surface 7 of the substrate 1 to form a second impurity diffusion region. A second protective film 3b is provided between 2b and the gate insulating film 5.
[0058]
The present invention is not limited to the first to fifth embodiments described above, and can be applied to a transistor according to a sixth embodiment having the configuration shown in FIG. In FIG. 9, some of the above are provided in that a p + semiconductor substrate 1, a channel forming surface 7, a source region 2A, a drain region 2B, a high dielectric gate insulating film 5, and a gate electrode 6 are provided. The configuration is substantially the same as that of the MIS type transistor of the embodiment, particularly the fifth embodiment.
[0059]
In the transistor according to the sixth embodiment shown in FIG. 9, the respective terminals, that is, the gate terminal 16, the source terminal 17, and the drain terminal 18 are provided in each electrode region via the low resistance contact 15. A protective film 3 a is provided between the channel forming surface 7 and the gate insulating film 5, and the protective film 3 b is also formed between the gate electrode 6, the low resistance contact 15, and the side wall 8 surrounding the gate terminal 16. Is provided.
[0060]
The gate insulating film 5 is configured such that 0x corresponds to 1.5 nm or less, and the low-resistance contact 15 is “Rcontact <10^-8Ωcm²The channel forming surface 7 is an extremely shallow channel (Rp ˜15 nm, dRp ˜7 nm). Further, the source region 2A and the drain region 2B are formed to be the second impurity diffusion region 2b which is elevated with a low resistance of “Xj <10 nm, R <16 Ωμm”.
[0061]
Also in the transistor according to the sixth embodiment having such a configuration, the upper surface of the source / drain region is located on the gate electrode side with respect to the channel formation surface, and is located on the substrate side with respect to the bottom surface of the gate electrode. This is one of the preferred embodiments of the MIS transistor according to the present invention.
[0062]
Next, a semiconductor device according to a seventh embodiment of the present invention will be described with reference to FIGS. First, FIG. 10 shows a cross-sectional structure of a semiconductor device according to the seventh embodiment of the present invention.
[0063]
In FIG. 10, for example, on the upper part of the semiconductor layer 105 made of p-type Si, for example, TiO₂For example, poly Si, amorphous Si, TiN, W, Pt, RuO through a gate insulating film 113 made of aluminum, alumina, tantalum oxide film, barium titanate, or lead zirconium titanate.₂, IrO₂A gate electrode 114 made of is formed. Here, when the thickness of the portion of the gate insulating film 113 in contact with the semiconductor layer 105 is t (nm) and the relative dielectric constant is ε, the relationship of t <1.3ε is satisfied.
[0064]
Further, in the region 105 on both sides of the gate electrode, for example, P, Sb, or As is grown by ion implantation or solid phase diffusion, and a source having conductivity opposite to that of the semiconductor layer 105 is formed. A diffusion layer and a drain diffusion layer 110 are formed to form an n-type MISFET. Furthermore, a semiconductor region 104 made of Si, SiGe, or SiGeC to which, for example, P, Sb, or As is added is formed on the source and drain diffusion layers 110. The semiconductor region 104 is formed above the interface between the gate insulating film 113 and the semiconductor layer 105 in the stacking direction and has a so-called elevated source / drain structure.
[0065]
Further, an insulating film 109 made of, for example, a silicon nitride film is formed on the side wall of the gate insulating film 113 where the gate electrode 114 is not formed. Further, an insulating film 108 made of, for example, a silicon oxide film is formed between the insulating film 109 and the conductive region 104. Further, a conductor layer 115 made of, for example, cobalt silicide, nickel silicide, or titanium silicide is formed on the upper surface of the region 104 where the insulating films 108 and 113 are not formed. The characteristic configuration in the seventh embodiment is that the height of the upper surface of the conductive region 104 is formed lower than the height of the bottom of the gate electrode 114. Thus, the source / drain region can be formed in an elevated structure while keeping the capacitance between the gate electrode 114 and the conductive region 104 small, and the junction depth of the conductive region 104 can be reduced. In addition, a low-resistance source / drain with a short channel effect can be realized.
[0066]
Further, an insulating film 111 and an insulating film 112 made of, for example, a silicon oxide film are stacked on the upper surface of the conductive layer 115. It is desirable that the upper surface height of the gate insulating film 113 be lower than the upper surface height of the insulating film 112 in order to form the contact 116 in a good shape even when the gate insulating film 113 is difficult to etch. . Further, an insulating film 118 made of, for example, a silicon oxide film or a silicon nitride film is formed on the gate electrode 114, the gate insulating film 113, and the insulating film 112. Further, a contact electrode 116 made of, for example, polycrystalline silicon doped with Al, P, or B, WSi, TiSi, W, AlSi, AlSiCu, Cu, or TiN is formed above the gate electrode 114 and the electrode 115. Yes.
[0067]
Further, an upper wiring layer 117 is formed on the contact electrode 116 by depositing a metal made of polycrystalline silicon doped with Al, P, or B, WSi, TiSi, AlSi, AlSiCu, Cu, or W. . In FIG. 10, the contact electrode 116 and the wiring layer 117 for the gate electrode are shown in the same cross section together with the contact electrode 116 and the wiring layer 117 for the source / drain electrode. However, they do not have to be in the same cross section. ) And as shown in FIG. 11 (b), they may be formed in different height sections cut along different planes.
[0068]
Next, the manufacturing process of the semiconductor device according to the seventh embodiment will be described with reference to FIGS. First, for example, a boron concentration of 10¹⁵cm^-3The semiconductor layer 105 in which the p-type region is formed is prepared. Next, boron is added to this p-type semiconductor layer 105.¹²-10¹⁵cm^-2The concentration of the semiconductor layer 105 may be optimized by implanting ions to the extent that wells are diffused. The ion implantation energy is between 100 eV and 1000 eV, for example. The concentration of these well regions is 10¹⁵cm^-3-10¹⁹cm^-3And it is sufficient. Next, although not shown in the figure, an element isolation region including, for example, LOCOS isolation or trench isolation is formed.
[0069]
Next, boron or indium may be ion-implanted into the p-type semiconductor layer 105 and well diffusion may be performed to optimize the concentration of the semiconductor layer 105. Next, the dummy gate insulating film 102 is formed by oxidizing or nitriding the surface of the semiconductor layer 105, for example, by 3 to 50 nm, and a polycrystalline silicon film to be the dummy gate electrode 101 is deposited on the entire surface of, for example, 10 to 200 nm. Further, after forming a silicon oxide film to be the insulating film 106 by, for example, depositing the entire surface of 2 to 200 nm or oxidizing the polycrystalline silicon film, the polycrystalline film to be the insulating film 106 and the dummy gate electrode 101 by lithography and reactive ion etching. The dummy gate electrode 101 is formed by processing the silicon film so as to reach the insulating film 102. Next, a silicon oxide film to be the insulating film 103 is deposited on the entire surface with a thickness of 2 to 50 nm, for example, and then processed by anisotropic etching, so that the sidewall insulating film is formed on the side walls of the dummy gate electrode 101 Leave 103. Thereafter, the insulating film 102 is etched using the insulating film 103 as a mask to expose the semiconductor layer 105. The sidewall insulating film 103 and the insulating film 106 deposited immediately before lithography surround the dummy gate electrode 101, and it becomes easy to selectively grow a semiconductor on the source / drain layer.
[0070]
Next, as shown in FIG. 12A, for example, the semiconductor layer 104 is formed to a thickness of, for example, 5 to 100 nm by using a selective epitaxial growth method or a selective deposition method for Si, SiGe mixed crystal, or SiGeC mixed crystal. To do. At this time, doping is performed at the same time, and the semiconductor layer 104 is doped with a donor impurity.¹⁶-10²¹cm^-3It is desirable to add As, Sb, or P at a low concentration to form a low-resistance shallow junction. The semiconductor layer 104 is, for example, AsH.₃And PH₃As or P may be adsorbed on the surface of the semiconductor layer 104, and then, for example, Si, SiGe mixed crystal, or SiGeC mixed crystal may be formed by selective epitaxial growth.
[0071]
Further, in particular, by patterning the semiconductor substrate in the {100} plane and patterning the gate parallel to the <100> orientation, a {311} plane is formed at the gate side wall as shown in FIG. Since the structure can be formed so as to move away from the top, the capacitance between the gate and the source and the capacitance between the gate and the drain can be kept smaller.
[0072]
Next, for example, by heating at 700 to 1100 ° C. in an atmosphere of 0.01 to 60 minutes, for example, Ar or N 2, the impurity-added n-type region 110 is formed in the p-type semiconductor layer 105 as shown in FIG. Add a diffusion step. The diffusion time is typically such that the n-type region 110 is formed under the dummy gate layer 101 and is formed so as to reach under the gate electrode 114 formed later. Desirable to enlarge.
[0073]
In the process of forming the semiconductor layer 104 and the n-type region 110, for example, first, As, P, and SB are applied with an acceleration voltage of 1 to 100 eV, 10¹³-10¹⁶cm^-2Alternatively, the n-type region 110 may be formed by ion implantation, and then the semiconductor layer 104 may be selectively epitaxially grown. Further, after forming the semiconductor layer 104 to which impurities are not intentionally added, As, P, and Sb are applied at acceleration voltages of 1 to 300 eV, 10¹³-10¹⁶cm^-2The step of forming the n-type region 110 by ion implantation may be substituted.
[0074]
Further, for example, a silicon oxide film is deposited on the entire surface of 2 to 100 nm to form the insulating film 108. Next, for example, a silicon nitride film is deposited on the entire surface of 10 to 300 nm, and the insulating film 109 is formed on the side wall of the side wall insulating film 108 formed by anisotropic etching, thereby obtaining the shape shown in FIG. it can. Here, the insulating film 108 is a buffer layer for stress relaxation and etching selectivity and damage relaxation of the insulating film 109, and there is a particular problem with respect to the stress of the insulating film 109 and the etching selectivity of the insulating film 109 with respect to the semiconductor layer 104. If not provided, the insulating film 108 is not necessarily provided.
[0075]
Further, the sum of the thicknesses of the insulating film 108 and the sidewall insulating film 103 is made thinner than the thickness of the insulating film 102, so that the insulating film 109 is exposed when the insulating film 102 is peeled, and gate insulation is performed. This is desirable because it defines the width of the film 113. The interval between the insulating films 109 is set to be twice or more the thickness of the portion of the gate insulating film 113 in contact with the semiconductor layer 105. Further, after the insulating film 108 on the semiconductor layer 104 is removed by etching using the insulating film 109 as a mask, silicide or metal is selectively formed on the semiconductor layer 104 serving as a source / drain region, and a source or drain electrode 115 is formed. Form. For example, Ni, Co or Ti is deposited on the entire surface of 0.01 to 0.03 μm, and NiSi, CoSi or Ti is selectively formed on the semiconductor layer 104 to be a source / drain region by performing a thermal process of 600 ° C. or more. TiSi is formed, and the remaining metal is removed by etching with, for example, a sulfuric acid hydrogen peroxide solution.
[0076]
Further, for example, a silicon oxide film is deposited on the entire surface of 5 to 100 nm to form an interlayer insulating film 111. Next, for example, a silicon oxide film, PSG, BPSG, or BSG is deposited on the entire surface of 50 to 1000 nm, and planarized by, for example, chemical mechanical polishing to form the interlayer insulating film 112. Thereafter, the upper portion of the dummy gate electrode 101 is patterned by lithography and anisotropic etching, and as shown in FIG. 12C, the interlayer insulating film 112, the interlayer insulating film 111, the buffer insulating film 108, and the insulating film 106, a part of the sidewall insulating film 103 is etched so that the dummy gate electrode 101 is partially exposed.
[0077]
At this time, the films 112, 111, 108, 106 and 103 are formed of a silicon oxide film, and the insulating film 109 is formed of a silicon nitride film, so that the films 112, 111, 108 are left with the insulating film 109 remaining. , 106 and 103 can be selectively etched. Although illustration is omitted, the resist used for patterning after this etching may be removed with, for example, ashing or aqueous hydrogen peroxide solution before etching the film 102. It is desirable to prevent contamination with organic matter.
[0078]
Next, for example, all the dummy gate electrodes 101 are removed by reactive etching using a gas containing HBr. At this time, the membranes 112, 111, 108, 106 and 103 are left by maintaining selectivity. Further, for example, all the dummy gate insulating film 102 made of the silicon oxide film is removed by dilute hydrofluoric acid, an aqueous ammonium fluoride solution, or HF vapor. At this time, the film 108 and the film 103 made of the silicon oxide film are also etched away, and the side wall insulating film 109 made of the silicon nitride film is left behind, and the gate length can be defined by the interval. In the step of removing the film 102, it is preferable to perform wet etching instead of ion etching so as not to damage the semiconductor layer 105.
[0079]
Then, for example, TiO₂And Al₂O₃A gate insulating film 113 made of (alumina) or a tantalum oxide film, strontium titanate, barium titanate, or lead zirconium titanate is deposited to a thickness of 10 to 200 nm. Furthermore, for example, poly Si, amorphous Si, TiNW, Pt, RuO₂Or IrO₂A gate electrode 114 made of is deposited on the entire surface with a thickness of 10 to 200 nm to obtain the shape of FIG. At this time, the interlayer insulating films 111 and 112 are formed of a silicon oxide film similarly to the film 102, and further recede when the film 102 is etched, and the etching opening becomes larger above the film 109. Therefore, the width of the gate electrode 114 in this portion is also wider than that of the bottom portion, so that a so-called T-shape gate is obtained. This shape is desirable for reducing the resistance of the gate electrode and keeping the capacitance between the gate electrode and the source / drain electrode small. The opening width at this time is preferably such that the edge of the interlayer insulating film 111 stays on the sidewall insulating film 109 in order to form a good T-shape. Further, when the uniformity of the gate insulating film 113 is not good, as shown in FIG. 13D, a shape that becomes partially narrower toward the upper side in the stacking direction can be obtained. When the gate electrode 114 is deposited in this state, a notch (void-void-) is formed below the gate electrode, as shown in FIG.
[0080]
Next, etching is performed until the film 113 is exposed while planarizing the entire surface of the gate electrode 114 by, for example, a chemical mechanical polishing method. Further, the entire surface of the film 113 is etched until the interlayer insulating film 112 is exposed, thereby obtaining the shape of FIG. If the film 113 can be easily anisotropically etched in a subsequent contact formation step, the step of removing the film 113 can be omitted.
[0081]
After that, although illustration is omitted, for example, an interlayer insulating film 118 made of BSG, PSG, BPSG is deposited, for example, 20 to 1000 nm as a silicon oxide film, and then a wiring contact 116 is formed by lithography and reactive ion etching. To do. The contact 116 has a depth that reaches the gate electrode 114 or the source / drain conductor electrode 115. The contact 116 may be polycrystalline silicon doped with, for example, Al, P, or B, WSi, TiSi, W, AlSi, AlSiCu, Cu or TiN may be deposited or selectively grown to be buried. Further, a metal composed of polycrystalline silicon doped with Al, P, or B, WSi, TiSi, AlSi, AlSiCu, Cu, W is deposited to a thickness of 20 to 500 nm, and an upper wiring layer 117 is formed to complete.
[0082]
If the manufacturing method of the MIS transistor according to the seventh embodiment is used, the silicide of the source / drain electrode is activated before the gate insulating film 113 is formed, so that the gate insulation such as a high temperature thermal process and hydrogen annealing is performed. It is not necessary to perform a process for deteriorating the characteristics of the film 113 after forming the gate insulating film. Therefore, a highly reliable process can be realized.
[0083]
Further, the width of the gate electrode facing the semiconductor region 105 is set to (width of the dummy gate 101) + (thickness of the insulating film 103) * 2 + (thickness of the insulating film 108) * 2- (side wall of the gate insulating film 113) The thickness of the dummy gate 101 can be made smaller. Therefore, a gate length smaller than that of lithography can be realized by adjusting the widths of the insulating film 103 and the insulating film 108.
[0084]
FIG. 11A and FIG. 11B are plan views of a single MISFET showing the positional relationship between the gate electrode 114, the source / drain region 110, and the channel region in this structure. In both figures, reference numeral 119 indicates an element isolation film made of LOCOS isolation or trench isolation, for example. Further, the positions of the contacts 116 are indicated by circles, and it is assumed that one contact is formed for each of the gate, the source, and the drain. The semiconductor region is a rectangular region sandwiched between two source / drain electrodes 110 and a dot-and-dash line between them, and surrounded by the solid line of the gate electrode 114, and is formed under the gate electrode 114. The boundary of the part is shown with the dashed-dotted line.
[0085]
In FIG. 11A, the lower width of the gate electrode 114 indicated by the dotted line is made constant over the semiconductor region surrounded by the element isolation 119. By doing so, even if the lithography of the gate electrode is shifted in the vertical direction, a constant gate length can be obtained at all times, and resistance against memory errors can be provided by combining transistor characteristics. FIG. 11B shows a modification of the gate electrode pattern. The gate length (= a) at the boundary between the element isolation 119 and the semiconductor region is longer than the gate length (= b) inside the semiconductor region. In the gate insulating film 113 formed by the deposited film, the film thickness deposited on the bottom surface of the groove increases as the opening width of the groove increases. Therefore, by adopting the structure of FIG. 11B, the gate insulating film at the boundary between the element isolation 119 and the semiconductor region can be made larger than the plane portion, and the breakdown voltage and leakage current characteristics at this portion are improved. Can be made. Here, when trench isolation is used for the element isolation film 119, for example, when the element isolation film 119 is etched by the process of etching the dummy gate electrode 102, and the element isolation film 119 is formed below the semiconductor region, Since the semiconductor region is convex toward the element isolation film 119 side and the gate electric field is concentrated, the threshold value is lowered. However, this can be solved by taking the structure of FIG.
[0086]
The present invention is not limited to the above-described embodiments. In the above-described embodiment, the insulating films 12, 111, 112, 113, 102, 103, 106, 108, 118, 109 are formed by thermal oxidation, oxygen is applied at a low acceleration energy of about 30 keV. An implanted oxide film may be formed, or a method of depositing an insulating film, a method of depositing a silicon nitride film, or a combination thereof may be formed. In addition, the element isolation film and the insulating film forming method itself are other methods for converting silicon into a silicon oxide film or a silicon nitride film, for example, a method of injecting oxygen ions into the deposited silicon, or a method of oxidizing the deposited silicon. May be used. Of course, a silicon nitride film, a tantalum oxide film, a ferroelectric film such as strontium titanate, barium titanate, lead zirconium titanate, a single layer film of a paraelectric film, or a composite film thereof may be used for this insulating film. it can.
[0087]
In the above embodiment, the p-type Si substrate is used as the semiconductor layers 7 and 105. However, the present invention is not limited to this, and an n-type Si substrate, SOI substrate, GaAs substrate, or InP substrate is used instead. Also good. Further, the present invention may be applied to a p-type MISFET instead of an n-type MISFET. In this case, the n-type in the above-described embodiment is read as p-type, the p-type is read as n-type, and doping impurities species As, P, Sb are used. Is replaced with either In or B. In the case of ion implantation, As, P, and Sb are replaced with In, B, and BF.₂It may be read as either of these.
[0088]
The gate electrodes 6, 10, 114 are made of single crystal silicon, polycrystalline silicon, porous silicon, amorphous silicon, SiGe mixed crystal, SiGeC mixed crystal, GaAs, W, Ta, Ti, Hf, Co, Pt, Pd metal, alloy Alternatively, silicide, TaN, TiN or conductive nitride thereof can be used. Moreover, you may make these laminated structures. In addition, various modifications can be made without departing from the scope of the present invention. The dummy gate 10 is preferably formed of SiGe or SiGeC, which increases the etching selectivity with respect to the source / drain region 2 during the process of removing the dummy gate 10.
According to the MIS transistor and the manufacturing method thereof according to the seventh embodiment, the inclined surface is formed from the upper surface of the semiconductor layer serving as the source / drain region to the channel formation surface. The capacitance between the gate and the source and the capacitance between the gate and the drain can be kept smaller.
[0089]
Further, by making the shape of the gate electrode T-shaped, it is possible to reduce the resistance of the gate electrode, and to obtain a specific effect that the capacitance between the gate electrode and the source / drain electrodes can be kept small.
[0090]
As described above in detail, according to the MIS transistor and the manufacturing method thereof according to the present invention, the resistance of the impurity diffusion layer constituting the source / drain can be reduced, and at the same time, the parasitic capacitance of the gate can be reduced. Thus, the operation speed of the transistor can be significantly improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a configuration of a MIS transistor according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing steps (a) to (e) in the method for manufacturing a MIS transistor according to the first embodiment.
FIG. 3 is a cross-sectional view showing steps (a) to (e) of a method for manufacturing an MIS transistor according to a second embodiment of the invention.
FIG. 4 is a cross-sectional view showing a configuration of a MIS transistor according to a third embodiment of the present invention.
FIGS. 5A and 5B are cross-sectional views showing steps (a) to (e) in a MIS transistor manufacturing method according to a fourth embodiment of the invention. FIGS.
FIG. 6 is a cross-sectional view showing a configuration of a MIS transistor according to a fourth embodiment of the present invention.
FIG. 7 is a cross-sectional view showing the configuration of a MIS transistor according to a fifth embodiment of the invention.
FIGS. 8A and 8B are cross-sectional views showing steps (a) to (e) in the MIS transistor manufacturing method according to the fifth embodiment of the invention. FIGS.
FIG. 9 is a cross-sectional view showing a configuration of a MIS transistor according to a sixth embodiment of the present invention.
FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device according to a seventh embodiment of the present invention.
11 is a plan view showing a planar configuration of different cross sections (a) and (b) of the semiconductor device shown in FIG. 10;
FIG. 12 is a cross-sectional view showing manufacturing steps (a) and (b) of the semiconductor device of the seventh embodiment.
13 is a cross-sectional view showing manufacturing steps (d) and (e) subsequent to FIG. 12. FIG.
FIG. 14 is a cross-sectional view showing a configuration of a conventional MIS transistor.
[Explanation of symbols]
1 Semiconductor substrate
2 Source / drain regions
2A source area
2B drain region
2a First impurity diffusion layer
2b Second impurity diffusion region
4 groove
5 High dielectric gate insulating film
6 Gate electrode
7 Channel forming surface
9 Silicon oxide film
10 Polysilicon
101 Dummy gate electrode
102 Dummy gate insulating film
104 Semiconductor region
111 Insulating film
112 Insulating film
113 Gate insulation film
114 Gate electrode
115 Conductor layer

Claims (11)

A semiconductor substrate, and the source and drain regions formed on said substrate, a gate electrode provided in the information of the channel region between the source and drain regions, the MIS-type transistor having a
The upper surface of the source / drain region formed in the semiconductor substrate is located closer to the gate electrode than the channel formation surface in the semiconductor substrate, and the upper surface of the source / drain region is provided on the channel formation surface. It is located closer to the channel formation surface than the boundary surface between the insulating film and the gate electrode, and the gate insulating film has a dielectric constant higher than that of silicon oxide. MIS type transistor. With the bottom surface of the channel formation surface of the groove to form a groove on the upper surface of the semiconductor substrate, the position of the gate electrode thereon to form the gate insulating film via the protective film in the opening portion of the groove 2. The MIS transistor according to claim 1, wherein the upper surface of the source / drain region, the channel formation surface, and the boundary surface are respectively in a predetermined relationship on both sides of the channel formation surface. . The gate insulating layer formed on the channel formation surface via a protective film, with the upper surface of the source / drain region where the portion sandwiching the channel formation surface in the semiconductor substrate is stacked positioned on the gate electrode side with respect to the channel formation surface 2. The MIS transistor according to claim 1, wherein an upper surface of the source / drain region is located closer to the channel formation surface than the boundary surface between the film and the gate electrode. The upper surface of the source / drain region provided across the channel formation surface is raised above the channel formation surface and positioned on the gate electrode side, and the upper surface of the source / drain region is raised to raise the gate 2. The MIS type according to claim 1, comprising: a substantially flat surface at a level located on the electrode side; and an inclined surface inclined from the level of the flat surface to the level of the channel forming surface. Transistor.   5. The shape of a gate electrode surrounded by a gate insulating film provided on the upper side of the channel formation surface is a T-shaped shape with a lower side tapered through a stepped portion. MIS type transistor described in 1.   2. The shape of a gate electrode surrounded by a gate insulating film provided on the upper side of the channel formation surface is a T-shaped shape with a lower side tapered through a stepped portion. MIS type transistor described in 1.   7. The MIS transistor according to claim 1, wherein the gate insulating film includes a metal oxide film.   8. The MIS transistor according to claim 7, wherein the gate insulating film includes at least one of a titanium oxide film, an aluminum oxide film, and a tantalum oxide film.   9. The MIS transistor according to claim 8, wherein a dielectric constant of the gate oxide film is higher than a dielectric constant of the aluminum oxide film. A semiconductor substrate, and the source and drain regions formed on the substrate, a manufacturing method of the MIS transistor and a gate electrode provided above the channel region between the source and drain regions,
Selectively forming an oxide film on the semiconductor substrate;
Etching using the selectively formed oxide film as a mask to form a groove;
A step of removing the oxide film after polishing the upper surface of the oxide film and the polycrystalline semiconductor film after laminating a polycrystalline semiconductor layer in the groove;
A step of diffusing impurities on the surface of the semiconductor substrate using the polycrystalline semiconductor film as a mask to form a groove-like impurity diffusion region including a bottom side of the groove;
A gate insulating film made of a high dielectric film is formed in the groove portion of the groove-like impurity diffusion region so that the upper surface thereof is located on the side farther from the semiconductor substrate than the upper surface of the portion other than the groove portion of the impurity diffusion region. And a process of
Forming a gate electrode on the upper surface of the gate insulating film;
A method of manufacturing a MIS transistor , comprising: A semiconductor substrate, a method for producing the source and drain regions formed on said substrate, a gate electrode provided above the channel region between the source and drain regions, a MIS transistor having a
Selectively forming a polycrystalline semiconductor layer on the semiconductor substrate,
Using the selectively formed polycrystalline semiconductor layer as a mask, impurities are diffused on the surface of the semiconductor substrate to increase the impurity diffusion region higher than the channel formation surface formed on the masked semiconductor substrate surface Forming an impurity diffusion region containing :
Forming an oxide film on the surface side of the raised impurity diffusion region, polishing the surface of the oxide film using the polycrystalline semiconductor layer as a stopper, and then removing the polycrystalline semiconductor layer ;
A gate insulating film made of a high dielectric film is formed in a region surrounded by the raised impurity diffusion layer and the oxide film, so that the upper surface of the gate insulating film is higher than the boundary surface between the impurity diffusion region and the oxide film. Forming, and
Forming a gate electrode on the upper surface of the gate insulating film;
A method of manufacturing a MIS transistor, comprising:

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