JP3868623B2 - Output buffer circuit, semiconductor integrated circuit, and output buffer test method - Google Patents

Description

【００１４】
表１に示すように、モード切替信号Ｔ０，Ｔ１として、ともに’Ｌ’レベルの信号が入力された場合は、半導体集積回路１００は、出力バッファをテストするための出力電圧テストモードに切り替えられる。また、モード切替信号Ｔ０，Ｔ１として、’Ｌ’レベル，’Ｈ’レベルの信号が入力された場合は、入力バッファをテストするための入力電圧テストモードに切り替えられる。さらに、モード切替信号Ｔ０，Ｔ１として、’Ｈ’レベル，’Ｌ’レベルの信号が入力された場合は、いずれのモードでもない、いわゆるイリーガル状態のモードとなる。また、モード切替信号Ｔ０，Ｔ１として、ともに’Ｈ’レベルの信号が入力された場合は、通常モードに切り替えられる。
【００１５】
図２は、図１に示す接続切替回路の回路図である。
この図２には、図１に示す接続切替回路のうちのいずれか１つの接続切替回路の回路図が代表して示されている。
図２に示す接続切替回路６１は、第１のセレクタ６２＿１と第２のセレクタ６２＿２とから構成されている。これら第１，第２のセレクタ６２＿１，６２＿２には、モード切替信号Ｔ１が入力される。第１のセレクタ６２＿１の入力端子Ａと第２のセレクタ６２＿２の入力端子Ｂは互いに接続され、かつ上段側のＮＡＮＤゲートの出力に接続されている。また、第１のセレクタ６２＿１の入力端子Ｂは内部回路１０に接続されている。さらに、第１のセレクタ６２＿１の出力端子Ｘは、その第１のセレクタ６２＿１を含む接続切替回路６１に対応する出力バッファの入力に接続されている。
【００１６】
一方、第２のセレクタ６２＿２の入力端子Ａは電源Ｖｄｄに接続され、出力端子Ｘは、その第２のセレクタ６２＿２を含む接続切替回路６１に対応するＮＡＮＤゲートの入力に接続されている。
図３は、図２に示す接続切替回路を構成するセレクタを示す図である。
この図３には、図２に示すセレクタのうちのいずれか１つのセレクタの回路図が示されている。
【００１７】
図３に示すセレクタ６２に、モード切替信号Ｔ１として’Ｌ’レベルの信号が入力されると、その’Ｌ’レベルの信号がインバータ６２ｃで反転され、これによりトランスミッションゲート６２ａ，６２ｂがオン状態、オフ状態になり、入力端子Ａに入力されている信号が出力端子Ｘから出力される。一方、モード切替信号Ｔ１として’Ｈ’レベルの信号が入力されると、トランスミッションゲート６２ａ，６２ｂがオフ状態，オン状態になり、入力端子Ｂに入力されている信号が出力端子Ｘから出力される。
【００１８】
図４は、図２に示す接続切替回路の、モード切替信号Ｔ１により切り替えられた２つのスイッチ状態を示す図である。
図４（ａ）には、接続切替回路６１にモード切替信号Ｔ１として’Ｌ’レベルの信号が入力され、これにより接続切替回路６１が、本発明にいう第１のモードに切り替えられた状態が示されており、この状態で出力バッファのテストが行なわれる。一方、図４（ｂ）には、接続切替回路６１にモード切替信号Ｔ１として’Ｈ’レベルの信号が入力され、これにより接続切替回路６１が、本発明にいう第２のモードに切り替えられた状態が示されており、この状態で入力バッファのテストが行なわれる。
【００１９】
以下、図１，図４を参照して、本実施形態の半導体集積回路１００に備えられた出力バッファ４２＿１，…，４２＿ｎ，４３のテストについて説明する。
図１に示す半導体集積回路１００には、モード切替信号Ｔ０，Ｔ１として、ともに’Ｌ’レベルの信号が入力される。また、トライステート構成が採用された出力バッファ４２＿１，…，４２＿ｎは、図示しない制御信号により通常の出力バッファ状態に切り替えられる。
【００２０】
セレクタ７０には、’Ｌ’レベルのモード切替信号Ｔ０が入力されるため、このセレクタ７０には、内部回路１０からの信号が遮断され、ＮＡＮＤツリー５０を構成する最下段のＮＡＮＤゲート５１＿ｎからの信号が入力される。
また、各接続切替回路６１＿１，…，６１＿ｎには、’Ｌ’レベルのモード切替信号Ｔ１が入力されるため、各接続切替回路６１＿１，…，６１＿ｎは、図４（ａ）に示すスイッチ状態に切り替えられる。従って、各接続切替回路６１＿１，…，６１＿ｎには、内部回路１０からの信号が遮断され、各ＮＡＮＤゲート５１＿０，ＮＡＮＤゲート５１＿１，…，ＮＡＮＤゲート５１＿の１つ上段のＮＡＮＤゲート（図示せず）からの信号がそれぞれ入力される。
【００２１】
ここで、先ず、第１の端子２１に’Ｈ’レベルの信号を入力する。この’Ｈ’レベルの信号は、入力バッファ３１を経由してＮＡＮＤゲート５１＿０の一方に入力される。ＮＡＮＤゲート５１＿０の他方には電源Ｖｄｄが入力されているため、この’Ｈ’レベルの信号はＮＡＮＤゲート５１＿０で反転されて’Ｌ’レベルの信号となり、さらに接続切替回路６１＿１，出力バッファ４２＿１を経由して第２の端子２２＿１から’Ｌ’レベルの信号が出力されるとともに入力バッファ３２＿１に入力される。入力バッファ３２＿１に入力された’Ｌ’レベルの信号は、次段のＮＡＮＤゲート５１＿１の一方に入力される。ＮＡＮＤゲート５１＿１の他方には電源Ｖｄｄが入力されているが（図４（ａ）参照）、ＮＡＮＤゲート５１＿１の一方に’Ｌ’レベルの信号が入力されるため、ＮＡＮＤゲート５１＿１から’Ｈ’レベルの信号が出力され、さらにそのＮＡＮＤゲート５１＿１の１つ下段の、図示しないＮＡＮＤゲートに対応する接続切替回路，出力バッファを経由して、その出力バッファに接続された第２の端子から’Ｈ’レベルの信号が出力される。このようにして、第２の端子２２＿１，…，２２＿ｎから、’Ｌ’レベル，’Ｈ’レベル，…，’Ｌ’レベル，’Ｈ’レベルというように、交互にレベルが異なる信号が出力される。ここで、ｎが偶数であると仮定すると、第２の端子２２＿ｎからは’Ｈ’レベルの信号が出力され、その’Ｈ’レベルの信号は入力バッファ３２＿ｎを経由して最下段のＮＡＮＤゲート５１＿ｎに入力され、このＮＡＮＤゲート５１＿ｎで反転されて’Ｌ’レベルの信号が出力される。この’Ｌ’レベルの信号は、セレクタ７０，出力バッファ４３を経由して第３の端子２３に入力され、その第３の端子２３から’Ｌ’レベルの信号が出力される。
【００２２】
この状態で、第２の端子２２＿１，…，２２＿ｎ，第３の端子２３に規定の負荷を与え、これら第２の端子２２＿１，…，２２＿ｎ，第３の端子２３から出力されている信号の電圧レベルが、規定された電圧範囲内にあるか否かをチェックする。
次に、第１の端子２１に’Ｌ’レベルの信号を入力する。すると、第２の端子２２＿１，…，２２＿ｎ，第３の端子から’Ｈ’レベル，’Ｌ’レベル，…，’Ｌ’レベル，’Ｈ’レベルの、前述した、第１の端子２１に’Ｈ’レベルの信号を入力した場合とは逆の組み合わせの信号が出力される。これら信号の電圧レベルが規定された電圧範囲内にあるか否かを、規定の負荷を与えてチェックする。このようにして、全ての出力バッファ４２＿１，…，４２＿ｎ，４３のテストが行なわれる。
【００２３】
本実施形態の半導体集積回路１００では、出力バッファのテストにあたり、上述したように第１の端子２１に’Ｈ’レベルの信号と’Ｌ’レベルの信号を各１回づつ入力するだけで、内部回路１０の構成とは無関係に全ての出力バッファ４２＿１，…，４２＿ｎ，４３から’Ｌ’レベル，’Ｈ’レベル，…，’Ｌ’レベルの組み合わせの信号と、この組み合わせの信号とは逆の、’Ｈ’レベル，’Ｌ’レベル，…，’Ｈ’レベルの組み合わせの信号とを瞬時に得ることができる。従って、全ての出力バッファ４２＿１，…，４２＿ｎ，４３のテストをわずか２つの’Ｌ’レベル，’Ｈ’レベルのパターンで実施することとなり、従来の、内部回路に種々の組み合わせのテストパターンを印加してテストする場合と比較し、複雑なテストパターンを作成する必要がなくテストの準備段階における手間が削減されるとともにテストタイムも削減される。
【００２４】
次に、入力バッファ３１，３２＿１，…，３２＿ｎのテストについて説明する。半導体集積回路１００には、モード切替信号Ｔ０，Ｔ１として、’Ｌ’レベル，’Ｈ’レベルの信号が入力される。これにより、各接続切替回路６１＿１，…，６１＿ｎは、図４（ｂ）に示すスイッチ状態に切り替えられる。また、出力バッファ４２＿１，…，４２＿ｎは、図示しない信号によりハイインピーダンス状態に切り替えられる。
【００２５】
ここで、先ず、第１の端子２１に、規定された’Ｈ’レベルの電圧のうち最も低いレベルの電圧を入力する。また、第２の端子２２＿１，…，２２＿ｎには通常の’Ｈ’レベルの電圧を入力する。入力バッファ３１が正常な場合は、その入力バッファ３１から’Ｈ’レベルの信号が出力される。この’Ｈ’レベルの信号はＮＡＮＤゲート５１＿０で反転されて’Ｌ’レベルの信号となり、さらに接続切替回路６１＿１を経由してＮＡＮＤゲート５１＿１の一方に入力される。ＮＡＮＤゲート５１＿１の他方には’Ｈ’レベルの信号が入力されているが、ＮＡＮＤゲート５１＿１の一方には’Ｌ’レベルの信号が入力されるため、ＮＡＮＤゲート５１＿１から’Ｈ’レベルの信号が出力される。このようにして、ＮＡＮＤツリー５０を構成するＮＡＮＤゲート５１＿０，５１＿１，…，５１＿ｎから、順次、’Ｌ’レベル，’Ｈ’レベル，…，’Ｌ’レベルの信号が出力される。前述したように、ここではｎは偶数であると仮定しており、その場合最下段のＮＡＮＤゲート５１＿ｎからは’Ｌ’レベルの信号が出力される。この’Ｌ’レベルの信号は、セレクタ７０，出力バッファ４３を経由し、第３の端子２３から’Ｌ’レベルの信号として出力され、入力バッファ３１の、’Ｈ’レベル側の電圧テストは’良’と判定される。
【００２６】
一方、入力バッファ３１から’Ｌ’レベルの信号が出力された場合は、第３の端子２３から’Ｈ’レベルの信号が出力され、この入力バッファ３１の、’Ｈ’レベル側の電圧テストは’否’と判定される。
次に、入力バッファ３１の、’Ｌ’レベル側の電圧テストが行なわれる。第２の端子２２＿１，…，２２＿ｎに入力されている’Ｈ’レベルの電圧を保持したまま、第１の端子２１のみ、規定された’Ｌ’レベルの電圧のうち最も高いレベルの電圧を入力して、第３の端子２３をチェックする。第３の端子２３から’Ｈ’レベルの信号が出力された場合は’良’と判定され、第３の端子２３から’Ｌ’レベルの信号が出力された場合は’否’と判定される。
【００２７】
次に、入力バッファ３２＿１のテストが行なわれる。第１の端子２１に’Ｌ’レベル、第２の端子２２＿１を除く全ての第２の端子に’Ｈ’レベルの電圧を入力し、第２の端子２２＿１のみ、規定された’Ｈ’レベルの電圧のうち最も低いレベルの電圧を入力して、入力バッファ３２＿１の、’Ｈ’レベル側のテストを行ない、さらに、規定された’Ｌ’レベルの電圧のうち最も高いレベルの電圧を入力して、入力バッファ３２＿１の、’Ｌ’レベル側のテストを行なう。以下、同様にして、入力バッファ３２＿ｎまで行なう。このようにして、全ての入力バッファ３１，３２＿１，…，３２＿ｎのテストが行なわれる。また、第２の端子２２＿１，…，２２＿ｎは入力バッファ及び出力バッファを同時に備える双方向ピンとして説明したが、入力バッファ３２＿１，…，３２＿ｎのない出力専用ピンの場合でも同様に出力バッファの出力電圧テストが行なえるのはいうまでもない。
【００２８】
【発明の効果】
以上説明したように、本発明による切替回路を付加することで入力バッファのみならず出力バッファのテストにおいても、その準備段階における手間が削減され、かつテストタイムの短縮化が図られる。
【図面の簡単な説明】
【図１】本発明の半導体集積回路の一実施形態の回路図である。
【図２】図１に示す接続切替回路の回路図である。
【図３】図２に示す接続切替回路を構成するセレクタを示す図である。
【図４】図２に示す接続切替回路の、モード切替信号Ｔ１により切り替えられた２つのスイッチ状態を示す図である。
【符号の説明】
１０ 内部回路
２０ 端子群
２１ 第１の端子
２２＿１，…，２２＿ｎ 第２の端子
２３ 第３の端子
３１，３２＿１，…，３２＿ｎ 入力バッファ
４２＿１，…，４２＿ｎ，４３ 出力バッファ
５０ ＮＡＮＤツリー
５１＿０，５１＿１，…，５１＿ｎ ＮＡＮＤゲート
６１，６１＿１，…，６１＿ｎ 接続切替回路
６２＿１，６２＿２，７０ セレクタ
６２ａ，６２ｂ トランスミッションゲート
６２ｃ インバータ
１００ 半導体集積回路[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an output buffer test circuit that facilitates testing.
[0002]
[Prior art]
The semiconductor integrated circuit that has completed the manufacturing process is tested with a dedicated device called an LSI tester. Among them, an output voltage level test (hereinafter simply referred to as a test) for checking the function of the output buffer is generally performed according to the following procedure.
First, pay attention to the output terminal connected to the output of the output buffer to be checked, and apply a test pattern from the LSI tester to the internal circuit via the input terminal so that the voltage of the output terminal becomes 'L' level. To do. Next, a load corresponding to the drive capability of the output buffer to be measured is applied from the LSI tester to the output buffer via the output terminal while maintaining the power supply and the input voltage. In this state, the comparator in the LSI tester checks whether the voltage of the output buffer is within the prescribed 'L' level voltage range via the output terminal. Similarly, it is checked by a comparator in the LSI tester whether or not the voltage of the output buffer is within a prescribed 'H' level voltage range. Such a check is performed by the number of output buffers provided in the semiconductor integrated circuit.
[0003]
[Problems to be solved by the invention]
As described above, the test of the output buffer is performed by applying a test pattern such that a signal of “L” level or “H” level is output from the output buffer to be measured to the internal circuit. Here, since the configuration of the internal circuit is different for each type of semiconductor integrated circuit, it is necessary to create a test pattern applied to the internal circuit each time. In general, the configuration of the internal circuit is complicated, so that various combinations and complicated test patterns are required to drive the internal circuit, and it takes a long time to create the test pattern. Further, since the output buffer is tested with such a test pattern, there is a problem that the test time becomes long. In recent years, as the degree of integration and the number of terminals of semiconductor integrated circuits have increased, the configuration of internal circuits has become more and more complicated. Therefore, it takes a longer time to create a test pattern, which is a preparation stage for output buffer testing. The test time is longer and the test cost is increased.
[0004]
SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide an output buffer test circuit in which the labor required in the preparation stage of the output buffer test is reduced and the test time is shortened.
[0005]
[Means for Solving the Problems]
A first output buffer test circuit according to the present invention for achieving the above object is provided in an output buffer circuit.
The output terminal of the output buffer circuit is connected to one input of the 2-input NAND together with the pad, and the output from the internal circuit is directly guided to the input terminal of the output buffer circuit, and the test internal terminal a is connected to the other input of the NAND. Or a circuit for switching whether the output from the internal circuit is OPEN and the new internal terminal a becomes an input of the output buffer and the other input of the NAND is fixed at the high level and the test internal terminal a It is characterized by comprising.
[0006]
A second output buffer test circuit according to the present invention that achieves the above object is an input / output buffer circuit comprising:
Whether the output terminal of the input buffer circuit is connected to one of the inputs of the 2-input NAND, and the output from the internal circuit is directly guided to the input terminal of the output buffer circuit, and the test internal terminal a is the other input of the NAND Or a circuit for switching whether the output from the internal circuit is OPEN and the test internal terminal a becomes an input of the output buffer and the other input of the NAND is fixed to the high level, and the test internal terminal a. It is characterized by that.
[0007]
Here, the output of the input buffer and the output of the NAND having two inputs of the high level signal are connected to the test internal terminal of the buffer circuit of claim 1 or 2, and the NAND output of the buffer circuit is connected to another buffer. A semiconductor integrated circuit including an output buffer test circuit connected to the test terminal of the circuit and serially connected to the other buffer circuits is also preferable.
[0008]
Conventionally, the output buffer test is performed by applying a test pattern to the internal circuit. Therefore, it takes a long time to create a test pattern in the test preparation stage, and the test time is also long. ing. On the other hand, in recent years, an input buffer test may be performed without adding a NAND tree to an input buffer and applying a test pattern to an internal circuit.
[0009]
The present invention pays attention to this NAND tree when testing the output buffer, and a connection switching circuit is arranged between NAND gates constituting the NAND tree, and the connection switching circuit inputs the output buffer from the internal circuit to the output buffer. The output buffer is tested without applying a test pattern to the internal circuit by switching off the signal and outputting the signal from the output buffer via the NAND gate. For this reason, it is not necessary to create a complex test pattern for testing the output buffer, the labor required in the test preparation stage can be reduced, and the test time can be shortened.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described.
FIG. 1 is a circuit diagram of an embodiment of a semiconductor integrated circuit according to the present invention.
A semiconductor integrated circuit 100 shown in FIG. 1 includes an internal circuit 10 composed of a plurality of logic circuits. The semiconductor integrated circuit 100 includes a terminal group 20 including a first terminal 21, n second terminals 22 </ b> _ <b> 1,..., 22 </ b> _n, and a third terminal 23. The first terminal 21 is connected to the input of the input buffer 31. The second terminals 22_1,..., 22_n are connected to the input of the input buffer 32_1 and the output of the output buffer 42_1,..., The input of the input buffer 32_n and the output of the output buffer 42_n, respectively. The output buffers 42_1,..., And the output buffers 42_n adopt a tri-state buffer configuration, and are switched to a normal output buffer state or a high impedance state according to a signal (not shown). The third terminal 23 is connected to the output of the output buffer 43.
[0011]
Further, in the semiconductor integrated circuit 100, the uppermost NAND gate 51_0, the NAND tree 50 including n NAND gates 51_1,..., 51_n, and n corresponding to the n NAND gates 51_1,. , 61_n are provided. The connection switching circuits 61_1,..., 61_n are respectively disposed between the NAND gate 51_0 and the NAND gate 51_1, and between the NAND gate 51_n and the NAND gate 51_n which is one stage above the NAND gate 51_n. Further, the first input of the uppermost NAND gate 51_0 constituting the NAND tree 50 is connected to the power supply Vdd, and the second input is connected to the output of the input buffer 31. Further, the first inputs of the NAND gates 51_1,..., 51_n are connected to the connection switching circuits 61_1,..., 61_n, respectively, and the second inputs of the NAND gates 51_1,. Is connected to each output.
[0012]
Further, in the semiconductor integrated circuit 100, an output buffer 43 connected to the third terminal 23 by selecting one of the output of the lowermost NAND gate 51 — n constituting the NAND tree 50 and the output of the internal circuit 10 is selected. A selector 70 is also provided.
The semiconductor integrated circuit 100 configured as described above receives the mode switching signals T0 and T1 shown in Table 1.
[0013]
[Table 1]

[0014]
As shown in Table 1, when both 'L' level signals are input as the mode switching signals T0 and T1, the semiconductor integrated circuit 100 is switched to the output voltage test mode for testing the output buffer. Further, when a signal of “L” level or “H” level is input as the mode switching signals T0 and T1, the mode is switched to the input voltage test mode for testing the input buffer. Further, when a signal of “H” level or “L” level is input as the mode switching signals T0 and T1, the mode is a so-called illegal state which is not any mode. In addition, when both of the mode switching signals T0 and T1 are input with an “H” level signal, the mode is switched to the normal mode.
[0015]
FIG. 2 is a circuit diagram of the connection switching circuit shown in FIG.
FIG. 2 representatively shows a circuit diagram of any one of the connection switching circuits shown in FIG.
The connection switching circuit 61 shown in FIG. 2 includes a first selector 62_1 and a second selector 62_2. A mode switching signal T1 is input to the first and second selectors 62_1 and 62_2. The input terminal A of the first selector 62_1 and the input terminal B of the second selector 62_2 are connected to each other and to the output of the upper NAND gate. The input terminal B of the first selector 62_1 is connected to the internal circuit 10. Further, the output terminal X of the first selector 62_1 is connected to the input of the output buffer corresponding to the connection switching circuit 61 including the first selector 62_1.
[0016]
On the other hand, the input terminal A of the second selector 62_2 is connected to the power supply Vdd, and the output terminal X is connected to the input of the NAND gate corresponding to the connection switching circuit 61 including the second selector 62_2.
FIG. 3 is a diagram showing a selector constituting the connection switching circuit shown in FIG.
FIG. 3 shows a circuit diagram of any one of the selectors shown in FIG.
[0017]
When the 'L' level signal is input as the mode switching signal T1 to the selector 62 shown in FIG. 3, the 'L' level signal is inverted by the inverter 62c, whereby the transmission gates 62a and 62b are turned on. The signal is turned off, and the signal input to the input terminal A is output from the output terminal X. On the other hand, when an “H” level signal is input as the mode switching signal T1, the transmission gates 62a and 62b are turned off and on, and the signal input to the input terminal B is output from the output terminal X. .
[0018]
FIG. 4 is a diagram illustrating two switch states switched by the mode switching signal T1 in the connection switching circuit illustrated in FIG.
FIG. 4A shows a state in which an “L” level signal is input to the connection switching circuit 61 as the mode switching signal T1, and the connection switching circuit 61 is switched to the first mode according to the present invention. In this state, the output buffer is tested. On the other hand, in FIG. 4B, an “H” level signal is input to the connection switching circuit 61 as the mode switching signal T1, thereby switching the connection switching circuit 61 to the second mode according to the present invention. The state is shown and the input buffer is tested in this state.
[0019]
Hereinafter, a test of the output buffers 42_1,..., 42_n, 43 provided in the semiconductor integrated circuit 100 of this embodiment will be described with reference to FIGS.
The semiconductor integrated circuit 100 shown in FIG. 1 receives both “L” level signals as the mode switching signals T0 and T1. Further, the output buffers 42_1,..., 42_n adopting the tri-state configuration are switched to a normal output buffer state by a control signal (not shown).
[0020]
Since the selector 70 receives the 'L' level mode switching signal T 0, the signal from the internal circuit 10 is cut off to the selector 70, and the signal from the NAND gate 51 — n at the lowest stage constituting the NAND tree 50 is output. A signal is input.
Further, since the 'L' level mode switching signal T1 is input to each connection switching circuit 61_1, ..., 61_n, each connection switching circuit 61_1, ..., 61_n is in the switch state shown in Fig. 4A. Can be switched. Therefore, the signal from the internal circuit 10 is cut off in each connection switching circuit 61_1,..., 61_n, and the NAND gate (not shown) one stage above each NAND gate 51_0, NAND gate 51_1,. Are respectively input.
[0021]
Here, first, an “H” level signal is input to the first terminal 21. This 'H' level signal is input to one of the NAND gates 51_0 via the input buffer 31. Since the power supply Vdd is input to the other side of the NAND gate 51_0, this 'H' level signal is inverted by the NAND gate 51_0 to become an 'L' level signal, and further passes through the connection switching circuit 61_1 and the output buffer 42_1. Then, an “L” level signal is output from the second terminal 22_1 and input to the input buffer 32_1. The 'L' level signal input to the input buffer 32_1 is input to one of the NAND gates 51_1 at the next stage. The power supply Vdd is input to the other side of the NAND gate 51_1 (see FIG. 4A). However, since an “L” level signal is input to one of the NAND gates 51_1, the NAND gate 51_1 is set to the “H” level. Is further output from the second terminal connected to the output buffer via the connection switching circuit and output buffer corresponding to the NAND gate (not shown), one level below the NAND gate 51_1. A level signal is output. In this way, signals having different levels such as “L” level, “H” level,..., “L” level, and “H” level are output from the second terminals 22_1,. The Here, assuming that n is an even number, a signal of “H” level is output from the second terminal 22 — n, and the signal of “H” level passes through the input buffer 32 — n and the NAND gate 51 — n at the lowest stage. And is inverted by the NAND gate 51_n to output an 'L' level signal. The 'L' level signal is input to the third terminal 23 via the selector 70 and the output buffer 43, and the 'L' level signal is output from the third terminal 23.
[0022]
In this state, a prescribed load is applied to the second terminals 22_1,..., 22_n, and the third terminal 23, and the voltages of the signals output from the second terminals 22_1,. Check if the level is within the specified voltage range.
Next, an “L” level signal is input to the first terminal 21. Then, the second terminal 22_1,..., 22_n and the third terminal are connected to the above-described first terminal 21 of “H” level, “L” level,..., “L” level, “H” level. A signal having a combination opposite to that in the case of inputting an H ′ level signal is output. Whether or not the voltage levels of these signals are within a specified voltage range is checked by applying a specified load. In this way, all the output buffers 42_1,..., 42_n, 43 are tested.
[0023]
In the semiconductor integrated circuit 100 according to the present embodiment, when the output buffer is tested, as described above, the “H” level signal and the “L” level signal are input to the first terminal 21 once each time. Regardless of the configuration of the circuit 10, all the output buffers 42_1,..., 42_n, 43 receive a combination of signals of the “L” level, “H” level,. , “H” level, “L” level,..., “H” level combination signals can be obtained instantaneously. Therefore, all the output buffers 42_1,..., 42_n, 43 are tested with only two 'L' level and 'H' level patterns, and various combinations of test patterns are applied to the conventional internal circuit. Compared with the case of testing, it is not necessary to create a complicated test pattern, so that labor in the test preparation stage is reduced and test time is also reduced.
[0024]
Next, the test of the input buffers 31, 32_1, ..., 32_n will be described. The semiconductor integrated circuit 100 receives “L” level and “H” level signals as the mode switching signals T0 and T1. Thereby, each connection switching circuit 61_1, ..., 61_n is switched to the switch state shown in FIG.4 (b). Further, the output buffers 42_1,..., 42_n are switched to a high impedance state by a signal (not shown).
[0025]
Here, first, a voltage of the lowest level among the prescribed 'H' level voltages is input to the first terminal 21. Further, a normal 'H' level voltage is input to the second terminals 22_1, ..., 22_n. When the input buffer 31 is normal, an “H” level signal is output from the input buffer 31. This 'H' level signal is inverted by the NAND gate 51_0 to become an 'L' level signal, and further input to one of the NAND gates 51_1 via the connection switching circuit 61_1. A signal of “H” level is input to the other of the NAND gate 51_1, but since a signal of “L” level is input to one of the NAND gate 51_1, a signal of “H” level is input from the NAND gate 51_1. Is output. In this way, signals of “L” level, “H” level,..., “L” level are sequentially output from the NAND gates 51_0, 51_1,. As described above, it is assumed here that n is an even number. In this case, a signal of “L” level is output from the NAND gate 51_n at the lowest stage. This' L 'level signal is output as a' L 'level signal from the third terminal 23 via the selector 70 and the output buffer 43, and the voltage test on the' H 'level side of the input buffer 31 is' It is judged as 'good'.
[0026]
On the other hand, when an “L” level signal is output from the input buffer 31, an “H” level signal is output from the third terminal 23, and a voltage test on the “H” level side of the input buffer 31 is performed. It is determined as “No”.
Next, a voltage test of the input buffer 31 on the “L” level side is performed. Only the first terminal 21 is inputted with the highest level voltage among the prescribed 'L' level voltages while holding the 'H' level voltage inputted to the second terminals 22_1, ..., 22_n. Then, the third terminal 23 is checked. When a signal of “H” level is output from the third terminal 23, it is determined as “good”, and when a signal of “L” level is output from the third terminal 23, it is determined as “no”. .
[0027]
Next, the input buffer 32_1 is tested. The 'L' level is input to the first terminal 21 and the 'H' level voltage is input to all the second terminals except the second terminal 22_1. Only the second terminal 22_1 has the specified 'H' level. A voltage at the lowest level among the voltages is input to perform a test on the 'H' level side of the input buffer 32_1. Further, a voltage at the highest level among the specified 'L' level voltages is input. Then, the 'L' level side test of the input buffer 32_1 is performed. Thereafter, the processing is similarly performed up to the input buffer 32_n. In this way, all the input buffers 31, 32_1, ..., 32_n are tested. The second terminals 22_1,..., 22_n have been described as bidirectional pins having an input buffer and an output buffer at the same time. However, the output voltage of the output buffer is the same even in the case of an output dedicated pin without the input buffers 32_1,. Needless to say, you can test.
[0028]
【The invention's effect】
As described above, by adding the switching circuit according to the present invention, not only the input buffer but also the output buffer can be tested in the preparation stage and the test time can be shortened.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of an embodiment of a semiconductor integrated circuit according to the present invention.
FIG. 2 is a circuit diagram of the connection switching circuit shown in FIG. 1;
FIG. 3 is a diagram showing a selector that constitutes the connection switching circuit shown in FIG. 2;
4 is a diagram showing two switch states switched by a mode switching signal T1 in the connection switching circuit shown in FIG. 2;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Internal circuit 20 Terminal group 21 1st terminal 22_1, ..., 22_n 2nd terminal 23 3rd terminal 31, 32_1, ..., 32_n Input buffer 42_1, ..., 42_n, 43 Output buffer 50 NAND tree 51_0, 51_1 ..., 51_n NAND gates 61, 61_1, ..., 61_n connection switching circuit 62_1, 62_2, 70 selectors 62a, 62b transmission gate 62c inverter 100 semiconductor integrated circuit

Claims (6)

An output buffer circuit of a semiconductor integrated circuit ,
An output buffer whose output terminal is connected to the pad,
NAND having the output terminal of the output buffer connected to one input ;
A test internal terminal a;
Or internal terminal a for the test and guides the output from the internal circuit directly to the input terminal of the output buffer is the NAND of the other input, or internal terminal the test and the output from the internal circuit OPEN output buffer circuit and a connection switching circuit for a switches or inputs and becomes the other input of the NAND of the output buffer is fixed to the High level.   The input terminal further includes an input buffer connected to the pad, the output terminal of the output buffer is connected to one input terminal of the NAND, and the output terminal of the input buffer is connected to one input terminal of the NAND. 2. The output buffer circuit according to claim 1, wherein the output buffer circuit is connected.   A plurality of output buffer circuits according to claim 1 or 2,
  The NAND output of the uppermost output buffer circuit of the plurality of output buffer circuits is connected to the test internal terminal a of the output buffer circuit of the next stage, and the NAND output of the output buffer circuit of each stage is sequentially connected to the next stage. A semiconductor integrated circuit including an output buffer test circuit configured to be connected to a test internal terminal of the output buffer circuit.   An input buffer whose input terminal is connected to the pad;
  An input buffer circuit including a NAND having two inputs of the output of the input buffer and a high level signal;
  4. The semiconductor integrated circuit according to claim 3, wherein the output buffer test circuit further has a configuration in which the output of the NAND of the input buffer circuit is connected to the test internal terminal a of the uppermost output buffer circuit.   4. The connection switching circuit of each of the plurality of output buffer circuits in the output buffer test circuit according to claim 3, wherein the test internal terminal a is an input of the output buffer and the other input of the NAND is fixed to a high level. Switch to the side
  Each of the plurality of output buffer circuits in a state where an 'L' level signal is input to the test internal terminal a of the uppermost output buffer circuit and an 'H' level signal is input. Output buffer test method to check the output voltage level of the output buffer.   5. The connection switching circuit of each of the output buffer circuits in the output buffer test circuit according to claim 4, wherein the test internal terminal a is an input of the output buffer and the other input of the NAND is fixed to a high level. Switch to the side,
  A state in which an “L” level signal is input to the test input terminal “a” of the uppermost output buffer circuit by inputting an “H” level signal to the pad of the input buffer circuit; Each of the plurality of output buffer circuits in a state in which an “H” level signal is input to the test input terminal “a” of the uppermost output buffer circuit by inputting an “L” level signal to the pad. Output buffer test method to check the output voltage level of the output buffer.

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