JP3849110B2 - Metal wiring formation method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method suitable for forming a metal wiring having a high orientation with a material that is difficult to dry etch because there is no etching gas having good selectivity.
[0002]
In general, since semiconductor devices are still aimed at further miniaturization, various developments have been made so that the metal wiring used therefor can maintain conductivity that can be put into practical use even in a miniaturized state. However, since many metal materials having high conductivity even when miniaturized are difficult to process by dry etching or the like, the present invention discloses one means for solving this problem.
[0003]
[Prior art]
At present, there are two broadly known methods widely used for forming metal wirings in semiconductor devices.
[0004]
For example, after forming a metal film, a lithography technique and a dry etching technique are applied, the metal film is made into a wiring pattern and then filled with an interlayer insulating film, and an opening is formed in the interlayer insulating film as necessary. This is a method of pulling out the wiring (the former).
[0005]
The other is a method of forming wirings by forming wiring pattern openings in an interlayer insulating film and then embedding a wiring metal material in the openings (the latter).
[0006]
In the former, it is difficult to form wiring using a substance that is difficult to dry and etch, such as Cu, because there is no appropriate etching gas, and in the latter, wiring metal material is embedded in the opening. The crystal orientation is affected from both the bottom and side surfaces of the opening, and it is difficult to control the orientation of the metal wiring, which is important for extending the life of the wiring.
[0007]
[Problems to be solved by the invention]
The present invention is intended to provide means for easily forming a long-life metal wiring having a high orientation and made of a material that is difficult to dry-etch, such as Cu.
[0008]
[Means for Solving the Problems]
In the present invention, a substance B for controlling the orientation of the substance A which is an element constituting the main part of the metal wiring is formed at the bottom of the wiring opening formed in the insulating film made of the substance C, and the substance is formed thereon. Basically, A is laminated.
[0009]
FIG. 1 is a cutaway side view of a main part showing a metal wiring structure for explaining the principle in the present invention. In the figure, 1 is an insulating film made of substance C, 2 is a film made of substance B, 3 Respectively indicate metal wirings made of the substance A.
[0010]
When the metal wiring 3 made of the substance A is embedded in the opening formed in the insulating film 1, the bottom surface thereof is in contact with the coating 2 made of the substance B, and the side surface is in contact with the insulating film 1 made of the substance C.
[0011]
Here, since the substance B is selected to have a stronger influence on the orientation of the substance A than the substance C, it is possible to align the orientation of the metal wiring made of the substance A with the orientation based on the substance B. it can.
[0013]
From the above, in the metal wiring forming method according to the present invention,
(1)
An insulating film (for example, a barrier film 22 made of SiN) having a barrier property is formed on a base (for example, an interlayer insulating film 21 made of SiO ₂ ) that does not have a barrier property with respect to a metal substance (for example, Cu) that forms the main body of wiring And forming a first metal wiring (for example, a Cu film 23 having a wiring pattern) made of a metal material capable of affecting the orientation of the metal material forming the main body of the wiring on the insulating film. ) By controlling the orientation, and then, with respect to the metal material having an opening (for example, opening 25A) that exposes the first metal wiring with a slight margin around the first metal wiring. Forming an interlayer insulating film having no barrier property (for example, an interlayer insulating film 25 made of SiO ₂ ), and then covering the side wall of the interlayer insulating film exposed in the opening and forming the main part of the wiring metal A step of forming a film having a barrier property against the substance (for example, a side wall 26S made of SiN), and then filling the opening in which the film is formed with a metal substance that forms the main body of the wiring , or characterized in that it comprises a step of forming a second metal interconnection (e.g. line 27) in the same orientation as the orientation of the first metal wiring is controlled, or,
[0014]
(2)
In the above (1) , the first metal wiring and the second metal wiring are the same metal material (for example, Cu), or
[0015]
(3)
In (1) , the base and interlayer insulating film having no barrier property are SiO ₂ , and the insulating film and coating having a barrier property are SiN.
[0016]
By adopting the above-mentioned means, it becomes possible to easily form a metal wiring having high orientation when forming a buried wiring, and in particular, since dry etching cannot be performed, the conventional technique uses a wiring. Therefore, it is possible to realize a fine wiring structure having a high orientation using a metal that has been considered difficult, which can contribute to an improvement in operation speed and reliability of the semiconductor integrated circuit device.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
2 to 4 are side sectional views showing a principal part of the semiconductor device at the main points of the process for explaining the first embodiment of the present invention. The following description will be given with reference to these figures. . Here, a case where fine wiring is formed using Cu, which is excellent in conductivity but cannot be dry etched, is exemplified.
[0018]
Refer to FIG. 2 (A) 2- (1)
By applying a chemical vapor deposition (CVD) method, an interlayer insulation made of CF having a thickness of, for example, 600 [nm] having a barrier property against Cu on a substrate (not shown). A film 11 is formed.
[0019]
Refer to FIG. 2 (B) 2- (2)
By applying the sputtering method, a Cu film 12 having a thickness of, for example, 10 nm is formed on the interlayer insulating film 11.
[0020]
Refer to FIG. 2 (C) 2- (3)
By applying the spin coating method, a resist film 13 for forming an etching mask is formed on the Cu film 12.
[0021]
Refer to FIG. 3 (A) 3- (1)
By applying a lithography technique, the resist film 13 is patterned into a wiring pattern.
[0022]
Refer to FIG. 3B. 3- (2)
By applying a wet etching method in which an etchant is an aqueous sulfuric acid solution, the Cu film 12 is etched into a wiring pattern using the resist film 13 as a mask. The Cu film 12 of the wiring pattern acts as a film for controlling the orientation.
[0023]
Refer to FIG. 3C. 3- (3)
The resist film 13 on the Cu film 12 is removed by dipping in a resist stripping solution.
[0024]
Refer to FIG. 4 (A) 4- (1)
By applying the CVD method, an interlayer insulating film 14 made of CF having a thickness of, for example, 600 [nm] is formed on the entire surface.
[0025]
Refer to FIG. 4 (B) 4- (2)
By applying the lithography technique, the interlayer insulating film 14 is etched to form an opening 14A having a wiring pattern, and the Cu film 12 is exposed at the bottom.
[0026]
4- (3)
The resist film on the interlayer insulating film 14 is removed by dipping in a resist stripping solution.
[0027]
By applying a reference selective CVD (Chemical Vapor Deposition) method in FIG. 4C, Cu is embedded in the opening 14A to form the wiring 15.
[0028]
In the first embodiment described above, the Cu film 12 is used as a film for controlling the orientation of the wiring 15. However, as described above, Cu is a substance that is difficult to dry-etch. Therefore, here, the problem is solved by applying the wet etching method.
[0029]
By the way, since wet etching is isotropic etching, it is originally not suitable for microfabrication, but the Cu film 12 wet-etched in the first embodiment is as thin as 10 [nm]. Therefore, there is no problem in pattern accuracy.
[0030]
When forming a Cu film by a sputtering method, it is possible to realize a Cu film having various orientations by controlling the film forming conditions. However, the present invention is not limited to the sputtering method, and the orientation can be controlled. Other film forming methods such as ion plating may be used.
[0031]
When a Cu film is formed by the selective CVD method, the orientation of the Cu film is strongly influenced by the underlying film. In particular, in the case of homo-epitaxy, a film having the same orientation as the underlying film can be formed. Therefore, the wiring 15 made of Cu embedded in the opening 14A by the CVD method has high orientation.
[0032]
FIG. 5 to FIG. 8 are side sectional views showing the main part of the semiconductor device in the process steps for explaining the second embodiment of the present invention. The following description will be given with reference to these drawings. . Here, a case where SiO ₂ which is universal as an insulating film but has no barrier property to Cu must be used for the interlayer insulating film is illustrated.
[0033]
Refer to FIG. 5A. 5- (1)
By applying the CVD method, an interlayer insulating film 21 made of SiO ₂ having a thickness of, for example, 600 nm is formed on a substrate (not shown). As described above, SiO ₂ has no barrier property with respect to Cu.
[0034]
Refer to FIG. 5B. 5- (2)
By applying the CVD method, a barrier film 22 made of SiN having a thickness of, for example, 10 nm is formed on the interlayer insulating film 21.
[0035]
Refer to FIG. 5C. 5- (3)
By applying the sputtering method, a Cu film 23 having a thickness of, for example, 10 nm is formed on the barrier film 22 made of SiN.
[0036]
Refer to FIG. 6 (A) 6- (1)
By applying the spin coating method, a resist film 24 is formed on the Cu film 23 as an etching mask.
[0037]
Refer to FIG. 6 (B) 6- (2)
By applying a lithography technique, the resist film 24 is patterned into a wiring pattern.
[0038]
Refer to FIG. 6C. 6- (3)
By applying a wet etching method using an aqueous solution of sulfuric acid as an etchant, the Cu film 23 is etched into a wiring pattern using the resist film 24 as a mask. The Cu film 23 of the wiring pattern is a film for controlling the orientation.
[0039]
Refer to FIG. 7A. 7- (1)
The resist film 24 on the Cu film 23 is removed by dipping in a resist stripping solution.
[0040]
Refer to FIG. 7B. 7- (2)
By applying the CVD method, an interlayer insulating film 25 made of SiO ₂ having a thickness of, for example, 600 [nm] is formed on the entire surface.
[0041]
Refer to FIG. 7C. 7- (3)
By applying the lithography technique, the interlayer insulating film 25 is etched to form an opening 25A having a slightly larger wiring pattern than the pattern of the Cu film 23, and the Cu film 23 is exposed at the bottom thereof. .
[0042]
7- (4)
The resist film on the interlayer insulating film 25 is removed by dipping in a resist stripping solution.
[0043]
Refer to FIG. 8 (A) 8- (1)
By applying the blanket CVD method, the SiN film 26 having a thickness of, for example, 10 nm is formed on the entire surface including the inside of the opening 25A.
[0044]
Refer to FIG. 8B. 8- (2)
By applying the dry etching method, the SiN film 26 is anisotropically etched to form the side wall 26S on the side wall in the opening 25A.
[0045]
Refer to FIG. 8C. 8- (3)
By applying the selective CVD method, Cu is embedded in the opening 25A to form the wiring 27.
[0046]
In the second embodiment described above, SiO ₂ that is most widely used as an interlayer insulating film can be used, and SiN having a dielectric constant larger than that of SiO ₂ is a thin film of 10 nm. Therefore, an increase in capacitance between wirings does not become a problem.
[0047]
Normally, a conductor such as TiN is often used as a Cu diffusion barrier, but in the second embodiment, SiN, which is an insulating material, is used. Since the entire area can be filled with Cu, the electrical resistance per unit cross-sectional area of the wiring is reduced.
[0048]
The present invention is not limited to the above-described embodiments, and many other modifications can be realized. Here, it is easy to understand when FIG. 1 used for explaining the principle of the present invention is also viewed.
[0049]
For example, in each of the embodiments described above, the selective CVD method is applied when the metal wiring is formed by embedding the substance A, for example, Cu, in the opening. However, it is optional to replace this with a sputtering method or a plating method.
[0050]
Further, as the substance A, Cu alloy, Al, or Al alloy can be used in addition to Cu.
[0051]
Furthermore, TiN, Ta, TaN, WN, Ti, Al, etc. can be used in addition to Cu as the substance B that affects the orientation of the metal wiring made of the substance A.
[0052]
Furthermore, TiN can be used as the substance B that affects the orientation of the metal wiring made of the substance A, and a SiO ₂ compound can be used as the substance C constituting the insulating film.
[0053]
Furthermore, a conductor such as TiN, Ta, TaN, WN, Ti, or Al can be used for the coating (side wall) in the second embodiment.
[0054]
【The invention's effect】
In the metal wiring forming method according to the present invention, an insulating film having a barrier property is formed on a base that does not have a barrier property with respect to a metal substance forming the main body of the wiring, and the wiring is formed on the insulating film. A first metal wiring made of a metal material capable of affecting the orientation of the main metallic material is formed by controlling the orientation, and the first metal wiring is exposed with a slight margin around it. Forming an interlayer insulating film that has an opening that does not have a barrier property with respect to the metal material that forms the main body of the wiring, covers the side wall of the interlayer insulating film exposed in the opening, and forms the main body of the wiring Forming a film having a barrier property with respect to a metal material, filling the opening in which the film is formed with a metal material forming a main body of the wiring, and controlling the orientation of the first metal wiring it is group forming a second metal interconnect in the same orientation It has become.
[0055]
By adopting the above configuration, when forming the embedded wiring, it becomes possible to easily form a metal wiring having a high orientation, and in particular, since dry etching cannot be performed, the conventional technique uses the wiring. Therefore, it is possible to realize a fine wiring structure having a high orientation using a metal that has been considered difficult, which can contribute to an improvement in operation speed and reliability of the semiconductor integrated circuit device.
[Brief description of the drawings]
FIG. 1 is a cutaway side view of a main part showing a metal wiring structure for explaining the principle of the present invention.
FIG. 2 is a cutaway side view showing a main part of a semiconductor device in a process key point for explaining the first embodiment of the present invention;
FIG. 3 is a cutaway side view showing a main part of a semiconductor device at a process point for explaining the first embodiment of the present invention;
FIG. 4 is a cutaway side view showing a main part of a semiconductor device in a process key point for explaining the first embodiment in the present invention;
FIG. 5 is a cutaway side view showing a main part of a semiconductor device in a process key point for explaining a second embodiment in the present invention;
FIG. 6 is a cutaway side view showing a main part of a semiconductor device in a process key point for explaining a second embodiment of the present invention.
FIG. 7 is a cutaway side view showing a main part of a semiconductor device in a process key point for explaining a second embodiment in the present invention;
FIG. 8 is a cutaway side view showing a main part of a semiconductor device in a process key point for explaining a second embodiment in the present invention;
[Explanation of symbols]
11 Interlayer Insulating Film 12 Cu Film 13 Resist Film 14 Interlayer Insulating Film 14A Opening 15 Wiring

Claims (3)

A step of forming an insulating film having a barrier property on a base that does not have a barrier property with respect to a metal substance that is a main component of wiring;
Next, forming a first metal wiring made of a metal material capable of affecting the orientation of the metal material forming the main body of the wiring on the insulating film while controlling the orientation;
Next, forming an interlayer insulating film that has an opening that exposes the first metal wiring around the first metal wiring with a slight margin and has no barrier property with respect to the metal material that forms the main body of the wiring;
Next, a step of covering the interlayer insulating film sidewall exposed in the opening and forming a film having a barrier property with respect to a metal substance that forms the main body of the wiring;
Next, the opening in which the film is formed is filled with a metal material that forms the main body of the wiring, and the second metal wiring is formed in the same orientation as the controlled orientation of the first metal wiring. And a metal wiring forming method comprising the steps of : The first metal wiring and the second metal wiring are the same metal material
The metal wiring formation method of Claim 1 characterized by these . Claim 1 Symbol mounting method of forming a metal wiring underlayer and the interlayer insulating film no barrier resistance insulation film and film with have and barrier properties a SiO ₂ is characterized <br/> be SiN.

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