JP3843043B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a heterojunction field effect transistor using a SiGeC layer or a SiGe layer, and a method for manufacturing the same.
[0002]
[Prior art]
In recent years, high integration of semiconductor devices is progressing. However, in the miniaturization region where the gate length is less than 0.1 μm, the miniaturization of the MOS transistor is also affected by the short channel effect and the increase of the resistance component. As a result, it is expected that the current performance cannot be expected such as saturation of the current driving capability. In particular, in order to increase the driving power of a fine MOS transistor, it is important to improve the carrier mobility of the channel and to reduce the resistance of the contact between the source and drain electrodes.
[0003]
Therefore, instead of a complementary semiconductor device (CMOS device) using Si of a single composition formed on a silicon substrate, a heterostructure CMOS device (Heterostructure CMOS: hereinafter) based on Si / SiGe (group IV mixed crystal) (Abbreviated as HCMOS device). This utilizes not the Si / Si02 interface as a channel but the interface of a heterojunction of two kinds of semiconductors having different band gaps. It is expected that a higher-speed device can be realized by using a Si / SiGe system that gives higher carrier mobility than Si. In this Si / SiGe system, an epitaxial growth layer having a desired strain amount and band gap value can be formed on a Si substrate by controlling the composition. IBM's Ismail is conducting basic experiments for improving characteristics with Si / SiGe HCMOS devices (K. Ismail, "Si / SiGe High Speed Field-Effect Transistors", IEDM Tech. Dig. 1995, p509). And MA Armstrong et al, "Design of Si / SiGe Heterojunction Complementary Metal-Oxide-Semiconductor Transistors" IEDM Tech. Dig. 1995, p761.).
[0004]
FIG. 15 is a cross-sectional view showing an example of this HCMOS device. As shown in the figure, a field effect transistor including a source / drain region 109, a gate insulating film 107, and a gate electrode 110 thereon is provided on a part of the Si substrate 101. In a so-called channel region between the source region and the drain region below the gate electrode 110, the SiGe buffer layer 102, the δ-doped layer 115, the spacer layer 103, the i-Si layer 104, and the i-SiGe layer 105 are formed. Then, an i-Si layer 106 is formed. In these regions, the SiGe buffer layer 102 applies tensile strain to the i-Si layer 104 in order to form the n-channel layer 112 between the i-Si layer 104 and the i-SiGe layer 105. . In the SiGe buffer layer 102, the composition ratio is changed stepwise so that the Ge composition ratio is 0% immediately above the Si substrate 101 and the Ge composition ratio is 30% at the top.
[0005]
Here, when a negative bias is applied, an n-channel layer 112 is formed in the heterointerface with the lower SiGe buffer layer 102 in the i-Si layer 104. The δ-doped layer 115 supplies electrons that are carriers to the n-channel layer 112 formed above. The spacer layer 103 spatially separates the ions of the δ-doped layer 115 formed below and the upper n-channel layer 112, and prevents the mobility from being lowered due to carrier ion scattering.
[0006]
When a positive bias is applied, the p-channel layer 111 is formed in the heterointerface between the i-SiGe layer 105 and the upper i-Si layer 106. The gate insulating film 107 is for insulating the gate electrode 110 and the p-channel layer 111.
[0007]
As described above, a hetero field effect transistor is characterized in that a channel is formed at a hetero interface between two types of semiconductor layers having different band gaps. Therefore, at least two types of semiconductor layers having different band gaps inevitably exist for channel formation. In addition, in order to form a channel for electrons or holes to move at high speed in the semiconductor layer, it is necessary to have a conduction band or valence band discontinuity at the heterointerface. In the Si / SiGe system described above, a hole channel is formed for the holes because the SiGe layer 105 has discontinuities in the valence band with respect to the i-Si layer 106 (on the left side of FIG. 15). Part reference). However, since there is almost no discontinuity in the conduction band, a tensile strain is applied to the i-Si layer 104 to form a channel for electrons, so that the conduction band is formed at the heterointerface with the i-SiGe layer 105. (See the right part of FIG. 15).
[0008]
From the simulation results, it is expected that the HCMOS device having such a structure can realize twice the high-speed operation with the same processing size and half the power consumption as compared with the conventional CMOS device using the Si / Si02 channel. ing. That is, a semiconductor element in which a heterointerface is formed by combining a Si semiconductor and a SiGe mixed crystal, and a high mobility channel is formed. The high-speed operation of an element using a heterojunction and the large-scale integration of a MOS device are achieved. It has attracted a great deal of attention as a compatible element.
[0009]
[Problems to be solved by the invention]
However, the hetero devices using the group IV mixed crystal such as SiGe as described above are greatly expected as a method of overcoming the performance limit of the conventional CMOS device, but the hetero device using the group IV mixed crystal represented by SiGe is used. Field-effect transistors have been delayed in research and development compared to heterobipolar transistors, which are hetero devices using the same SiGe mixed crystal, due to the difficulty of their production, and the structure and method of production that can still fully demonstrate their expected performance. It cannot be said that the examination has been sufficiently conducted. Also, among the hetero field effect transistors, in the case of a so-called hetero MOS structure having an insulating film between the gate electrode and the semiconductor layer as described above, a stable and good insulating film cannot be formed in the SiGe layer. An oxide film made of SiO2 is used as the film. Therefore, it is necessary that the Si layer is always directly under the gate insulating film, but Si has a feature that the band gap is always larger than that of SiGe.
[0010]
Therefore, the structure of the conventional HCMOS device has the following problems.
[0011]
First, as described above, in order to form an electron channel on the Si substrate 101, tensile strain is applied to the i-Si layer 104 to form a band discontinuity at the Si / SiGe heterointerface. . However, since the lattice constant is changed, dislocation is introduced by lattice relaxation.
[0012]
FIG. 16 is a sectional view showing the SiGe buffer layer 102 and the i-Si layer 104 thereon. Since the i-Si layer 104 has a smaller lattice constant than the SiGe buffer layer 102, tensile strain is accumulated at the stage of crystal growth. When the accumulation of strain increases, dislocations enter the i-Si layer 104 as shown in FIG. Thus, dislocations and defects are unavoidable due to lattice mismatch strain between the i-Si layer 104 and the SiGe buffer layer 102. Therefore, regardless of the initial characteristics of the element using this crystal, it is considered that the influence of characteristic deterioration due to the growth of dislocations appears from the viewpoint of reliability and lifetime.
[0013]
Further, the SiGe buffer layer 102 made of SiGe having a lattice constant larger than that of Si is stacked on the Si substrate 101, and tensile strain is accumulated in the i-Si layer 104 grown thereon, but the film of the SiGe buffer layer 102 As the thickness is increased, the lattice constant of the SiGe buffer layer 102 exceeds the critical film thickness that changes from the lattice constant of Si to the original lattice constant of SiGe. Etc. are introduced.
[0014]
Although these defects may have little influence on the initial characteristics of the device, they may cause a serious problem from the viewpoint of long-term reliability and lifetime. In other words, the growth of defects due to current and the deterioration due to diffusion through the defects of metals and impurities may occur, leading to a decrease in reliability.
[0015]
A first object of the present invention is to utilize a heterojunction lattice-matched or substantially lattice-matched with a band discontinuity capable of forming a carrier accumulation layer as a structure in a channel region under the gate of an HCMOS device. Another object is to provide a highly reliable semiconductor device with high carrier mobility.
[0016]
Second, hetero-field effect devices using group IV mixed crystals represented by SiGe are effective technologies as element structures that overcome the performance limitations of conventional fine CMOS devices, but at the present time, channel mobility is improved. Compared with this research, the optimization of the contact between the source and drain electrodes is still insufficient, and it cannot be said that the structure is able to make full use of its high mobility. Although the above-mentioned hetero CMOS device technology by IBM has also been studied in detail for improving the mobility of the channel region, contact of the source / drain electrodes, which is another important factor for improving the performance of a fine transistor Little consideration has been given to lowering the resistance.
[0017]
That is, in the CMOS device structure using Si single crystal, various studies have been made on the structure of the contact region on the substrate side connected to the source / drain electrodes, but the optimum contact in a general CMOS device. It is necessary to examine whether the structure of the region and the formation method are the best in a hetero field effect device having a different element structure.
[0018]
A second object of the present invention is to provide a semiconductor device having a contact region capable of exhibiting a small contact resistance without impairing the excellent characteristics of a hetero field effect device, and a method for manufacturing the same.
[0019]
[Means for Solving the Problems]
A first semiconductor device of the present invention is a semiconductor device including a field effect transistor formed on a part of a semiconductor substrate and having a gate electrode, a source / drain region, and a channel region between the source / drain regions. In the channel region, an Si layer and Si formed in contact with the Si layer _1-xy Ge _x C _y Layers (0 ≦ x ≦ 1, 0 <y ≦ 1) are provided, and Si _1-xy Ge _x C _y A carrier storage layer is formed in a region close to the Si layer in the layer, and the Si _1-xy Ge _x C _y The composition ratio of each element of the layer is the above Si _1-xy Ge _x C _y The composition ratio is adjusted so that the layer and the Si layer lattice match.
[0020]
Thereby, Si whose composition ratio y of C is 0.01 to 0.03 _1-xy Ge _x C _y A band discontinuity necessary for forming a carrier accumulation layer for two-dimensionally confining carriers can be formed at the interface between the layer and the Si layer. And since this carrier storage layer functions as a channel, Si that gives larger carrier mobility than the Si layer _1-xy Ge _x C _y A field effect transistor having a high operation speed with the layer as a channel can be obtained. Moreover, Si _1-xy Ge _x C _y Since the lattice mismatch between the layer and the Si layer can be controlled to be eliminated or extremely small, the lattice strain can be adjusted to be 0 or almost not, and Si _1-xy Ge _x C _y It is possible to configure so that crystal defects do not enter the layer. Therefore, a highly reliable semiconductor device can be obtained. And there is no distortion caused by lattice mismatch _1-xy Ge _x C _y Since a channel is formed in the layer, a semiconductor device having extremely high reliability can be obtained.
[0021]
A second semiconductor device of the present invention is a semiconductor device including a field effect transistor formed on a part of a semiconductor substrate and having a gate electrode, a source / drain region, and a channel region between the source / drain regions. In the channel region, an Si layer and Si formed in contact with the Si layer _1-xy Ge _x C _y Layers (0 ≦ x ≦ 1, 0 <y ≦ 1) _1-xy Ge _x C _y A carrier storage layer is formed in a region close to the Si layer in the layer, and the Si _1-xy Ge _x C _y The layer has a lattice constant smaller than that of the Si layer and has a thickness that does not cause lattice relaxation.
[0022]
As a result, Si _1-xy Ge _x C _y Since tensile strain is applied to the layer, the amount of band discontinuity with the Si layer can be increased, and the carrier confinement efficiency is improved.
[0023]
A third semiconductor device of the present invention is a semiconductor device including a field effect transistor formed on a part of a semiconductor substrate and having a gate electrode, a source / drain region, and a channel region between the source / drain regions. In the channel region, an Si layer and Si formed in contact with the Si layer _1-xy Ge _x C _y Layers (0 ≦ x ≦ 1, 0 <y ≦ 1) _1-xy Ge _x C _y A carrier storage layer is formed in a region close to the Si layer in the layer, and the Si _1-xy Ge _x C _y The energy level between the lower end of the conduction band of the layer and the lower end of the conduction band of the Si layer is discontinuous.
[0024]
A fourth semiconductor device of the present invention is a semiconductor device including a field effect transistor formed on a part of a semiconductor substrate and having a gate electrode, a source / drain region, and a channel region between the source / drain regions. In the channel region, an Si layer and Si formed in contact with the Si layer _1-xy Ge _x C _y Layers (0 ≦ x ≦ 1, 0 <y ≦ 1) _1-xy Ge _x C _y A carrier storage layer is formed in a region close to the Si layer in the layer, and the carriers stored in the carrier storage layer are negative or positive carriers.
[0025]
A fifth semiconductor device of the present invention is a semiconductor device comprising a field effect transistor formed on a part of a semiconductor substrate and having a gate electrode, a source / drain region, and a channel region between the source / drain regions. In the channel region, an Si layer and Si formed in contact with the Si layer _1-xy Ge _x C _y Layers (0 ≦ x ≦ 1, 0 <y ≦ 1), and the Si in the Si layer is provided. _1-xy Ge _x C _y A carrier supply layer for supplying carriers to the storage layer is further formed in a region close to the layer.
[0026]
The sixth semiconductor device of the present invention is formed on a Si substrate having different compositions from each other. _1-xy Ge _x C _y A layer (0.ltoreq.x.ltoreq.1, 0 <y.ltoreq.1), a gate oxide film, and a gate electrode are provided, and charges confined at the heterointerface are controlled by a voltage applied from the gate electrode.
[0027]
Si _1-xy Ge _x C _y The Ge composition ratio x and the Si composition ratio y of the layer are set to a range in which the Si substrate is substantially lattice-matched. _1-xy Ge _x C _y By controlling the band gap energy of the layer, a discontinuity between the conduction band edge and the valence band edge can be formed to form an electron or hole channel.
[0028]
A seventh semiconductor device of the present invention is a semiconductor device including at least one field effect transistor formed on a semiconductor substrate, wherein the field effect transistor includes Si _1-xy Ge _x C _y A first semiconductor layer including layers (0 ≦ x ≦ 1, 0 <y ≦ 1), a second semiconductor layer made of a semiconductor having a band gap different from that of the first semiconductor layer, and the first semiconductor layer A channel region having a carrier accumulation layer formed in a region near the interface between the second semiconductor layers, a third semiconductor layer, and a fourth semiconductor composed of a semiconductor having a larger band gap than the third semiconductor layer. Source / drain regions having a semiconductor layer and a source / drain contact layer made of a low-resistance conductor film formed immediately above the third semiconductor layer.
[0029]
This makes it possible to reduce the contact resistance to the source / drain region in a field effect transistor that uses a heterojunction and has high carrier movement, that is, high operating speed.
[0030]
The first semiconductor layer and the third semiconductor layer are constituted by a common first semiconductor film, and the second semiconductor layer and the fourth semiconductor layer are constituted by a common second semiconductor film. Then, the second semiconductor film can be formed on the first semiconductor film.
[0031]
The method for manufacturing a semiconductor device according to the present invention includes Si _1-xy Ge _x C _y A first semiconductor layer including layers (0 ≦ x ≦ 1, 0 <y ≦ 1), a second semiconductor layer having a band gap different from that of the first semiconductor layer, and the first and second layers A method of manufacturing a semiconductor device having a carrier storage layer serving as a channel formed in a region near an interface between semiconductor layers and functioning as a field effect transistor, wherein a Si substrate is formed on a field effect transistor formation region of a semiconductor substrate. _1-xy Ge _x C _y First step of sequentially forming a third semiconductor layer including layers (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) and a fourth semiconductor layer having a larger band gap than the third semiconductor layer And a second step of depositing a conductor film above the fourth semiconductor layer and then patterning the conductor film to form a gate electrode; and the field effect transistor located on both sides of the gate electrode. Impurities are introduced into the formation region to a depth that reaches at least the carrier accumulation layer to form source / drain regions, and the fourth semiconductor layer in the source / drain regions is formed at least by the third step. A fourth step of removing by etching until the semiconductor layer is exposed, and a fifth step of forming a source / drain contact layer made of a low-resistance conductor film on the exposed surface of the third semiconductor layer; It is provided.
[0032]
By this method, a semiconductor device having the above structure can be easily formed.
[0033]
In the first step, the first and third semiconductor layers are simultaneously formed from a common first semiconductor film, and the second and fourth semiconductor layers are simultaneously formed from a common second semiconductor film. Can be done as follows.
[0034]
The fourth step is preferably performed under etching conditions having a high etching selectivity with respect to the third semiconductor layer and the fourth semiconductor layer.
[0035]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
The HCMOS device according to the first embodiment uses a SiGeC ternary mixed crystal system in which C is added to a SiGe / Si system, and the SiGeC layer and the Si layer are substantially lattice-matched, and a difference in band gap energy is obtained. The field effect transistor forms a band discontinuity at the hetero interface.
[0036]
FIG. 1 is a cross-sectional view showing the structure of the HCMOS device according to the first embodiment. As shown in the figure, an NMOS transistor and a PMOS transistor are formed on the silicon substrate 10. First, the structure of the NMOS transistor will be described.
[0037]
In the NMOS transistor, a p-well 11 (high-concentration p-type silicon layer) is formed on a Si substrate 10 and further has a δ-doped layer and a spacer layer doped with a group V element at a high concentration. The Si layer 13n and the SiGeC layer 14n (C composition ratio is 1%, Ge composition ratio is 8.2%) are sequentially formed. As will be described later, the composition ratio of each element in the SiGeC layer 14n is a value in which the SiGeC layer 14n and the Si layer 13n immediately below the lattice match.
[0038]
At the heterointerface between the SiGeC layer 14n and the Si layer 13n, as shown in the right part of FIG. 1, there is a band discontinuity portion of the conduction band Ec having a band offset value ΔEc. A carrier accumulation layer for confining electrons, which are negative carriers, as a two-dimensional electron gas (2DEG) is formed in the part. The carrier accumulation layer formed in the vicinity of the interface on the SiGeC layer 14n side becomes a channel through which electrons travel at high speed. In the SiGeC layer 14n, the electron mobility is higher than in the Si layer, and the operating speed of the NMOS transistor can be increased.
[0039]
Further, on this SiGeC layer 14n, an SiGe layer 15n (Ge composition ratio is 30%, Si composition ratio is 70%) and an Si layer 17n are sequentially formed, and further, a silicon oxide film is formed on the surface. A gate insulating film 19n is formed. Since the Si layer 17n exists under the gate insulating film 19n, the gate insulating film 19n having high crystallinity can be easily formed only by oxidizing the surface of the Si layer 17n. A gate electrode 18n is formed on the gate insulating film 19n, and a source / drain layer 16n is formed in the substrate located on both sides of the gate electrode 18n. The travel of electrons in the SiGeC layer 14n is controlled by a voltage applied to the gate electrode 18n. The source / drain layer 16n is formed to a depth reaching the p-well 11, but may be formed at least to the depth of the portion to be a channel formed in the SiGeC layer 14n.
[0040]
On the other hand, the PMOS transistor has almost the same configuration as the NMOS transistor described above. An n-well 12 (high-concentration n-type Si layer) is formed on the Si substrate 10, and an Si layer 13 p having a δ-doped layer doped with a V-group element at a high concentration, and an SiGeC layer 14p (Ge composition ratio is 8.2% and C composition ratio is 1%) are sequentially formed. Further, an SiGe layer 15p (Ge composition ratio is 30%, Si composition ratio is 70%) and an Si layer 17p are sequentially formed on the SiGeC layer 14p. In the case of a PMOS transistor, carriers are holes, and the channel through which the holes flow is formed on the SiGe layer 15p side of the interface between the SiGe layer 15p and the Si layer 17p. A band discontinuity portion of the valence band having a band offset value ΔEv exists at the heterointerface between the SiGe layer 15p and the Si layer 17p, and a carrier accumulation layer is formed at the discontinuity portion. Therefore, although holes move through the carrier accumulation layer channel formed at the interface on the SiGe layer 15p side, the mobility of holes is larger in the SiGe layer 15p than in the Si layer. Also grows.
[0041]
In the PMOS transistor, a gate insulating film 19p made of a silicon oxide film is formed on the Si layer 17p. A source / drain layer 16p is formed on both sides of the gate electrode 18p, and the movement of holes in the SiGe layer 15p is controlled by a voltage applied to the gate electrode 18p.
[0042]
Further, a trench isolation 20 is provided between the NMOS transistor and the PMOS transistor, in which a trench formed in the substrate is filled with a silicon oxide film. By this trench isolation 20, the NMOS transistor and the PMOS transistor are mutually connected. Electrically separated.
[0043]
The Si layers 13n and 13p, the SiGeC layers 14p and 14n, the SiGe layers 15n and 15p, and the Si layers 17n and 17p are simultaneously formed by crystal growth. And the dimension of each layer can be made into the following dimensions, for example. However, it is not necessarily limited to the following dimensions.
[0044]
The thickness of each Si layer 13n, 13p is, for example, about 0.6 μm, and preferably in the range of 0 to 1 μm. The thickness of the spacer layer is, for example, about 30 nm and is preferably in the range of 0 to 50 nm. The thickness of each SiGeC layer 14p, 14n is preferably 3 to 50 nm. Each SiGe layer 15n, 15p has a thickness of about 5 nm, preferably in the range of 3-5 nm. The thickness of each Si layer 17n, 17p is about 1 nm and is preferably in the range of 0.5 to 5 nm. The thickness of the gate insulating films 19n and 19p is, for example, about 5 nm.
[0045]
The gate length of the gate electrodes 18n and 18p is 0.25 μm, the gate width is 2.5 μm, the width of the source / drain regions is about 1.2 μm, and the contact area of the source / drain electrodes 21n and 21p is 0. It is about 5 μm × 0.6 μm. The doping concentration of each well 13n, 13p is 1 × 10 ¹⁷ ~ 1x10 ¹⁸ cm ^-3 The doping concentration of the δ-doped layer is 1 × 10 ¹⁸ ~ 1x10 ²⁰ cm ^-3 Degree.
[0046]
The feature of the HCMOS device (Heterostructure CMOS device) in this embodiment is that a SiGeC layer is used. The SiGeC layer can change the band gap amount and the lattice mismatch ratio with respect to silicon by adjusting the composition ratio of each of Si, Ge, and C. Here, the relationship between the composition ratio of Si, Ge, and C, the strain of each layer, and the band offset amount in this embodiment will be described in detail.
[0047]
FIG. 2 shows the lattice mismatch ratio (%) between the SiGeC layer and the Si layer (mis) when the horizontal axis represents the C (carbon) composition ratio (%) and the vertical axis represents the Ge composition ratio (%). (Fit) changes. A line with zero misfit indicates that the lattice constants of the SiGeC layer and the Si layer are equal. The lattice constant of Ge (germanium) single crystal is larger than that of Si single crystal, and the lattice constant of C (carbon) single crystal is smaller than that of Si single crystal. Therefore, the composition ratio of Ge and C is adjusted. By doing so, the lattice constant of the SiGeC layer 14n and the lattice constant of the Si layer 13n can be matched.
[0048]
FIG. 3 is a characteristic diagram showing the relationship between the lattice matching with respect to the composition ratio of the three elements Si, Ge, and C. The three vertices in the figure are points where the composition ratios of Si, Ge, and C are 100% (composition ratio is 1), respectively. It shows how the matching rate changes. The hatched area in the figure shows the area of the composition ratio that gives tensile strain to the SiGeC layer, and the solid line in the figure shows each element for zero lattice mismatch between the SiGeC layer and the Si layer, that is, for both to lattice match The composition ratio conditions are shown. Since the lattice constant of Ge is 4.2% larger than the lattice constant of Si and the lattice constant of C is 34.3% smaller than the lattice constant of Si, the composition ratio of Ge is 8.2 times the composition ratio of C. By increasing the size, the lattice constant of the SiGeC layer can be matched with the lattice constant of the Si layer.
[0049]
In the SiGeC layer 14n in this embodiment, the Ge composition ratio is 8.2% (x = 0.082), and the C composition ratio is 1% (y = 0.01). It can be seen that the lattice mismatch with the Si substrate is 0, and the SiGeC layer 14n and the lower Si layer 13n have the same lattice constant.
[0050]
Next, FIG. 4 shows the band offset value ΔEc of the conduction band at the interface between the SiGeC layer and the Si layer and the valence band when the horizontal axis represents the C composition ratio and the vertical axis represents the energy level. It shows how the band offset value ΔEv changes. However, the black circle represents the band offset value ΔEv of the valence band, and the white circle represents the band offset value ΔEc of the conduction band. The origin of energy is the energy value at the lower end of the Si conduction band for the conduction band, and the energy value at the upper end of the Si valence band for the valence band. Further, the solid line in the figure corresponds to the unstrained system, and the dotted line in the figure corresponds to the tensile strain system.
[0051]
As shown in FIG. 4, the band offset values of the conduction band and the valence band at the interface between the SiGeC layer (C composition ratio of 0.01) and the Si layer of this embodiment are 300 meV and 0 meV, respectively. It can be seen that there is no band discontinuity in the valence band at the interface between Si and Si, and a band discontinuity is formed only in the conduction band. Further, since the composition ratio of C in the SiGeC layer 14n of this embodiment is 0.01, the SiGeC layer 14n and the Si layer 13n are lattice-matched. Therefore, it is possible to prevent the occurrence of defects such as dislocations due to lattice mismatch with the lower Si layer 13n in the SiGeC layer 14n in which the channel in which the two-dimensional electron gas travels is formed.
[0052]
On the other hand, since there is no band discontinuity in the valence band at the interface between the SiGeC layer 14n and the Si layer 13n in the present embodiment, holes cannot be confined in the SiGeC layer 14n. Therefore, in the case of a PMOS transistor using holes as carriers, a heterojunction between the SiGe layer 15p and the Si layer 17p is used. The lattice constant of the SiGe single crystal is larger than the lattice constant of the Si single crystal, and the SiGe layer 15p is positioned on the SiGeC layer 14p lattice-matched with the Si layer 13p. The band offset value in the valence band is large. Also in this case, when an electric field is applied from the gate, holes are two-dimensionally confined (2DHG) by the band inclination, thereby forming a carrier accumulation layer. Therefore, the carrier accumulation layer in the SiGe layer 15p serves as a channel for holes to travel at high speed.
[0053]
As described above, according to the structure of this embodiment, in the NMOS transistor, the band offset value of the conduction band is stored in the two-dimensional electron gas by adjusting the composition ratio of each element Si, Ge, C in the SiGeC layer 14n. Therefore, lattice matching between the SiGeC layer and the Si layer can be achieved while maintaining a sufficient value for the above. Therefore, it is possible to achieve high reliability by reducing the defect density while realizing an increase in operation speed using the high carrier mobility of the two-dimensional electron gas in the SiGeC layer. Further, since there is no band discontinuity in the valence band at the interface between the SiGeC layer 14n and the Si layer 13n, holes cannot be confined in the SiGeC layer 14n, but the heterogeneity between the SiGe layer 15p and the Si layer 17p is not possible. By using the junction, a channel of a PMOS transistor using holes as carriers can be formed, and high-speed operation can be realized.
[0054]
A high-performance HCMOS device can be realized by integrating a high-speed NMOS transistor and a high-speed PMOS transistor by forming band discontinuities in the valence band using SiGe.
[0055]
In this embodiment, the Ge composition ratio is 8.2% and the C composition ratio is 1%. From FIG. 4, the band discontinuity, that is, the band offset value ΔEv is maximized in the lattice matching system. In order to achieve this, it is understood that the composition ratio of C should be increased. By providing such a large band offset value ΔEv, the two-dimensional electron gas (2DEG) confined in the heterointerface does not get over the heterointerface even if the electron concentration increases, and can travel stably. Can do. In particular, it is preferable to adjust the composition ratio of C to a range of 0.01 to 0.03. Within this range, a band offset value ΔEv (= −0.2 to −0.6) appropriate for forming a carrier accumulation layer for confining the two-dimensional electron gas in both the unstrained system and the tensile strain system. V) can be obtained.
[0056]
In this embodiment, the Ge composition ratio in the SiGe layer 15p is set to 30%. However, the Ge composition ratio may be increased so that the band offset value is maximized to increase the compressive strain.
[0057]
Further, since the HCMOS device is formed on the Si substrate, this HCMOS device is used where the element speed is required, and otherwise, the CMOS formed on the active region having a normal Si single composition. Devices may be made. With this configuration, integration with a MOS field effect transistor fabricated directly on a Si substrate is also possible. In addition, as a device using SiGeC, it is not necessary to form p and n type transistors on the same substrate. For example, in the case of an integrated circuit used for a mobile communication device, an amplifier, a mixer, etc. used in a high-frequency region where high-speed operation is required do not need to form a complementary circuit. For example, it may be possible to construct a part that performs digital signal processing that requires a complementary circuit by using a MOS device using only SiGeC (for example, n-type) and a CMOS device that uses a single Si composition. .
[0058]
Next, a method for manufacturing the HCMOS device of the first embodiment will be described with reference to FIGS. 5A to 5F are cross-sectional views showing an example of a manufacturing process for realizing the structure of the HCMOS device shown in FIG.
[0059]
First, in the step shown in FIG. 5A, a p well 11 and an n well 12 are formed in an Si substrate 10 by ion implantation.
[0060]
Next, in the step shown in FIG. 5B, the Si layer 13 including the δ-doped layer and the SiGeC layer 14 (Ge: 8.2%, C: 1) are formed on the wells 11 and 12 by the UHV-CVD method. %), SiGe layer 15 and Si layer 17 are grown. Although a δ-doped layer and a spacer layer are also formed, these layers are not shown for easy viewing.
[0061]
Next, in the step shown in FIG. 5C, a trench isolation trench is formed in order to electrically isolate the PMOS transistor and NMOS transistor, and the trench isolation 20 is formed by filling this trench with a silicon oxide film. Form. By this processing, the Si layer 13, the SiGeC layer 14, the SiGe layer 15, and the Si layer 17 are respectively converted into the Si layer 13n, the SiGeC layer 14n, the SiGe layer 15n, the Si layer 17n on the NMOS transistor side, and the Si layer 13p on the PMOS transistor side. , SiGeC layer 14p, SiGe layer 15p, and Si layer 17p. Further, the surfaces of the Si layers 17n and 17p are oxidized to form gate insulating films 19n and 19p, respectively.
[0062]
Next, in the step shown in FIG. 5D, a polysilicon film is deposited on the entire surface of the substrate, and then patterned to form a gate electrode 18n on the gate insulating films 19n and 19p of the NMOS transistor and PMOS transistor. , 18p, respectively. Thereafter, using the gate electrodes 18n and 18p as a mask, source / drain regions 16n are formed on the NMOS transistor side by implanting phosphorus ions (P +), and boron ions (B +) are implanted on the PMOS transistor side. As a result, source / drain regions 16p are formed. The depth of the source / drain region 16n of the NMOS transistor only needs to be deeper than at least the carrier accumulation layer in the SiGeC layer 14n, and the depth of the source / drain region 16p of the PMOS transistor is at least deeper than the carrier accumulation layer in the SiGe layer 15p. It is good if it is deep. This is because a channel is formed in each carrier storage layer in the SiGeC layer 14n and the SiGe layer 15p.
[0063]
Next, in the step shown in FIG. 5E, openings are formed in portions of the gate insulating films 19n and 19p above the source / drain regions 16n and 16p. In the step shown in FIG. Source / drain electrodes 21n and 21p are formed in the openings of the films 19n and 19p, respectively.
[0064]
As a result, an HCMOS device including an NMOS transistor and a PMOS transistor is formed on the Si substrate 10.
[0065]
As described above, according to the manufacturing method of this embodiment, although it is necessary to form different channels for the NMOS transistor and the PMOS transistor, the crystal growth can be performed in common for the NMOS transistor and the PMOS transistor, and the manufacturing is simple. be able to.
[0066]
(Second Embodiment)
In the first embodiment described above, the field effect transistor is formed by using the SiGeC layer lattice-matched with silicon. However, in this embodiment, the SiGeC layer is actively applied within a range in which the crystallinity is not deteriorated. In this case, a transistor is formed by introducing a strain into the transistor and utilizing a change in the band structure due to the strain. The structure of the HCMOS device according to this embodiment is basically a structure in which the PMOS transistor and NMOS transistor according to the first embodiment shown in FIG. 1 are realized in one transistor.
[0067]
FIGS. 6A to 6C show a case where compressive strain is generated in the SiGeC layer, a case where the SiGeC layer is lattice-matched to the Si layer (no strain), and a case where tensile strain is generated in the SiGeC layer. It is a figure which shows the state of the crystal structure in. As shown in FIG. 6A, when the lattice constant of the SiGeC layer is made larger than the lattice constant of the Si layer, the SiGeC layer is subjected to compressive strain, and the band between the lower end of the conduction band and the upper end of the valence band in the SiGeC layer. The gap value increases. On the other hand, when the lattice constant of the SiGeC layer is made smaller than the lattice constant of the Si layer, tensile strain occurs in the SiGeC layer, as shown in FIG. 5C, and between the lower end of the conduction band and the upper end of the valence band in the SiGeC layer. The band gap of is reduced. That is, since the band structure changes due to the strain of the SiGeC layer, the band offset value of the layer such as the Si layer adjacent to the SiGeC layer can be changed by actively utilizing this effect.
[0068]
Here, even when the lattice constant of the SiGeC layer is deviated from the lattice constant of the Si layer, the thickness of the SiGeC layer is set to such an extent that distortion is accumulated without causing lattice relaxation, thereby causing crystal defects such as dislocations. It is possible to effectively prevent a decrease in reliability of the element to be performed.
[0069]
7A and 7B are a band structure diagram and a cross-sectional view in the channel region of the field effect transistor according to the present embodiment. After growing the Si layer 13n on the Si substrate, the SiGeC layer 14n (Ge: 10%, C: 4%) having a large C composition ratio is grown, so that the band gap value in the SiGeC layer 14n increases. The lattice constant can be set to be small. The SiGeC layer 14n is subjected to tensile strain by reducing the thickness of the SiGeC layer 14n to such an extent that strain is accumulated without causing lattice relaxation. Therefore, in addition to the effect of increasing the band gap value by increasing the composition ratio of C, the band offset value of the conduction band at the interface between the SiGeC layer 14n and the Si layer 13n increases due to the tensile strain of the SiGeC layer 14n, and 2 The confinement efficiency of the two-dimensional electron gas (2DEG) is improved.
[0070]
Further, since the SiGeC layer 14n is not lattice-relaxed, the lattice constant on the upper surface matches the lattice constant of the Si layer 13n. Therefore, when the SiGe layer 15p is grown on the SiGeC layer 14n, the lattice constant of the SiGe layer 15p is larger than the lattice constant of the Si layer 13n, so that the SiGe layer 15p is subjected to compressive strain.
[0071]
Therefore, according to the semiconductor device according to the present embodiment, by introducing tensile strain into the SiGeC layer 14n and compressive strain into the SiGe layer 15p, the band offset value in the conduction band at the interface between the SiGeC layer 14n and the Si layer 13n can be obtained. The band offset value in the valence band at the interface between the SiGe layer 15p and the Si layer 17p is increased, and when this transistor is used as an NMOS transistor, a channel formed in the SiGeC layer 14n is used. On the other hand, when used as a PMOS transistor, by using a channel formed in the SiGe layer 15p, it is possible to form HCMOS devices having different channel positions while having a common gate electrode and source / drain regions. .
[0072]
In addition, by appropriately setting the thickness of each layer, it is possible to obtain an HCMOS device having a highly reliable field effect transistor with good crystallinity without introducing dislocations and defects due to lattice mismatch.
[0073]
Note that the broken line in FIG. 4 indicates a composition in which a tensile strain of 0.25% is applied to the SiGeC layer 14n in the present embodiment. In general, when the composition ratio of Ge in the SiGeC layer is 8.2 times the composition ratio of C, lattice matching with the Si layer occurs, so the Ge composition ratio is made smaller than 8.2 times the C composition ratio. Thus, tensile strain can be introduced into the SiGeC layer 14n. Further, when the composition ratio of C is y and the Ge composition is 8.2y-0.12, the lattice constant of the SiGeC layer 14n can be made 0.25% smaller than the lattice constant of the Si layer 13n. .
[0074]
As shown in FIG. 4, as in the case of the unstrained system, there is no band discontinuity in the valence band at the interface between the SiGeC layer 14n and the Si layer 13n, and a band discontinuity is formed only in the conduction band. I understand. When the C composition ratio is 2% or less, the band offset value of the conduction band is almost the same as in the case of no strain, and the ratio between the C composition ratio and the Ge composition ratio satisfies the lattice matching condition. Even if they are shifted, it is possible to obtain almost the same element characteristics as the lattice matching system. This means that the conditions can be widened from the viewpoint of controlling the composition ratio of C and the composition ratio of Ge during crystal growth of the SiGeC layer 14n, and the crystal growth of the SiGeC layer is facilitated. To. Further, when the C composition ratio is 2% or more, the band offset value can be increased even at the same C composition ratio as compared with the case of no distortion. Thereby, it is possible to cope with the case where it is necessary to increase the band offset value.
[0075]
Here, the lattice constant of SiGeC is used smaller than that of Si, but the thickness of the layer is such that lattice relaxation does not occur and strain is accumulated. There is no decline in sex.
[0076]
(Third embodiment)
In the first embodiment described above, a heterostructure in which the SiGeC layer is lattice-matched to the Si layer is formed in the channel region of the field effect transistor, and electrons or holes are confined in the band discontinuity at the heterointerface. Used as a carrier.
[0077]
In this embodiment, a region for confining carriers is not a heterointerface, but a quantum well structure is formed with a structure of Si / SiGeC / Si or Si / SiGe / Si, and a quantum well (SiGeC, SiGe) sandwiched between barrier layers is channeled. Are provided as transistors.
[0078]
FIG. 8 is a cross-sectional view of the HCMOS device according to this embodiment. This is a CMOS device structure in which an NMOS transistor and a PMOS transistor are formed on a Si substrate 30. In this structure, the p well 31 and the n well 32 are provided on the silicon substrate 30, and the first Si layers 33n and 33p each having a δ-doped layer doped with a group V element at a high concentration are provided thereon. This is the same as the structure of the HCMOS device shown in FIG. 1 in the first embodiment. However, the structure of the PMOS transistor and the NMOS transistor on the first Si layers 33n and 33p is different from the structure of the first embodiment.
[0079]
In the NMOS transistor, an SiGeC layer 34n having a composition lattice-matched to the first Si layer 33n is formed on the first Si layer 33n, and further, a second Si layer 35n is formed on the SiGeC layer 34n. Are stacked. In the present embodiment, there is a quantum well region (SiGeC layer 34n) sandwiched between two band discontinuities in the conduction band extending from the first Si layer 33n-SiGeC layer 34n to the second Si layer 35n. A carrier accumulation layer for confining a two-dimensional electron gas (2DEG) as a carrier is formed in the SiGeC layer 34n as the quantum well region (see the band diagram on the right side of FIG. 8). That is, a channel is formed in the SiGeC layer 34n during the operation of the NMOS transistor. A small SiGe layer 36n and a third Si layer 37n are sequentially formed on the second Si layer 35n.
[0080]
With this structure, as in the first embodiment, a channel for carrier movement is formed in the SiGeC layer 34n having a higher electron mobility than the Si layer, so that an NMOS transistor having a high operating speed can be obtained. It is done. In addition, since the thickness of the SiGeC layer 34n serving as the quantum well layer is small, the carrier confinement efficiency is improved as compared with the structure in the first embodiment, and can be realized with a system having a small mixed crystal ratio. Therefore, it is possible to suppress factors that degrade the mobility of electrons serving as carriers, such as carrier scattering due to the deterioration of the regularity of the crystal structure accompanying mixed crystallization.
[0081]
Also in the PMOS transistor, on the first Si layer 33p, a SiGeC layer 34p having a composition lattice-matched to the first Si layer 33p, a second Si layer 35p, a small SiGe layer 36p, The third Si layer 37p is formed in order, which is the same as the structure of the NMOS transistor. However, in the case of a PMOS transistor, in the valence band extending from the second Si layer 35p-SiGe layer 36p to the third Si layer 37p, a quantum well region (SiGe layer 36p) sandwiched between two band discontinuities is provided. A carrier accumulation layer for two-dimensionally confining holes serving as carriers is formed in the quantum well region. That is, when the PMOS transistor is operated, a channel is formed in the SiGe layer 36p. Since the SiGe layer 36p also has a higher hole mobility than the Si layer, the operating speed of the PMOS transistor is also increased.
[0082]
Further, in the NMOS transistor and the PMOS transistor, gate insulating films 39n and 39p made of a silicon oxide film are formed on the substrate, and gate electrodes 38n and 38p are formed on the gate insulating films 39n and 39p. . Source / drain layers 42n, 42p are formed on both sides of the gate electrodes 38n, 38p, and source / drain electrodes 41n, 41p are in contact with the source / drain regions 42n, 42p. Needless to say, in the NMOS transistor and the PMOS transistor, the travel of electrons and holes in the SiGeC layer 34n and the SiGe layer 36p, which are the quantum well regions, is controlled by the voltages applied to the gate electrodes 38n and 38p, respectively. Yes.
[0083]
In addition, a trench isolation 40 is formed between the NMOS transistor and the PMOS transistor by embedding a silicon oxide film in the isolation trench. By this trench isolation 40, the NMOS transistor and the PMOS transistor are electrically isolated from each other. Has been.
[0084]
According to the HCMOS device of this embodiment, as in the first embodiment, in the NMOS transistor, the SiGeC layer 34n that is lattice-matched to the Si layer and becomes the quantum well region is formed, and the SiGeC layer 34n has an electron. A channel for traveling is formed. Also in the PMOS transistor, a SiGe layer 36p serving as a quantum well region is formed, and a channel for holes to travel is formed in the SiGe layer 36p. Therefore, a high-performance HCMOS can be realized by integrating NMOS transistors and PMOS transistors having a high switching speed using a quantum well structure with high carrier confinement efficiency.
[0085]
However, in this embodiment, this HCMOS device may be used for a circuit that requires element speed, and a CMOS device formed on a normal Si substrate may be manufactured for other circuits. Integration with a MOS field effect transistor directly formed on the top is also possible.
[0086]
Note that both the NMOS transistor and PMOS transistor channels do not necessarily have to be quantum well regions.
[0087]
Next, a method for manufacturing an HCMOS device according to the third embodiment will be described with reference to FIGS. 9A to 9F are cross-sectional views showing an example of a manufacturing process for realizing the structure of the HCMOS device shown in FIG.
[0088]
First, the outline of the manufacturing process will be described. When the SiGeC layer 34, the second Si layer 35, and the SiGe layer 36 are grown, the thickness of the SiGeC layer 34 and the SiGe layer 36 is set to 10 nm so as to have a quantum well structure. Hereinafter, it is set to 3 nm, for example. Other portions are formed in substantially the same steps as the steps shown in FIGS.
[0089]
First, in the step shown in FIG. 9A, a p-well 31 and an n-well 32 are formed in an Si substrate 30 by ion implantation.
[0090]
9B, a first Si layer 33 including a δ-doped layer and a SiGeC layer 34 (Ge: 36%, C) are formed on the p well 31 and the n well 32 by the UHV-CVD method. : 4%), the second Si layer 35, the SiGe layer 36, and the third Si layer 37 are successively grown.
[0091]
Next, in the step shown in FIG. 9C, a trench isolation trench is formed in order to electrically isolate the PMOS transistor and the NMOS transistor, and then the trench isolation 40 is formed by filling the trench with a silicon oxide film. Form. By this processing, the first Si layer 33, the SiGeC layer 34, the second Si layer 35, the SiGe layer 36, the third Si layer 37, and the gate insulating film 39 are each converted into the first Si layer 33n on the NMOS transistor side. , SiGeC layer 34n, second Si layer 35n, SiGe layer 36n, third Si layer 37n, PMOS transistor side first Si layer 33p, SiGeC layer 34p, second Si layer 35p, SiGe layer 36p, Separated into a third Si layer 37p. Thereafter, the surfaces of the third Si layers 37n and 37p are oxidized to form gate insulating films 39n and 39p.
[0092]
9D, after forming the gate electrodes 38 and 38p, source / drain regions 42n are formed on the NMOS transistor side by phosphorus ion (P +) implantation, and the PMOS transistor On the side, source / drain regions 42p are formed by implanting boron ions (B +). The depth of the source / drain region 42n of the NMOS transistor only needs to be deeper than at least the SiGeC layer 34n, and the depth of the source / drain region 42p of the PMOS transistor only needs to be deeper than at least the SiGe layer 36p. This is because a channel is formed in the SiGeC layer 34n and the SiGe layer 36p.
[0093]
Thereafter, in the step shown in FIG. 9E, openings are formed in the gate insulating films 39n, 39p above the source / drain regions 42n, 42p. In the step shown in FIG. Source / drain electrodes 41n and 41p are formed, respectively.
[0094]
Through the above steps, the structure of the HCMOS device including the NMOS transistor and the PMOS transistor according to the third embodiment is realized.
[0095]
According to the manufacturing method of the present embodiment, there is an HCMOS device in which the NMOS transistor channel is the SiGeC layer 34n having a quantum well structure using a heterojunction, and the PMOS transistor channel is an SiGe layer 36p having a quantum well structure using a heterojunction. Easy to form. Moreover, according to the manufacturing method of this embodiment, although it is necessary to form different channels for the NMOS transistor and the PMOS transistor, the crystal growth can be performed in common for the NMOS transistor and the PMOS transistor, and it can be easily manufactured. it can.
[0096]
(Fourth embodiment)
FIG. 10 is a cross-sectional view showing the structure of the field effect transistor according to the fourth embodiment. The present embodiment relates to a structure for providing a source / drain contact suitable for a hetero field effect transistor.
[0097]
As shown in the figure, on the well 51 made of the Si layer, the SiGe buffer layer 52, the δ-doped layer 53, the spacer layer 54, the n-channel layer 67, the i-Si layer 55, i-Si _1-x Ge _x A layer 56, an i-Si layer 57, and a gate insulating film 58 are formed. Then, a gate electrode 65 is formed on the gate insulating film 58 and i-Si. _1-x Ge _x A source / drain contact W layer 61 and an Al source / drain electrode 63 are sequentially formed on regions of the layer 56 located on both sides of the gate electrode 65. Further, on both sides of the gate electrode 65, a part of the SiGe buffer layer 52, the δ-doped layer 53, the spacer layer 54, the n-channel layer 67, the i-Si layer 55, and i-Si _1-x Ge _x Source / drain regions 59 are formed in a region extending over the layer 56 and the i-Si layer 57. Further, the space between the gate electrode 65 and the Al source / drain electrode 63 is filled with a first-layer insulating film 66.
[0098]
Here, the structure of each part of the field effect transistor will be described.
[0099]
First, the composition ratio of Ge in the SiGe buffer layer 52 increases toward the top. The SiGe buffer layer 52 has a larger lattice constant than Si by being formed with a film thickness sufficient for lattice relaxation of the SiGe mixed crystal. On top of this, an n-channel using a strain effect is formed. Formation is possible. When a heterojunction between the Si layer and the SiGe layer is formed in a lattice-matched state with the Si substrate without using such a lattice-relaxed SiGe buffer layer, the valence band has a large step and a large discontinuity. However, since the discontinuity hardly appears in the conduction band, it is difficult to confine the two-dimensional electron gas to form an n-channel.
[0100]
Here, the composition ratio of Ge in the SiGe buffer layer 52 changes continuously, for example, from 0% to 30% or stepwise for each thin layer. At this time, lattice relaxation is generated in each layer, and the lattice constant in the substrate surface on the uppermost surface of the buffer layer is bulk Si. _0.7 Ge _0.3 To be the same. The reason why the composition ratio is changed in the vertical direction is to reduce the influence of crystal defects such as dislocations accompanying lattice relaxation on the channel above. The total film thickness of the SiGe buffer layer 52 is required to be about 1 μm.
[0101]
Si which does not add impurities on the SiGe buffer layer 52 _0.7 Ge _0.3 A spacer layer 54 made of is disposed. A carrier accumulation layer is formed at a discontinuous portion of the conduction band existing at the heterointerface between the spacer layer 54 and the Si layer 55 thereabove, and this carrier accumulation layer is used as an n-channel 67 that confines electrons two-dimensionally. .
[0102]
The δ-doped layer 53 is a layer doped with a V group element such as P or As at a high concentration in order to supply electrons as carriers to the n-channel 67. The spacer layer 54 on the δ-doped layer 53 is made of Si not doped with impurities. _0.7 Ge _0.3 The carrier electrons of the n-channel 67 and the ions of the δ-doped layer 53 are spatially separated, thereby reducing the scattering of the carrier electrons by ions and improving the mobility. The thicker the spacer layer 54, the more the carrier scattering effect due to the ionized impurities can be reduced. On the contrary, the carrier density is reduced, so that the thickness is preferably about 3 nm.
[0103]
i-Si _1-x Ge _x The layer 56 and the i-Si layer 57 are used to form a step in the valence band at the heterointerface and form the p-channel 68. X is preferably set to around 0.7.
[0104]
The gate insulating film 58 insulates between the gate electrode 65 and the underlying semiconductor layer, thereby reducing gate leakage current and enabling low power consumption operation of the device. Since an oxide film formed by oxidizing the SiGe layer 56 is a water-soluble and unstable film, it is preferable to use a silicon oxide film as a gate insulating film also in a SiGe-based field effect transistor. Therefore, in the Si-based hetero MOS device, it is preferable that the semiconductor layer immediately below the gate insulating film is a Si layer.
[0105]
That is, the field effect transistor according to the present embodiment has a channel region composed of the above laminated film, a source / drain region 59 indicated by a broken line in FIG. 10, and a current for introducing / extracting the current for the operation of the transistor. An Al source / drain electrode 63 and a gate electrode 65 for applying a voltage for controlling current are constituted. When this field effect transistor is used as an n-channel field effect transistor, a voltage is applied to the gate electrode 65 so as to form an n-channel 67, and the field effect transistor is used as a p-channel field effect transistor. Applies a voltage to the gate electrode 65 so as to form a p-channel 68.
[0106]
The feature of the invention according to this embodiment is that Si _1-xy Ge _x C _y A first semiconductor layer including layers (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), a second semiconductor layer having a band gap different from that of the first semiconductor layer, and the first and second layers A channel region having a carrier accumulation layer formed in a region near the interface between the semiconductor layers, a third semiconductor layer, and a fourth semiconductor layer having a larger band gap than the third semiconductor layer; And a source / drain contact layer made of a low-resistance conductor film formed immediately above the third semiconductor layer.
[0107]
When the field effect transistor of this embodiment is used as an n-channel field effect transistor, the i-Si layer 55 is made of Si. _1-xy Ge _x C _y The first semiconductor layer including the layers (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) (x = y = 0), the SiGe buffer layer 52 is the second semiconductor layer, and i-Si _1-x Ge _x The layer 56 is a third semiconductor layer, and the i-Si layer 57 is i-Si. _1-x Ge _x I-Si, which is a fourth semiconductor layer having a band gap larger than that of the layer 56 and is a third semiconductor layer _1-x Ge _x A source / drain contact W layer 61 is formed immediately above the layer 56.
[0108]
On the other hand, when the field effect transistor of this embodiment is used as a p-channel field effect transistor, i-Si is used. _1-x Ge _x Layer 56 is Si _1-xy Ge _x C _y The first semiconductor layer including the layers (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) (y = 0) and the third semiconductor layer, and the i-Si layer 57 is the second semiconductor layer And a fourth semiconductor layer having a band gap larger than that of the third semiconductor layer, i-Si being the third semiconductor layer _1-x Ge _x A source / drain contact W layer 61 is formed immediately above the layer 56.
[0109]
As described above, in the present embodiment, the region on the substrate side that makes contact with the Al source / drain electrode 63 is provided in a layer having a small band gap among the semiconductor layers for channel formation. In this embodiment, the p-channel forming Si layer 57 and i-Si _1-x Ge _x Of the hetero interface of layer 56, i-Si having a small band gap _1-x Ge _x The source / drain contact W layer 61 is provided immediately above the layer 56. As a result, the contact resistance is smaller than when a contact is provided immediately above the i-Si layer 57, which is the uppermost semiconductor layer, and the device can be operated at low power consumption and at high speed.
[0110]
Si on the Si layer _0.7 Ge _0.3 After growing W on the layer and then depositing metal (in this case Al), very low resistance contacts can be obtained. The contact using the SiGe film can obtain a contact having a single-digit resistance lower than that of the low-resistance contact using the silicide technology generally used as a low-resistance contact in the conventional CMOS device (IEEE Electron Device Letters Vol.17, No.7, 1996 pp360).
[0111]
In this paper, the SiGe layer is grown only for source / drain electrode contact formation. However, if the structure for contacting the SiGe layer for channel formation is taken as in this embodiment, transistor fabrication described later is performed. As will be apparent from the method, it is not necessary to newly grow a SiGe crystal, and productivity is improved.
[0112]
However, in this embodiment, this HCMOS device may be used where the device speed is required, and otherwise, a CMOS device formed on a normal Si substrate may be manufactured. Integration with a directly formed MOS field effect transistor is also possible.
[0113]
Next, a method for manufacturing the field effect transistor according to this embodiment will be described. FIGS. 11A to 11E and FIGS. 12A to 12E are cross-sectional views illustrating an example of a manufacturing process for realizing the structure of the field effect transistor shown in FIG.
[0114]
First, in the process shown in FIG. 11A, prior to epitaxial growth for channel formation, ions are implanted into the Si substrate 50 to form a p-well 51n and an n-well 51p that serve as the foundation of an NMOS transistor and a PMOS transistor.
[0115]
Next, in the step shown in FIG. 11B, before epitaxial growth on the substrate, the substrate is cleaned using an RCA cleaning method or the like to remove impurities on the surface. Thereafter, the oxide film on the surface is removed, the substrate is inserted into an epitaxial growth apparatus, and heating is performed in a vacuum state to obtain a clean surface. Then, epitaxial growth of a semiconductor layer for forming a channel region is performed on this clean surface. This semiconductor layer includes SiGe buffer layer 52, δ-doped layer 53, spacer layer 54, n-channel layer 67, i-Si layer 55, i-Si. _1-x Ge _x Layer 56, p-channel layer 68, i-Si layer 57, and the like are included. However, for the sake of clarity, the illustration of the δ-doped layer 53, the spacer layer 54, the n-channel layer 67, and the p-channel layer 68 is omitted. Hereinafter, the formation procedure of each layer in the semiconductor layer will be described.
[0116]
As a method for growing the semiconductor layer, an MBE method using a solid source or a UHV-CVD method using a gas source can be used. In the case of UHV-CVD, the atmosphere in the apparatus is first set to ultra high vacuum (10 ^-Ten After introducing the source necessary for crystal growth into the vacuum vessel, ^-Five -10 ^-6 Crystal growth is performed in a state where the degree of vacuum reaches about Torr.
[0117]
Therefore, also in this embodiment, after generating a clean surface on the substrate by the above-described processing, the substrate temperature is set to about 500 to 700 ° C. when the degree of vacuum in the vacuum vessel becomes sufficiently high, and each semiconductor crystal Do layer growth. Note that changing the substrate temperature affects the quality of the crystal, such as changing the composition ratio within a single semiconductor crystal layer, so the substrate temperature is basically changed while the single layer is grown. I won't let you. Further, at a high temperature such as 800 ° C. or higher, Ge and Si are interdiffused to impair the steepness of the heterointerface, or distortion is relaxed and channel characteristics are deteriorated. As shown in FIG.
[0118]
Crystal growth is performed by introducing a source gas necessary for crystal growth into a vacuum vessel in an ultra-high vacuum state. As a source gas used for crystal growth, disilane is used for the growth of the Si layer. For the growth of the SiGe layer, germane is used as the Ge source gas in addition to the source gas for growing the Si layer such as disilane. At this time, the composition ratio of Si and Ge in the SiGe layer can be controlled by adjusting the partial pressure ratio of each source gas. The gas flow rate is 10 degrees of vacuum. ^-Five -10 ^-6 Adjust to about Torr.
[0119]
First, a SiGe buffer layer 52 is formed by stacking a large number of SiGe layers whose composition ratios are changed stepwise and whose lattice is relaxed. At this time, in order to change the composition ratio stepwise, as described above, the ratio of the partial pressure of the Si source gas and the partial pressure of the Ge source gas is changed stepwise.
[0120]
Next, for forming the δ-doped layer 53, a dopant gas such as arsine or phosphine is introduced into the vacuum container together with disilane and germane.
[0121]
Here, when impurities introduced into the δ-doped layer 53 are mixed into the spacer layer 54, transistor characteristics deteriorate. Therefore, after the dopant gas is introduced into the vacuum vessel, the supply of the source gas is stopped once, and the degree of vacuum is reduced. After sufficiently improving, a gas for growing the spacer layer 54 is introduced to grow the spacer layer 54. The composition of the spacer layer 54 is uniformly Si _0.7 Ge _0.3 The growth is performed with the flow rate of disilane and germane fixed.
[0122]
After the growth of the spacer layer 54, the supply of the source gas is temporarily stopped, and after the degree of vacuum is improved, only disilane is introduced into the growth chamber, and the i-Si layer 55 not doped with impurities is grown.
[0123]
After the growth of the i-Si layer 55, disilane and germane are again introduced into the growth chamber. _1-x Ge _x Layer 56 is grown. The composition ratio of Ge is 70%. i-Si _1-x Ge _x After the growth of the layer 56, the supply of the source gas is temporarily stopped, and after the degree of vacuum is improved, only disilane is introduced into the growth chamber to grow the i-Si layer 57.
[0124]
With the above processing, the epitaxial growth process of the semiconductor layer constituting the channel region is completed.
[0125]
Next, in the step shown in FIG. 11C, the substrate is taken out from the UHV-CVD apparatus and introduced into a thermal oxidation furnace, and the surface of the uppermost i-Si layer 57 is oxidized to form a gate made of a silicon oxide film. An insulating film 58 is formed.
[0126]
Next, a gate electrode 65 is formed on the gate insulating film 58 in the step shown in FIG. The formation method of this gate electrode is the same as the conventional CMOS device process. That is, a polysilicon film is deposited, impurities are ion-implanted, and then the polysilicon film is patterned by dry etching to form gate electrodes 65n and 65p. As the impurity ions, boron fluoride ions (BF2 +) can be used. At the stage where the polysilicon film for the gate electrode is deposited, the source / drain regions are not formed.
[0127]
Next, in the step shown in FIG. 11E, impurity ions as dopants are implanted into the substrate using the gate electrodes 65n and 65p as a mask to form source / drain regions 59n and 59p, and then contact is made. For this purpose, etching is performed to remove the oxide film exposed on the substrate. In the ion implantation, the ion acceleration voltage is selected so that the peak of the impurity distribution is in the layer where the source / drain electrode contact is provided. As impurity ions to be implanted, arsenic ions (As +) or phosphorus ions (P +) that are n-type impurities are used in the NMOS transistor region, and boron ions (B +) that are p-type impurities are used in the PMOS transistor region. To do. Therefore, ion implantation for forming the source / drain region 59n of the NMOS transistor and ion implantation for forming the source / drain region 59p of the PMOS transistor need to be performed using separate masks.
[0128]
Immediately after ion implantation, annealing for activating impurities is performed. However, a short time (30 seconds) of RTA at about 1000 ° C. so that the annealing heat treatment does not cause interdiffusion of Si and Ge at the heterointerface and generation of crystal defects in the strain relaxation process existing in the Si / SiGe system. (Rapid thermal annealing) is preferably performed.
[0129]
Next, in the step shown in FIG. 12A, a photoresist mask (not shown) is formed again on the substrate, and the region between the NMOS transistor formation region and the PMOS transistor formation region is made at least more than the channel region by dry etching. The element isolation trench 71 is formed by digging deeply.
[0130]
Next, in the step shown in FIG. 12B, a first insulating film 72 is deposited on the entire surface of the substrate including the groove 71. In order to avoid a high-temperature process, it is preferable to use a TEOS film formed by a plasma CVD method that can be formed at a temperature of 500 ° C. or lower as a material constituting the insulating film. At this time, the trench isolation 73 is constituted by the insulating film embedded in the groove 71.
[0131]
Next, the source / drain contact, which is a feature of this embodiment, is formed by the following procedure. However, the steps for realizing the structure shown in FIG. 10 are not limited to the following procedures.
[0132]
In order to maximize the effects of the present embodiment, it is necessary that a very thin specific semiconductor layer which finally becomes the base of the contact exists. Therefore, in this embodiment, i-Si is used as a specific semiconductor layer serving as a base. _1-x Ge _x The layers 56n and 56p are selected and i-Si _1-x Ge _x Etching is performed until the layers 56n and 56p are exposed. This i-Si _1-x Ge _x When the layers 56n and 56p are exposed, it is preferable to use etching with high selectivity by wet etching. However, since wet etching has poor anisotropy and is not suitable for microfabrication, first, the region where the source / drain electrodes are to be formed is selectively removed from the first insulating film 72 by dry etching. It is desirable to form a contact hole and expose the gate insulating films 58n and 58p, and then perform wet etching. Examples of such processing include the following processing.
[0133]
First, as is well known, a hydrofluoric acid-based solution is used to remove the uppermost oxide film (gate insulating films 58n and 58p). When the i-Si layers 57n and 57p are exposed, hydrofluoric acid hardly removes silicon, so that the etching solution is changed to an etching solution that can remove the i-Si layer 57. Here, in this embodiment, i-Si under the i-Si layers 57n and 57p. _1-x Ge _x Since contacts are formed in the layers 56n and 56p, i-Si _1-x Ge _x An etchant that can selectively etch the i-Si layers 57n and 57p without etching the layers 56n and 56p so much is selected. Then, using this etchant, the i-Si layers 57n and 57p are removed, and the i-Si layers are removed. _1-x Ge _x Layers 56n and 56p are exposed. At this time, i-Si _1-x Ge _x A part of the layers 56n and 56p may be removed by overetching. As mentioned above, this i-Si _1-x Ge _x The layers 56n and 56p are epitaxially grown to form an n-channel in the channel region of the NMOS transistor. Therefore, according to the present embodiment, a new i-Si is formed to form a low resistance contact using the SiGe layer. _1-x Ge _x A process for growing the layers 56n and 56p is not necessary.
[0134]
This exposed i-Si is then used to form contacts. _1-x Ge _x A low resistance metal film is deposited on the layers 56n and 56p. As described above, when tungsten (W) is used as the metal material constituting the metal film, a contact having a very low resistance value can be formed. Therefore, in this embodiment, a gas obtained by diluting WF6 with hydrogen is used as a source gas by LPCVD, and the temperature condition is set to 400 ° C. _1-x Ge _x Source / drain contact W layers 61n and 61p are selectively grown on the layers 56n and 56p.
[0135]
Next, in the step shown in FIG. 12E, sputtering is performed to deposit an Al alloy film on the entire surface of the substrate, followed by patterning to form Al source / drain electrodes 63n and 63p. Through the above steps, a low resistance contact can be formed on the source / drain regions.
[0136]
As described above, in the Si-based hetero MOS device, the semiconductor upper layer is preferably a Si layer having a large band gap because of the use of a silicon oxide film as the gate insulating film. A technique of forming a contact metal layer after removing the layer is a technique particularly suitable for forming a Si-based hetero MOS device.
[0137]
(Fifth embodiment)
In the above embodiment, a channel structure using a heterojunction composed of Si and SiGe is taken as a representative example. However, the invention for forming a low-resistance contact in the source / drain region of an HCMOS device is limited to this embodiment. A channel formed by a heteroepitaxial laminated film having a configuration other than the laminated structure of Si and SiGe of this embodiment, for example, Si and Si _1-xy Ge _x C _y (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) A channel formed with a mixed crystal semiconductor may be used. The formation of a channel by a hetero interface necessarily requires the joining of two types of semiconductors having different band gaps, so that the formation of such a low resistance contact layer is effective.
[0138]
FIG. 13 is a cross-sectional view of an HCMOS device according to the fifth embodiment in which a low-resistance contact metal layer is formed in the structure shown in FIG.
[0139]
As shown in the figure, in the HCMOS device according to the present embodiment, source / drain contact W layers 25n and 25p are formed on the SiGe layers 15n and 15p.
[0140]
The feature of the invention according to the present embodiment is similar to the feature of the first embodiment, as well as the fourth embodiment. _1-xy Ge _x C _y A first semiconductor layer including layers (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), a second semiconductor layer having a band gap different from that of the first semiconductor layer, and the first and second layers A channel region having a carrier accumulation layer formed in a region near the interface between the semiconductor layers, a third semiconductor layer, and a fourth semiconductor layer having a larger band gap than the third semiconductor layer; And a source / drain contact layer made of a low-resistance conductor film formed immediately above the third semiconductor layer.
[0141]
In the NMOS transistor of this embodiment, the SiGeC layer 14n is made of Si. _1-xy Ge _x C _y The first semiconductor layer including the layers (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), the Si layer 13n is the second semiconductor layer, the SiGe layer 15n is the third semiconductor layer, and the Si layer Reference numeral 17n denotes a fourth semiconductor layer having a band gap larger than that of the SiGe layer 15n. A source / drain contact W layer 25n is formed immediately above the SiGe layer 15n which is the third semiconductor layer.
[0142]
On the other hand, in the PMOS transistor of this embodiment, the SiGe layer 15p is made of Si. _1-xy Ge _x C _y The first semiconductor layer including the layers (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) (y = 0) and the third semiconductor layer, and the Si layer 17p is the second semiconductor layer and the first semiconductor layer. A source / drain contact W layer 25p is formed on the fourth semiconductor layer having a larger band gap than the third semiconductor layer, and immediately above the SiGe layer 15p, which is the third semiconductor layer.
[0143]
As described above, in the present embodiment, the region on the substrate side (source / drain contact W layers 25n, 25p) that makes contact with the Al source / drain electrodes 21n, 21p is formed of the semiconductor layers for channel formation. Since it is provided immediately above the layer having a small band gap, the contact resistance is smaller than that provided above the Si layers 17n and 17p, which are the uppermost semiconductor layers, and the device can be operated at low power consumption and at high speed. become.
[0144]
In particular, since the source / drain contact W layers 25n and 25p made of tungsten (W) are provided so as to be in contact with the SiGe layers 15n and 15p, a very low contact resistance can be obtained.
[0145]
That is, in this embodiment, it is possible to reduce the contact resistance while exhibiting the effects of the first embodiment.
[0146]
(Sixth embodiment)
FIG. 14 is a cross-sectional view of an HCMOS device according to the sixth embodiment in which a low-resistance contact metal layer is formed in the structure shown in FIG.
[0147]
As shown in the figure, in the HCMOS device according to the present embodiment, source / drain contact W layers 45n and 45p are formed on the SiGe layers 36n and 36p serving as quantum well regions.
[0148]
The feature of the invention according to the present embodiment is similar to the feature of the third embodiment, as well as the fourth embodiment. _1-xy Ge _x C _y A first semiconductor layer including layers (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), a second semiconductor layer having a band gap different from that of the first semiconductor layer, and the first and second layers A channel region having a carrier accumulation layer formed in a region near the interface between the semiconductor layers, a third semiconductor layer, and a fourth semiconductor layer having a larger band gap than the third semiconductor layer; And a source / drain contact layer made of a low-resistance conductor film formed immediately above the third semiconductor layer.
[0149]
In the NMOS transistor of this embodiment, the SiGeC layer 34n that is the quantum well region is formed of Si. _1-xy Ge _x C _y The first semiconductor layer including the layers (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), the first Si layer 33n is the second semiconductor layer, and the SiGe layer 36n that is the quantum well region is the third semiconductor layer. The third Si layer 37n is a fourth semiconductor layer having a band gap larger than that of the SiGe layer 36n, and the source / drain contact W layer is directly above the SiGe layer 36n as the third semiconductor layer. 45n is formed.
[0150]
On the other hand, in the PMOS transistor of this embodiment, the SiGe layer 36p is made of Si. _1-xy Ge _x C _y The first semiconductor layer including the layers (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) (y = 0) and the third semiconductor layer, and the third Si layer 37p is the second semiconductor layer. In addition, a source / drain contact W layer 45p is formed on the fourth semiconductor layer having a band gap larger than that of the third semiconductor layer and immediately above the SiGe layer 36p which is the third semiconductor layer.
[0151]
As described above, in the present embodiment, the region on the substrate side (source / drain contact W layers 45n, 45p) for making contact with the Al source / drain electrodes 41n, 41p is defined as the semiconductor layer for channel formation. Since it is provided immediately above the layer with a small band gap, the contact resistance is smaller than that provided with a contact immediately above the Si layers 37n and 37p, which are the uppermost semiconductor layers, and the device can be operated with low power consumption and high speed. become.
[0152]
In particular, since the source / drain contact W layers 45n and 45p made of tungsten (W) are provided so as to be in contact with the SiGe layers 36n and 36p, a very low contact resistance can be obtained.
[0153]
That is, in this embodiment, it is possible to reduce the contact resistance while exhibiting the effects of the third embodiment.
[0154]
(Other variations)
In the first to sixth embodiments, the MOS field effect transistor in which the gate insulating film is provided under the gate electrode has been described. However, the present invention is not limited to such an embodiment. In particular, a field effect transistor using a hetero interface rather than a hetero MOS structure having an insulating film as the uppermost layer can be implemented even in a device using a Schottky junction that does not use an insulating film, and an effect of reducing resistance can be obtained. This is advantageous in terms of low power consumption and high speed operation.
[0155]
In the first to sixth embodiments, the δ-doped layer is formed. However, the present invention is not limited to such an embodiment, and the effect of the present invention can be exhibited without providing the δ-doped layer. Is possible. Even when the δ-doped layer is formed, the spacer layer is not always necessary.
[0156]
Instead of the SiGe layer in the first, second, third, fifth and sixth embodiments, a SiGeC layer to which a small amount of C is added may be provided.
[0157]
In the first, second, third, fifth, and sixth embodiments, the vertical relationship between the SiGeC layer and the SiGe layer may be reversed. In that case, in the fifth and sixth embodiments, the source / drain contact W layer may be formed immediately above the SiGeC layer in the source / drain region.
[0158]
【The invention's effect】
According to the semiconductor device of the present invention, in a semiconductor device having a field effect transistor, the Si layer and the Si layer _1-xy Ge _x C _y A layer and Si _1-xy Ge _x C _y Since the carrier storage layer formed in the layer is used as a channel, it is possible to provide a semiconductor device having a field effect transistor with high operation speed and high reliability.
[0159]
The structure of this semiconductor device can be easily realized by the method for manufacturing a semiconductor device of the present invention.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing the structure of a SiGeC-based HCMOS device according to a first embodiment.
FIG. 2 is a graph showing the dependence of lattice strain of a SiGeC layer in an HCMOS device on the Ge composition ratio and the C composition ratio.
FIG. 3 is a diagram showing the relationship between the composition ratio of Si, Ge, and C that cause lattice matching or tensile strain between the SiGeC layer and the Si layer of the SiGeC-based HCMOS device.
FIG. 4 is a diagram showing a relationship between a C composition ratio of an SiGeC layer and an energy gap value.
FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment.
FIG. 6 is a diagram showing the relationship between the composition of a SiGeC layer and strain due to lattice mismatch in the second embodiment.
FIG. 7 is a view showing a band lineup of a lattice matching SiGeC-HCMOS device according to a second embodiment.
FIG. 8 is a cross-sectional view showing the structure of an HCMOS device having a quantum well structure channel according to a third embodiment.
FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the third embodiment.
FIG. 10 is a cross-sectional view showing the structure of an HCMOS device according to a fourth embodiment.
FIG. 11 is a cross-sectional view showing the first half of the manufacturing process of the HCMOS device according to the fourth embodiment.
FIG. 12 is a cross-sectional view showing the latter half of the manufacturing process of the HCMOS device according to the fourth embodiment.
FIG. 13 is a cross-sectional view showing the structure of an HCMOS device according to a fifth embodiment.
FIG. 14 is a cross-sectional view showing the structure of an HCMOS device according to a sixth embodiment.
FIG. 15 is a cross-sectional view showing the structure of a conventional HCMOS device.
FIG. 16 is a diagram showing defects such as dislocations due to lattice mismatch distortion introduced into a heterointerface of a conventional HCMOS device.
[Explanation of symbols]
10 Si substrate
11 p-well
12 n-well
13 Si layer
14 SiGeC layer
15 SiGe layer
16 Source / drain region
17 Si layer
18 Gate electrode
19 Gate insulation film
21 Source / drain electrodes
25 Source / drain contact W layer
30 Si substrate
31 p-well
32 n-well
33 First Si layer
34 SiGeC layer
35 Second Si layer
36 SiGe layer
37 Third Si layer
38 Gate electrode
39 Gate insulation film
41 Source / drain electrodes
42 Source / drain regions
45 Source / drain contact W layer
50 Si substrate
51n p-well
51p n-well
52 SiGe buffer layer
53 δ-doped layer
54 Spacer layer
55 i-Si layer
56 i-Si1-xGex layer
57 i-Si layer
58 Gate insulation film
59 Source / drain regions
61 W layer for source / drain contact
63 Al source / drain electrode
65 Gate electrode
66 First layer insulating film
67 n-channel
68 p-channel

Claims (1)

A semiconductor device comprising a field effect transistor formed on a part of a semiconductor substrate and having a gate electrode, a source / drain region, and a channel region between the source / drain region,
In the above channel region,
A Si layer;
An Si _1-xy Ge _{x Cy} layer (0 ≦ x ≦ 1, 0 <y ≦ 1) formed in contact with the Si layer,
A carrier accumulation layer is formed in a region near the Si layer in the Si _1-xy Ge _{x Cy} layer,
The composition ratio of each element of the _{Si 1-x-y Ge x} C y layer, the composition ratio of the _{Si 1-x-y Ge x} C y layer and the Ge to the above Si layer becomes a composition ratio which is lattice-matched Is adjusted to 8.2 times the composition ratio of C ,
The composition ratio of C is 0.01 to 0.03,
A semiconductor device characterized in that carriers accumulated in the carrier accumulation layer are negative carriers .

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