JP3724485B2 - Signal processing circuit and signal processing method - Google Patents

Description

  The present invention relates to a signal processing circuit and a signal processing method, and more particularly to a signal processing circuit and a signal processing method for processing a digital signal generated from an FM (Frequency Modulation) modulation signal in an optical disc apparatus.

  Conventionally, a signal processing circuit for generating a digital FM signal from an FM modulated signal is provided in a reproduction system such as an optical disk device.

  FIG. 8 shows a block diagram of a signal processing circuit which is a conventional example. FIG. 9 shows an ideal timing chart in the conventional signal processing circuit. In FIG. 8, the signal processing circuit 10 includes a double edge detection circuit 11, a counter circuit 12, a latch circuit 13, and a digital LPF circuit 14.

  Both edge detection circuits 11 are supplied with an FM modulation signal shown in FIG. Both edge detection circuits 11 convert the supplied FM modulation signal into an FM pulse signal shown in FIG. 9B. The FM pulse signal is converted so as to be High when the level of the FM modulation signal is higher than the zero level, and Low when the level is lower. The both-edge detection circuit 11 detects the rising edge and the falling edge of the converted FM pulse signal and generates the both-edge signal 18 shown in FIG. Both edge signals are supplied to the counter circuit 12, the latch circuit 13, and the digital LPF 14 (18).

  The counter circuit 12 is supplied with a clock pulse from the terminal 16 and both edge signals from both edge detection circuits 11. The counter circuit 12 counts clock pulses and supplies the count values Q1 to Qn to the latch circuit 13 (19). The counter circuit 12 is reset by both edge signals and counts between edges.

  Referring to the count value in FIG. 9D, when the count value is counted up to N1, it is reset by the edge output of both edge signals shown in FIG. 9C, and the count value becomes zero. After the reset, the count value is restarted, and when the count value is counted up to N2, it is reset by the edge output of both edge signals. Thus, the count values when reset by both edge signals are N1, N2, N3, and N4.

  The latch circuit 13 is supplied with the count value from the counter circuit 12 and both edge signals from the both edge detection circuit 11. The latch circuit 13 latches the count values Q1 to Qn based on the edge output timing of both edge signals. In the count value of FIG. 9D, the latch circuit 13 latches the count values N1, N2, N3, and N4 at the reset timing. The latched count value is supplied to the digital LPF 14.

  The digital LPF 14 is supplied with the count value from the latch circuit 13 and the both edge signals from the both edge detection circuit 11. The digital LPF 14 performs digital processing based on the count value supplied from the latch circuit 13 and removes the high frequency component of the FM modulation signal. The FM signal subjected to the digital processing is supplied to the terminal 17. Signal processing is performed based on the output digital data of the digital LPF 14.

  In this way, the signal processing circuit detects both edge signals of the FM pulse signal generated from the FM modulation signal, counts the number of clocks with the counter based on the timing of both edge signals, and performs digital processing based on the count value. And signal processing.

  Further, when signal processing is performed at an ideal timing as shown in FIG. 9, a signal or count value corresponding to the FM modulation signal can be obtained, and an accurate digital FM signal can be obtained. However, noise is superimposed on the actual FM modulation signal.

  FIG. 10 shows an enlarged view of the actual FM modulation signal and the vicinity of the zero level. In FIG. 10, since the FM modulation signal and the zero level cross each other multiple times due to the noise of the FM modulation signal near the zero level, each of the rising edge and the falling edge of the signal is detected a plurality of times. Therefore, the both-edge signals supplied from the both-edge detection circuit 11 shown in FIG. 8 are not accurately detected.

  FIG. 11 shows a timing chart in an actual signal processing circuit. 11A shows an FM pulse signal, FIG. 11B shows a double-edge signal, FIG. 11C shows a clock pulse (CLK), and FIG. 11D shows a count value. The timing charts shown in FIGS. 11A to 11D are generated by the FM modulation signal in which actual noise shown in FIG. 10 is generated.

  Since the FM pulse signal in FIG. 11A crosses the zero level a plurality of times due to the noise of the FM modulation signal shown in FIG. 10, there are a plurality of rising and falling edges in the signal rising period T1 and the falling period T2. appear. A plurality of rising edges and falling edges occurring in the periods T1 and T2 are called chattering.

  By chattering generated in the FM pulse signal, a plurality of edges are detected in the periods T1 and T2 as shown in FIG. Since a plurality of edges are detected, the count start position of the clock pulse in FIG. 11C cannot be accurately determined, and the count value in FIG. 11D cannot be obtained accurately. was there.

  Therefore, when an actual FM modulation signal is signal-processed by the signal processing circuit, noise is generated in the FM modulation signal, so that chattering occurs in the FM pulse signal, and accurate signal processing of the digital FM signal cannot be performed. It was.

  Therefore, the method described below is used so that an accurate digital FM signal can be obtained even when an FM pulse signal in which chattering occurs is processed.

  FIG. 12 shows a timing chart for eliminating the conventional chattering. 12A shows an FM pulse signal, FIG. 12B shows an FM pulse signal after chattering removal, and FIG. 12C shows both edge signals. The FM pulse signal shown in FIG. 12A is subjected to chattering removal by the edge detection circuit 11 and becomes the FM pulse signal shown in FIG. Based on the FM pulse signal of FIG. 12B, both edge signals of FIG. 12C are generated.

  In the FM pulse signal after chattering removal in FIG. 12B, for example, when chattering occurs at timing t1, the rising edge is not determined until timing t2 when chattering disappears. Thereafter, the FM pulse signal continues at the same level in a certain period T3, and the FM pulse signal determines rising edge detection at timing t3. At this time, the period after the chattering removal until the rising edge detection of the FM pulse signal is confirmed is Tx.

  Next, when chattering occurs at timing t4, the falling edge is not determined until timing t5 when chattering disappears. Thereafter, the FM pulse signal is kept at the same level and is continued for a certain period T3. At timing t6, the FM pulse signal determines falling edge detection. At this time, the period after the chattering removal until the FM pulse signal determines the falling edge detection is Ty.

  On the other hand, at timing t7 and timing t9 at which chattering does not occur in the FM pulse signal, a fixed period T3 is delayed, and rising and falling edge detection is determined.

  As described above, the FM pulse signal after chattering removal is generated by a method of confirming rising and falling edge detection when the FM pulse signal reaches the same level for a certain period. In this method, if chattering occurs, the amount of delay until the edge detection is confirmed is the sum of the period until chattering ceases and a certain period. If chattering does not occur, only a certain period is delayed. It becomes quantity.

  As described above, noise is present in the actual signal, and the period at which the detection of the rising and falling edges of this signal occurs is not constant, and accurate signal processing cannot be performed.

  In addition, in order to remove noise, the period during which noise is generated and a certain period are delayed to determine edge detection, and when the noise is present and when it is not present, the delay amount when detecting the edge is In contrast, the period of the signal changes. As a result, the counter value becomes an abnormal value, and accordingly, the value held in the latch circuit also increases or decreases with respect to the normal value. As a result, an accurate signal cannot be obtained.

  Therefore, an object of the present invention is to provide a signal processing circuit and a signal processing method that can solve the above-described problems and that can process an input pulse signal with an accurate period.

In order to solve the above problem, the invention according to claim 1 is a signal processing circuit that generates a digital signal corresponding to an input pulse signal, and generates a phase difference pulse signal having a predetermined phase difference from the input pulse signal. A phase difference pulse signal generating means for setting, and a setting means for setting a predetermined period including at least one pulse allowing a noise component of the input pulse signal based on the phase difference pulse signal generated by the phase difference pulse signal generating means And a clock pulse output means for outputting a clock pulse with either polarity during a predetermined period set by the setting means, and a clock pulse output with a positive polarity and the clock pulse output with a negative polarity, respectively. separate counting means for counting, the phase difference pulse signal and counting means generated by the phase difference pulse signal generating means counts Characterized by providing an output means for outputting an output digital signal values based.

According to the first aspect of the present invention, the phase difference pulse signal generating means for generating the phase difference pulse signal having a predetermined phase difference from the input pulse signal, and the phase difference pulse signal generated by the phase difference pulse signal generating means And setting means for setting a predetermined period including at least one pulse that allows noise components in the input pulse signal, and outputting a clock pulse with either polarity during the predetermined period set by the setting means A clock pulse output means for counting, a count means for independently counting the clock pulse output with a positive polarity and the clock pulse output with a negative polarity, and a phase difference pulse signal generated by a phase difference pulse signal generation means and by the count value of the counting means based on an output means for outputting an output digital signal, a plurality of pulse signals Cow Can be obtained bets value, based on the count value of the plurality of pulse signals, it is possible to output a more accurate output digital signal.

  According to a second aspect of the present invention, the clock pulse output means outputs first clock pulse output means for outputting a clock pulse when the input pulse signal is positive, and clock pulse is output when the input pulse signal is negative. And a second clock pulse output means for outputting the first clock pulse output means for counting the clock pulses from the first clock pulse output means and a clock from the second clock pulse output means. And second counting means for counting pulses.

  According to the second aspect of the present invention, the clock pulse output means includes the first clock pulse output means and the second clock pulse output means, and the count means includes the first count means, the second count pulse means, More accurate signal processing can be performed.

The invention according to claim 3, the rising edge output means outputting means outputs a third timing signal in response to the rising edge of the phase difference pulse signal, the fourth according to the down edge of the phase difference pulse signal Down edge output means for outputting the first timing means, first latch means for latching the count value of the first count means in response to the third timing signal, and second count in response to the fourth timing signal And second latch means for latching the count value of the means.

  According to the third aspect of the invention, the output means outputs the third and fourth timing signals in response to the up edge of the phase difference pulse signal, the up edge output means and the down edge output means, and the third and fourth By having the first and second latch means for latching the count value according to the four timing signals, it is possible to perform more precise input pulse signal processing and improve the accuracy of the output signal Can do.

  According to a fourth aspect of the invention, the output means delays the third timing signal and outputs the fifth timing signal, and the fourth timing signal delays the fourth timing signal. Second delay means for outputting a timing signal, the first counting means is reset in response to the fifth timing signal, and the second counting means is reset in response to the sixth timing signal. It is characterized by that.

  According to the invention described in claim 4, the output means includes first and second delay means for delaying the third and fourth timing signals and outputting the fifth and sixth timing signals, By resetting the first and second counting means in accordance with the fifth and sixth timing signals, respectively, it is possible to perform more precise processing of the input pulse signal and improve the accuracy of the output signal. Can do.

  According to a fifth aspect of the present invention, the output means includes third delay means for delaying the output of the phase difference pulse signal and outputting a delayed phase difference pulse signal, and the output means has a third delay means according to the output of the delayed phase difference pulse signal. It has switching means for switching the output of the first count value latched by one latch means and the second count value latched by the second latch means.

  According to the fifth aspect of the present invention, the output means outputs the delayed phase difference pulse signal, the third delay means, and the first count value and the second count value according to the output of the delayed phase difference pulse signal. Therefore, it is possible to perform more precise processing of the input pulse signal and improve the accuracy of the output signal.

  The invention described in claim 6 is characterized in that the output means includes a digital low-pass filter.

  According to the invention described in claim 6, by using the digital low-pass filter, it is possible to output a more accurate output digital signal based on the processed signal.

The invention according to claim 7 is a signal processing method for generating a digital signal corresponding to an input pulse signal, a phase difference pulse signal generation procedure for generating a phase difference pulse signal having a predetermined phase difference from the input pulse signal, A setting procedure for setting a predetermined period including at least one pulse that allows a noise component in the input pulse signal based on the phase difference pulse signal generated in the phase difference pulse signal generation procedure, and a predetermined value set in the setting procedure the period, the clock pulse output procedure for outputting a clock pulse in one polarity, a counting procedure for counting the clock pulses independently output by the clock pulse and the negative polarity output a positive polarity, position output that outputs the phase difference output digital signal count value based on the pulse steps the phase difference pulse signal and counting procedure generated by A predetermined period including at least one pulse to permit the noise component of the forward and force pulse signal, and having a clock pulse output procedure for outputting a clock pulse in either polarity.

According to invention of Claim 7, the phase difference pulse signal generation procedure which produces | generates the phase difference pulse signal which has a predetermined phase difference with an input pulse signal, and the phase difference pulse signal produced | generated by the phase difference pulse signal generation procedure Based on the setting procedure to set a predetermined period including at least one pulse that allows noise components in the input pulse signal, and to output a clock pulse with either polarity during the predetermined period set in the setting procedure By providing the clock pulse output procedure, a count value of a plurality of pulse signals can be obtained, and a more accurate output digital signal can be output based on the count values of the plurality of pulse signals.

According to the signal processing circuit of the present invention, the phase difference pulse signal generating means for generating the phase difference pulse signal having a predetermined phase difference from the input pulse signal, and the phase difference pulse signal generated by the phase difference pulse signal generating means Based on the setting means for setting a predetermined period including at least one pulse that allows a noise component in the input pulse signal, and outputs a clock pulse with either polarity during the predetermined period set by the setting means A clock pulse output means, a count means for independently counting the clock pulse output with positive polarity and the clock pulse output with negative polarity, a phase difference pulse signal generated by the phase difference pulse signal generation means, and by the count value of the counting means based on an output means for outputting an output digital signal, a plurality of pulse signals Cow Can be obtained bets value, based on the count value of the plurality of pulse signals, it is possible to output a more accurate output digital signal. In addition, since the count timing can be generated simply by generating a phase difference pulse signal having a predetermined phase difference from the input pulse signal by phase difference pulse generation means such as a PLL circuit, the circuit can be simplified.

  FIG. 1 is a block diagram of an optical disc apparatus according to an embodiment of the present invention.

  In FIG. 1, an optical disc apparatus 100 includes a disc 40, an optical system 41, a spindle motor 42, a thread motor 43, a laser driver 44, a front monitor 45, an ALPC (Absolute Time In Pregroove) 46, a storage compensation circuit 47, and a wobble signal processing unit. 48, RF amplifier 49, focus / tracking servo circuit 50, feed servo circuit 51, spindle servo circuit 52, CD encode / decode circuit 53, D / A converter 54, audio amplifier 55, RAM 56, 58, CD-ROM encode / decode The circuit 57, the interface / buffer controller 59, the CPU 60, the host computer 61, and the like.

  A signal processing circuit for performing signal processing of the present invention is provided in the wobble signal processing unit 48. This circuit processes the FM modulated signal to generate a digital FM signal. The recording system includes an optical system 41, a laser driver 44, a front monitor 45, an ALPC 46, a storage compensation circuit 47, a wobble signal processing unit 48, and the like. With these circuits, a signal is recorded on a storage medium such as an optical disk.

  The optical system 41 is an optical head that reads a signal from the disk 40, and includes an objective lens, an actuator, a quarter wave plate, a collimator lens, a beam splitter, a light emitting element (laser diode), a light receiving element (photodetector), and the like. Is done. The optical system 41 is controlled by a sled motor 43 and a focus / tracking servo circuit 50.

  The thread motor 43 moves the optical pickup in the radial direction of the disk by driving control of the feed servo circuit 51. The focus / tracking servo circuit 50 controls focus servo and tracking servo.

  The disc 40 is a CD-R (write-once disc), a CD-RW (rewritable disc) or the like, and is controlled by a spindle motor 42.

  The spindle motor 42 is controlled by the spindle servo circuit 52 to rotate the disk at a predetermined rotational speed.

  The focus / tracking servo circuit 50, the feed servo circuit 51, and the spindle servo circuit 52 are controlled based on signals from the CPU 60 and the RF amplifier 49. The RF amplifier 49 is a head amplifier that amplifies the reproduction signal. The RF amplifier 49 shown here includes a matrix amplifier, extracts various servo signals in addition to the main signal, and outputs them to each servo control circuit.

  These control circuits determine the desired position of the disk 40, and a signal of the disk 40 is sent from the optical system 41 to the RF amplifier 49. From this RF amplifier 49, an EFM signal is sent to the CD encode / decode circuit 53. The CD encoding / decoding circuit 53 performs processing such as CIRC (Cross Interleaved Reed-Solomon Code) encoding / decoding, EFM (Eight to Fourteen Modulation), and synchronization detection. The CD encode / decode circuit 53 receives a clock pulse from the CPU 60 and performs demodulation processing. The demodulated signal is sent to the CD-ROM encode / decode circuit 57. The CD-ROM encoding / decoding circuit 57 performs processing such as encoding / decoding of ECC (Error Correction Coding) unique to the CD-ROM, detection of a header, and the like. In order to perform the processing, data is temporarily stored using the RAM 56. The processed data is sent to the interface / buffer controller 59. The interface / buffer controller 59 transmits / receives data to / from the host computer and controls the data buffer. In order to perform the processing, the RAM 58 is used to temporarily store data.

  The CD-ROM encode / decode circuit 57 and interface / buffer controller 59 are also controlled by the CPU 60. After processing by the interface / buffer controller 59, the processing result is sent to the host computer 61, and processing corresponding to the data is performed.

  On the other hand, when outputting sound, the demodulated signal from the CD encode / decode circuit 53 is sent to the D / A converter 54 and converted from digital to analog. The analog-converted signal is amplified by the audio amplifier 55, and this audio signal is output.

  Thus, the reproduction / recording process is performed on the optical disc apparatus 100, and the signal processing circuit of the present invention is provided on the wobble signal processing unit 48 and processes the digital FM signal generated from the FM modulation signal.

  FIG. 2 is a block diagram of a signal processing circuit according to an embodiment of the present invention. In FIG. 2, the signal processing circuit 30 provided in the wobble signal processing unit 48 includes a positive polarity gate 71, a negative polarity positive gate 72, a counter circuit (positive polarity) 73, a counter circuit (negative polarity) 74, and latch circuits 75 and 76. , A switching circuit 78, a digital LPF 79, an RS flip-flop 77, delay circuits 80, 81, 82, and an OR gate 83.

  The positive polarity gate 71 and the negative polarity gate 72 are connected to a wobble FM pulse signal terminal 84 and a clock terminal 85. The positive gate 71 and the negative gate 72 are supplied with a zero level 70 from a wobble FM pulse signal terminal 84 and a clock pulse signal from a clock terminal 85.

  The positive polarity gate 71 sends a clock pulse to the counter circuit 73 when the level of the FM modulation signal is higher than the zero level, that is, when the FM pulse signal is at a high level. The negative polarity gate 72 sends a clock pulse to the counter circuit 74 when the FM modulation signal level is smaller than the zero level, that is, when the FM pulse signal is at a low level.

  The counter circuit 73 has a reset input and a carry output, and counts clock pulses supplied from the positive polarity gate 71. The counter circuit 73 resets the count values Q1 to Qn by a signal input from the reset input. The counter circuit 73 outputs a pulse from the carry output to the delay circuit 81 and the latch circuit 76 when the count reaches a predetermined value.

  The delay circuit 81 delays the carry output of the counter 73 for a predetermined period and supplies it to the reset input of the counter circuit 74, the set of the RS flip-flop 77, and the OR gate 83.

  The latch circuit 75 latches the count value of the counter circuit 73 by the carry output of the counter circuit 74. The latched count value is supplied to the B input of the switching circuit 78.

  The counter circuit 74 has a reset input and a carry output, and counts clock pulses supplied from the negative polarity gate 72. The counter circuit 74 resets the count value by a pulse input from the reset input. The counter circuit 74 outputs a pulse from the carry output to the delay circuit 80 and the latch circuit 75 when the count reaches a predetermined value.

  The delay circuit 80 delays the carry output of the counter circuit 74 for a predetermined period, and supplies it to the reset input of the counter circuit 73, the reset of the RS flip-flop 77, and the OR gate 83.

  The latch circuit 76 latches the count value of the counter circuit 74 by the carry output of the counter circuit 73. The latched count value is sent to the input A of the switching circuit 78.

  The switching circuit 78 switches the output of the count value supplied from the latch circuits 76 and 75 to the A input and the B input according to the pulse from the RS flip-flop 77.

  The RS flip-flop 77 is a flip-flop having a reset set, and controls switching of the switching circuit 78 by the Q output. The Q output output from the RS flip-flop 77 is sent to the switching circuit 78.

  The output of the A and B inputs is switched based on the above Q output. The switched A output or B input is supplied to the digital LPF 79, and a digital FM signal is output from the terminal 86.

  In the digital LPF 79, a pulse obtained by delaying the output from the OR gate 83 by the delay circuit 82 is supplied. The digital LPF 79 outputs a digital FM signal based on the supplied pulse.

  In this way, two positive and negative gates are provided in the signal processing circuit, the timing at the time of counting the high level and the low level of the FM pulse signal is obtained, and the high or low period including chattering is counted. Thus, the high period and the low period of the FM pulse signal can be reliably determined.

  FIG. 3 shows a timing chart of the signal processing circuit of the present invention. 3A is an FM pulse signal, FIG. 3B is a clock pulse (CLK), FIG. 3C is a positive gate, FIG. 3D is a negative gate, and FIG. 3E is positive. 3 (F) is a negative count value, FIG. 3 (G) is a carry pulse (positive), FIG. 3 (H) is a carry pulse (negative), and FIG. 3 (I) is a delay (Delay) pulse ( 3 (J) is a delay pulse (negative), FIG. 3 (K) is an RS flip-flop, FIG. 3 (L) is an output count value, FIG. 3 (M) is an OR gate output, FIG. 3N shows a delayed pulse (OR).

  The FM pulse signal in FIG. 3A and the clock pulse in FIG. 3B are supplied to the positive polarity gate and the negative polarity gate. The positive polarity gate is closed when the FM pulse signal is at a low level, while the negative polarity gate is opened and is output as shown in FIGS. 3 (C) and 3 (D).

  At time t1, the FM pulse signal changes to high level. At this time, the positive polarity gate is opened and a clock pulse is supplied to the counter circuit 73. The counter circuit 73 counts the supplied clock pulses. The positive count value is as shown in FIG.

  From time t1 to t2, chattering occurs in the FM pulse signal. At this time, since the pulse supply from the positive polarity gate becomes intermittent, the positive polarity count value gradually increases.

  After a lapse of a certain period Tc from the time t 1 when the clock pulse signal is supplied to the counter circuit 73, the counter circuit 73 supplies the carry pulse (positive) of FIG. 3G to the delay circuit 81 and the latch circuit 76. At this time, it is time t3. Here, the period Tc is determined by the count value.

  At time t3, the latch circuit 76 latches the count value of the counter circuit 74 based on the carry pulse (positive) from the counter circuit 73. Thereafter, the carry pulse (positive) from the counter circuit 73 is delayed by the delay circuit 81. The delayed delayed pulse (positive) shown in FIG. 3 (I) is supplied to the reset input of the counter circuit 74. Thereafter, the count value of the counter circuit 74 is reset. The delay pulse (positive) by the delay circuit 81 is set in consideration of the latch period.

  Since the high level state of the FM pulse signal is maintained between times t2 and t4, the positive polarity count value shows a constant increase.

  At time t4, the FM pulse signal changes to a low level. At this time, the negative polarity gate is opened and a clock pulse is supplied to the counter circuit 74. The counter circuit 74 counts the supplied clock pulses. The negative count value is as shown in FIG.

  From time t4 to t5, chattering occurs in the FM pulse signal. At this time, the clock pulses supplied from the positive polarity gate 71 and the negative polarity gate 72 become intermittent. Therefore, the positive count value and the negative count value increase gently.

  After a lapse of a certain period Tc from the time t4 when the clock pulse signal is supplied to the counter circuit 74, the counter circuit 74 receives the carry pulse (negative) in FIG. 3 (H) as a latch circuit 75, a positive gate 71, and a delay circuit 80. To supply. At this time, it is time t6.

  At time t6, the latch circuit 75 latches the count value of the counter circuit 73 based on the carry pulse (negative) from the counter circuit 74. Thereafter, the carry pulse (negative) from the counter circuit 74 is delayed by the delay circuit 80. The delayed delayed pulse (negative) shown in FIG. 3J is supplied to the reset input of the counter circuit 73. Thereafter, the count value of the counter circuit 73 is reset.

  Between times t6 and t7, the low level state of the FM pulse signal is maintained, so the negative count value shows a constant increase.

  Also, the RS flip-flop 77 shown in FIG. 3K is set by a delay pulse (positive) from the delay circuit 81. Further, it is reset by a delay pulse (negative) from the delay circuit 80. The Q output generated based on these sets and resets is supplied to the switching circuit 78.

  The switching circuit 78 switches to output an A input when the Q output is at a high level, and switches to output a B input when the Q output is at a low level. This output is an output count value shown in FIG. That is, the output of the A input is switched by the carry pulse (positive) of the counter circuit 73, and the output of the B input is switched by the carry pulse (negative) of the counter circuit 74. When these carry pulses are supplied to the OR gate 83, an OR gate output as shown in FIG. The output from the OR gate 83 is supplied to the delay circuit 82 and is delayed as shown in FIG. The delay amount of the delay circuit 82 is determined in consideration of the period required for output from the switching circuit 78.

  The output data from the switching circuit 78 and the clock pulse delayed by the delay circuit 82 are sent to the digital LPF 79. Data sent to the digital LPF 79 is signal-processed based on the delayed clock pulse.

  In this way, in the FM pulse signal in which chattering has occurred, the positive and negative polarity gates are switched according to the period Tc, that is, the count value of each polarity, whereby a more accurate count value can be obtained. Accordingly, accurate signal processing can be performed.

  On the other hand, when chattering does not occur at times t7 to t10, the negative and positive gates are switched after the elapse of the period Tc from the rise and fall of the FM pulse signal. Thereafter, similarly to the above, each counter circuit and each latch circuit are controlled to perform signal processing.

  Thus, even when chattering does not occur, the positive and negative polarity gates are switched according to the period Tc, that is, the count value of each polarity, so that a more accurate count value can be obtained. Therefore, the counting means for counting clock pulses generates a timing signal, and the input pulse signal is controlled based on this timing signal, so that the pulse cycle can be made constant and signal processing can be stabilized. Accurate signal processing can be performed.

  FIG. 4 shows a block diagram of a modification of the signal processing circuit shown in FIG. In the signal processing circuit shown in FIG. 4, the same components as those in FIG. 4, the signal processing circuit 31 includes AND gates 87 and 88, an inverter 89, a high gate counter 90, a low gate counter 93, a counter circuit (positive polarity) 97, a counter circuit (negative polarity) 95, gate circuits 91 and 94, Latch circuits 96 and 98, RS flip-flop 92, high edge output circuit 99, low edge output circuit 102, delay circuits 101 and 103, and the like.

  The AND gate 87 is connected to the FM pulse signal terminal 84 and the clock terminal 85. The AND gate 87 performs an AND operation on the supplied clock pulse and FM pulse signal. The AND gate 88 is connected to the FM pulse signal terminal 84 and the inverter 89. The AND gate 88 performs an AND operation on the clock pulse and the inverted signal of the FM pulse signal from the inverter 89.

  The high gate counter 90 counts clock pulses from the AND gate 87. The high gate counter 90 counts clock pulses during a period when the FM pulse signal is at a high level. The high gate counter 90 supplies the counted values Q1 to Qn to the gate circuit 91.

  The gate circuit 91 sets the pulse to the R-S flip-flop 92 when the supplied count value reaches a predetermined value, for example, when the value corresponds to half of the minimum half cycle of the FM pulse signal. Supply to the terminal.

  The low gate counter 93 has the same configuration as the high gate counter 90, and counts clock pulses from the AND gate 88. The low gate counter 93 counts clock pulses while the FM pulse signal is at a low level. The low gate counter 90 supplies the lower bits Q1 to Qk among the counted values Q1 to Qn to the gate circuit 94.

  The gate circuit 94 resets the pulse of the RS flip-flop 92 when the supplied count value becomes a predetermined value, for example, when the count value becomes a value corresponding to half of the minimum half cycle of the FM pulse signal. Supply to the terminal.

  In the RS flip-flop 92, when a pulse is input from the gate circuit 91 to the set terminal, the Q output is supplied to the low gate counter 93 to start counting. When a pulse is input from the gate circuit 94 to the reset terminal, the inverted Q output is supplied to the high gate counter 90 and starts counting. The Q output is supplied to the switching circuit 78, the high edge output circuit 99, and the low edge output circuit 102.

  The high edge output circuit 99 supplies a pulse to the delay circuit 101 and supplies a pulse to the latch circuit 96 according to the rising edge of the Q output. The delay circuit 101 delays the pulse from the high edge output circuit 99 and supplies it to the counter circuit 95 and the OR gate 83.

  The low edge output circuit 102 supplies a pulse to the delay circuit 103 and supplies a pulse to the latch circuit 98 according to the falling edge of the Q output. The delay circuit 103 delays the pulse from the low edge output circuit 102 and supplies it to the counter circuit 97 and the OR gate 83.

  The counter circuit 95 has a reset input and a carry output, and counts clock pulses from the AND gate 88. The counter circuit 95 counts clock pulses while the FM pulse signal is at a low level. The counter circuit 95 supplies the count values Q1 to Qn to the latch circuit 96. Further, the count value of the counter circuit 95 is cleared by a pulse from the delay circuit 101.

  The latch circuit 96 latches the count value of the counter circuit 95 with a pulse from the high edge output circuit 99. The latched count value is supplied to the A input of the switching circuit 78.

  The counter circuit 97 has the same configuration as the counter circuit 95, and counts clock pulses from the AND gate 87. The counter circuit 97 counts clock pulses during a period when the FM pulse signal is at a high level. The counter circuit 97 supplies the count values Q1 to Qn to the latch circuit 98. Further, the count value of the counter circuit 97 is cleared by a pulse from the delay circuit 103.

  The latch circuit 98 latches the count value of the counter circuit 95 with a pulse from the low edge output circuit 102. The latched count value is supplied to the B input of the switching circuit 78.

  FIG. 5 shows a timing chart of the signal processing circuit shown in FIG. 5A is an FM pulse signal, FIG. 5B is a clock pulse (CLK), FIG. 5C is an AND gate 87, FIG. 5D is an inverter 89, and FIG. 5E is an AND gate 88. 5 (F) is an R-SFF set input, FIG. 5 (G) is an R-SFF reset input, FIG. 5 (H) is a Q output, FIG. 5 (I) is an inverted Q output, and FIG. FIG. 5K shows the low edge output, FIG. 5L shows the delay pulse 101, and FIG. 5M shows the delay pulse 103.

  The FM pulse signal in FIG. 5A is supplied to the AND gate 87 and the inverter 89, and the clock pulse in FIG. 5B is supplied to the AND gates 87 and 88. The inverter in FIG. 5D shows a signal obtained by inverting the FM pulse signal in FIG. The AND gate 87 performs an AND operation on the clock pulse and the FM pulse signal and outputs a signal as shown in FIG. The AND gate 88 integrates the clock pulse and the inverted signal of the FM pulse signal and outputs a signal as shown in FIG.

  For example, the low gate counter 93 counts clock pulses from the AND gate 88 and supplies the count value to the gate circuit 94. The gate circuit 94 supplies a pulse to the reset input of the RS flip-flop 92 when the count value reaches a certain value.

  At time t1, the low gate counter 93 resets the count value when the inverted Q output becomes a high level as shown in FIG. 5 (I), and the RS flip-flop 92 is reset as shown in FIG. 5 (G). A pulse is supplied to the reset input. The high gate counter 90 counts clock pulses from the AND gate 87 in FIG. 5C because the Q output in FIG. 5H is in a low level state.

  At time t2, the count value of the counter circuit 97 is reset by a delay pulse from the delay circuit 103 shown in FIG. A period between times t1 and t2 is a delay period T4 of a pulse output from the delay circuit 103.

  When the count value of the high gate counter 90 becomes a constant value at time t3, the count value is supplied to the set input of the RS flip-flop 92 as shown in FIG.

  The RS flip-flop 92 sets the Q output in FIG. 5H to the high level and sets the inverted Q output in FIG. 5I to the low level according to the set input. When the Q output becomes high level, the low gate counter 93 counts the clock pulses from the AND gate 88 in FIG. In the high gate counter 90, the count value is reset when the Q output becomes a low level.

  5J supplies a pulse to the latch circuit 96 and the delay circuit 101 in accordance with the rising edge of the Q output. The latch circuit 96 latches the count value of the counter circuit 95 according to the high edge output. The pulse delayed by the delay circuit 101 is output as shown in FIG.

  At time t4, the count value of the counter circuit 95 is reset by the delay pulse 101 from the delay circuit 101 in FIG. A period from time t3 to t4 is a delay period T4 of a pulse output from the delay circuit 101.

  When the count value of the low gate counter 93 becomes a constant value at time t5, the gate circuit 94 supplies a pulse to the reset input of the RS flip-flop 92.

  The RS flip-flop 92 sets the Q output in FIG. 5H to the low level and sets the inverted Q output in FIG. 5I to the high level according to the set input. When the inverted Q output becomes high level, the high gate counter 90 counts the clock pulses from the AND gate 87 in FIG. In the low gate counter 93, the count value is reset when the inverted Q output becomes a low level.

  5K supplies a pulse to the latch circuit 98 and the delay circuit 103 in accordance with the rising edge of the Q output. The latch circuit 98 latches the count value of the counter circuit 97 according to the high edge output. The pulse delayed by the delay circuit 103 is output as shown in FIG.

  At time t6, the count value of the counter circuit 97 is reset by the delay pulse 103 from the delay circuit 103 in FIG. A period from time t5 to t6 is a delay period T4 of a pulse output from the delay circuit 103.

  The switching circuit 83 performs switching so that the A input is output when the Q output is at a high level, and the B input is output when the Q output is at a low level. That is, switching to the A input by a signal from the delay circuit 101 and switching to the B input by a signal from the delay circuit 103.

  According to this modification, the same operational effects as the signal processing circuit shown in FIG.

  FIG. 6 shows a block diagram of a modification of the signal processing circuit shown in FIG. FIG. 7 shows a timing chart of the signal processing circuit shown in FIG. In the signal processing circuit shown in FIG. 6, the same components as those in FIG. The signal processing circuit of this modification is provided with a PLL circuit 105 and a delay circuit 104 in place of the high gate counter 90, the low gate counter 93, the gate circuits 91 and 94, and the RS flip-flop 92 as compared with the signal processing circuit of FIG. It is different in point. The PLL circuit 105 and the delay circuit 104 will be described below.

  The PLL circuit 105 includes a 90 ° phase comparison circuit 106, a VCO (Voltage Controlled Oscillator) 107, and a 1 / N-minute period 108. When the PLL input signal shown in FIG. 7A is supplied to the PLL circuit 105, the PLL output signal shown in FIG. 7B having a 90 ° phase difference from the period of the FM pulse signal is output. The 90 ° phase comparison circuit 106 compares the phases of the FM pulse signal and the output signal of the PLL circuit 105, and outputs the FM pulse signal so that the phase difference is 90 °. The FM pulse signal is supplied to the VCO 107. The VCO 107 generates a clock pulse having a predetermined frequency based on the supplied FM pulse signal. The generated clock pulse is supplied to the period 1 / N. In the 1 / N division period 108, the clock pulse from the VCO 107 is divided by a predetermined division ratio (1 / N), and an FM pulse signal having a phase difference of 90 ° is output. The FM pulse signal having a phase difference of 90 ° is supplied to the delay circuit 104, the high edge output circuit 99, the low edge output circuit 102, and the 90 ° phase comparison circuit.

  The delay circuit 104 delays the FM pulse signal supplied from the PLL 105 and supplies it to the switching circuit 78.

  Further, the count value of the counter circuit 95 is cleared by a pulse from the delay circuit 103. The latch circuit 96 latches the supplied count value of the counter circuit 95 with a pulse from the low edge output circuit 102.

  The count value of the counter circuit 97 is cleared by a pulse from the delay circuit 101. The latch circuit 98 latches the supplied count value of the counter circuit 97 with a pulse from the high edge output circuit 99.

  7A is an ideal PLL input signal (FM pulse signal), FIG. 7B is a PLL output signal, FIG. 7C is an actual FM pulse signal (input signal), and FIG. 7D is a clock pulse. 7E is an AND gate 87, FIG. 7F is an inverter 89, FIG. 7G is an AND gate 88, FIG. 7H is a high edge output, FIG. 7I is a delay pulse 101, FIG. (J) shows the low edge output, FIG. 7 (K) shows the delay pulse 103, and FIG. 7 (L) shows the delay pulse 104. Also, description of signals having the same timing as in FIG. 5 is omitted.

  When the actual input signal in FIG. 7C is supplied, the PLL circuit 105 outputs the PLL output signal in FIG.

  At time t1, a pulse is output from the high edge output circuit 99 as shown in FIG. 7H in response to the PLL output signal in FIG. In response to this pulse, the latch circuit 98 latches the count value of the counter circuit 97.

  At time t2, the counter circuit 97 is reset according to the pulse output from the delay pulse 101 in FIG. Thereafter, the counter circuit 97 again counts the clock pulses from the AND gate 87 shown in FIG.

  When the PLL output signal in FIG. 7B becomes a low level at time t3, a pulse is output from the low edge output circuit 102 in accordance with the fall of the PLL output signal as shown in FIG. 7J. In response to this pulse, the latch circuit 96 latches the count value of the counter circuit 95.

  At time t4, the counter circuit 95 is reset in accordance with the pulse output from the delay pulse 103 in FIG. After that, the counter circuit 95 again counts the clock pulses from the AND gate 88 shown in FIG.

  Similar operations are repeated at times t5 to t8.

  The counter circuit 97 counts clock pulses in the positive polarity period of the input signal in FIG. 7C during a period until the reset is performed by the pulse of the delay circuit 101 (for example, from time t2 to t6).

  The counter circuit 95 counts the clock pulses in the negative polarity period of the input signal in FIG. 7C during a period until the reset is performed by the pulse of the delay circuit 103 (for example, time t4 to t8).

The delay circuit 104 supplies a signal whose polarity is inverted at the timing of resetting each counter circuit to the switching circuit 78. The switching circuit 78 is switched so as to output the side on which the count value is latched by the signal from the delay circuit 104. In this embodiment, the count value of the latch circuit 98 is output when the output signal of the delay circuit 104 is positive, and the count value of the latch circuit 96 is output when the output signal is negative.
That is, the switching circuit 78 controls to output the count value latched at time t1 from the latch circuit 98 at the timing when the counter circuit 97 is reset at time t2. In addition, the switching circuit is controlled so that the count value latched at time t3 is output from the latch circuit 96 at the timing when the counter circuit 95 is reset at time t4.

  As described above, in this modification, the timing of counting the high and low periods is measured by generating a pulse whose phase is 90 ° different from that of the input signal by the PLL circuit. According to this modification, the count timing can be generated only by the PLL circuit, so that the circuit can be simplified compared to the signal processing circuit shown in FIG.

1 is a block diagram of an optical disc apparatus according to an embodiment of the present invention. It is a block diagram of the signal processing circuit of one Example of this invention. 4 shows a timing chart of the signal processing circuit of the present invention. The block diagram of the modification of the signal processing circuit shown in FIG. 2 is shown. 5 shows a timing chart of the signal processing circuit shown in FIG. FIG. 6 shows a block diagram of a modification of the signal processing circuit shown in FIG. 4. 7 is a timing chart of the signal processing circuit shown in FIG. An ideal timing chart in a conventional signal processing circuit is shown. The timing chart in the conventional ideal signal processing circuit is shown. An actual FM modulation signal and an enlarged view near zero level are shown. The timing chart in an actual signal processing circuit is shown. The timing chart for removing the conventional chattering is shown.

Explanation of symbols

10, 30, 31, 32 Signal processing circuit 11 Both-edge detection circuit 12 Counter circuit 13, 75, 76, 96, 98 Latch circuit 14 Digital LPF
15 FM modulation signal terminal 16 clock pulse terminal 17 digital FM signal terminal 40 disk 41 optical system 42 spindle motor 43 thread motor 44 laser driver 45 front monitor 46 ALPC
47 Memory Compensation Circuit 48 Wobble Signal Processing Unit 49 RF Amplifier 50 Focus / Tracking Servo Circuit 51 Feed Servo Circuit 52 Spindle Servo Circuit 53 CD Encode / Decode Circuit 54 D / A Converter 55 Audio Amplifier 56, 58 RAM
57 CD-ROM encode / decode circuit 59 Interface / buffer controller 60 CPU
61 Host computer 71 Positive polarity gate 72 Negative polarity positive gate 73, 97 Counter circuit (positive polarity)
74, 95 Counter circuit (negative polarity)
77, 92 RS flip-flop 78 switching circuit 79 digital LPF
80, 81, 82, 101, 103, 104 Delay circuit 83 OR gate 87, 88 AND gate 89 Inverter 90 High gate counter 93 Low gate counter 91, 94 Gate circuit 99 High edge output circuit 102 Low edge output circuit 100 Optical disk device 105 PLL circuit 106 90 ° phase comparison circuit 107 VCO
108 1 / N divider

Claims (7)

In a signal processing circuit that generates a digital signal according to an input pulse signal,
A phase difference pulse signal generating means for generating a phase difference pulse signal having a predetermined phase difference from the input pulse signal;
Setting means for setting a predetermined period including at least one pulse that allows a noise component in the input pulse signal based on the phase difference pulse signal generated by the phase difference pulse signal generation means;
A clock pulse output means for outputting a clock pulse with either polarity during the predetermined period set by the setting means ;
Counting means for independently counting the clock pulse output with a positive polarity and the clock pulse output with a negative polarity;
An output means for outputting an output digital signal based on the phase difference pulse signal generated by the phase difference pulse signal generation means and the count value of the count means. The clock pulse output means includes
First clock pulse output means for outputting a clock pulse when the input pulse signal is positive;
Second clock pulse output means for outputting a clock pulse when the input pulse signal is negative,
The counting means includes
First counting means for counting clock pulses from the first clock pulse output means;
2. The signal processing circuit according to claim 1, further comprising second counting means for counting clock pulses from said second clock pulse output means. The output means includes
Up edge output means for outputting a third timing signal in response to the up edge of the phase difference pulse signal;
Down edge output means for outputting a fourth timing signal in response to the down edge of the phase difference pulse signal;
First latch means for latching the count value of the first count means in response to the third timing signal;
3. The signal processing circuit according to claim 2, further comprising second latch means for latching a count value of the second count means in response to the fourth timing signal. The output means includes
First delay means for delaying the third timing signal and outputting a fifth timing signal;
Second delay means for delaying the fourth timing signal and outputting a sixth timing signal;
The first counting means is reset according to the fifth timing signal,
4. The signal processing circuit according to claim 3, wherein the second counting means is reset in accordance with the sixth timing signal. The output means includes
Third delay means for delaying the output of the phase difference pulse signal and outputting a delayed phase difference pulse signal,
Switching means for switching the output of the first count value latched by the first latch means and the second count value latched by the second latch means in accordance with the output of the delayed phase difference pulse signal 5. The signal processing circuit according to claim 3 or 4, The output means includes
6. The signal processing circuit according to claim 1, further comprising a digital low-pass filter. In a signal processing method for generating a digital signal corresponding to an input pulse signal,
A phase difference pulse signal generation procedure for generating a phase difference pulse signal having a predetermined phase difference from the input pulse signal;
A setting procedure for setting a predetermined period including at least one pulse that allows a noise component in the input pulse signal based on the phase difference pulse signal generated in the phase difference pulse signal generation procedure;
A clock pulse output procedure for outputting a clock pulse with either polarity during the predetermined period set in the setting procedure ;
A counting procedure for independently counting the clock pulse output with a positive polarity and the clock pulse output with a negative polarity;
An output procedure for outputting an output digital signal based on the phase difference pulse signal generated by the phase difference pulse procedure and the count value of the count procedure.

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