JP3790911B2 - Electronic endoscope device - Google Patents

Description

【００６４】
ここで、垂直方向の直線補間を行うためには、あるラインの映像信号を複数回読み出す必要がある。これはフレームメモリ４０から読み出した映像信号をラインメモリ４１，４２に格納し、これらを複数回読み出すことで対応している。２個のラインメモリのうち一方には奇数ラインの映像信号が、他方には偶数ラインの映像信号が書き込まれるようにＷＥ１信号，ＷＥ２信号によって書き込み制御され、同時にこれらの信号が読み出される。
【００６５】
垂直方向に拡大した後、水平方向に直線補間して拡大を行う。水平方向の直線補間後の映像信号Ｚ（ｍ，ｎ）は、以下の（２）式で表すことができる。

【００６６】
ここで、水平方向の直線補間を行うためには、ある画素の映像信号を複数回読み出す必要がある。これはフレームメモリ４０から映像信号を読み出す際に、ＲＥ１信号を制御して信号をホールドした状態のままラインメモリ４１，４２に書き込むことで実現している。
【００６７】
次いで演算回路４３の動作を説明する。ラインメモリ４１，４２から読み出された映像信号は演算回路４３に入力され、まず垂直拡大回路部において垂直方向の拡大処理が行われる。垂直方向及び水平方向の拡大を行う直線補間は、以下の（３）式で表すことができる。
Ｙ（ｍ，ｎ）＝α×Ｘ（ｉ，ｊ）＋β×Ｘ（ｋ，ｌ） …（３）
【００６８】
ここで、
α＋β＝１ …（４）
であるから、（３）式は以下のように変形できる。

【００６９】
拡大処理回路１７内の図示しない垂直カウンタの出力は、ＲＯＭで構成されたＶＫＲＯＭ４４に入力される。このＶＫＲＯＭ４４は、垂直カウンタの出力の垂直アドレスを参照アドレスとして、垂直方向のライン位置に応じて垂直補間係数αと、ラインメモリ４１，４２へ送るＷＥ１信号，ＷＥ２信号を生成するためのＷＥ信号及びラインメモリ４１，４２のどちらの出力が奇数ラインか偶数ラインかを判別するためのＡＢＳＥＬ信号とがテーブルとして書き込まれている。また、このＶＫＲＯＭ４４内には接続される内視鏡２に搭載されたＣＣＤ４の種類に応じて前記テーブルが複数書き込まれており、第１実施形態で述べたＣＣＤ判別結果に基づくＣＣＤセレクト信号により、これらのテーブルの選択が行われる。
【００７０】
演算回路４３内部では、ラインメモリ４１，４２から読み出された映像信号の減算処理（Ｘ（ｉ，ｊ）−Ｘ（ｋ，ｌ））が行われ、この減算結果はＶＲＯＭ５４に入力される。２つのラインメモリ出力のどちらをＸ（ｉ，ｊ），Ｘ（ｋ，ｌ）に当てはめるかはＡＢＳＥＬ信号によって選択実行される。ＶＲＯＭ５４には、ＶＫＲＯＭ４４から出力されるコード化された垂直補間係数αと映像信号の減算結果との乗算を行うテーブルが書き込まれている。ＶＲＯＭ５４の出力は、演算回路４３に戻され、時間合わせのため遅延されたＸ（ｋ，ｌ）と加算され垂直方向の拡大処理が行われる。
【００７１】
図１２に垂直拡大回路部のタイミングチャートを示す。ここでは垂直方向に４／３倍の拡大を行う場合を示している。
【００７２】
ＶＫＲＯＭ４４に入力される垂直アドレスに応じて、ＷＥ信号，ＡＢＳＥＬ信号が出力され、これらの信号を基にＷＥ１信号，ＷＥ２信号が生成される。このＷＥ１信号，ＷＥ２信号に応じてラインメモリ４１，４２に映像信号が書き込まれ、１ライン遅延した後に出力される。このラインメモリ４１，４２の出力信号を基に、垂直拡大回路部において上記数式で示される直線補間が行われる。
【００７３】
垂直拡大回路部において垂直方向に拡大された映像信号は、次いで水平拡大回路部において水平方向の拡大処理が行われる。
【００７４】
拡大処理回路１７内の図示しない水平カウンタの出力は、ＲＯＭで構成されたＨＫＲＯＭ４５に入力される。このＨＫＲＯＭ４５は、水平カウンタの出力の水平アドレスを参照アドレスとして、水平方向の画素の位置に応じて水平補間係数α′と、フレームメモリ４０へ送るＲＥ１信号を生成するためのＲＥ信号及び水平方向に映像信号をホールドするためのＣＥ信号とがテーブルとして書き込まれている。また、このＨＫＲＯＭ４５内には接続される内視鏡２に搭載されたＣＣＤ４の種類に応じて前記テーブルが複数書き込まれており、ＣＣＤ判別結果に基づくＣＣＤセレクト信号により、これらのテーブルの選択が行われる。
【００７５】
演算回路４３内部では、垂直方向拡大後の映像信号Ｙ（ｍ，ｎ）の減算処理（Ｙ（ｉ，ｊ）−Ｙ（ｋ，ｌ））が行われ、この減算結果はＨＲＯＭ７０に入力される。垂直方向拡大後の映像信号は、フレームメモリ４０から読み出される時点で、ある画素の信号はホールドされ複数回読み出された形になっている。この読み出しのタイミングに応じて、減算結果をＣＥ信号で更新する。ＨＲＯＭ７０には、ＨＫＲＯＭ４５から出力されるコード化された水平補間係数α′と映像信号の減算結果との乗算を行うテーブルが書き込まれている。ＨＲＯＭ７０の出力は、演算回路４３に戻され、時間合わせのため遅延されたＹ（ｋ，ｌ）と加算され水平方向の拡大処理が行われる。
【００７６】
図１３に水平拡大回路部のタイミングチャートを示す。ここでは水平方向に１３／１０倍の拡大を行う場合を示している。
【００７７】
ＨＫＲＯＭ４５に入力される水平アドレスに応じて、ＲＥ信号，ＣＥ信号が出力され、これらの信号とＡＢＳＥＬ信号を基にＲＥ１信号が生成される。このＲＥ１信号に応じてフィールドメモリ４０から映像信号が読み出され、ラインメモリ４１，４２で１ライン遅延した後に出力され、垂直拡大回路部により垂直方向に拡大された後に水平拡大回路部に送られる。またこの垂直方向に拡大された映像信号は、ＣＥ信号による出力イネーブル端子を持つＦＦ６５に送られる。前記垂直方向に拡大された映像信号とＣＥ信号により出力制御されるＦＦ６５の出力信号を基に、水平拡大回路部において上記数式で示される直線補間が行われる。
【００７８】
垂直方向及び水平方向の拡大処理を行う回路において、前記（３）式に示したＹ（ｍ，ｎ）＝α×Ｘ（ｉ，ｊ）＋β×Ｘ（ｋ，ｌ）による直線補間を行う場合、従来の構成では２種類の補間係数α及びβを発生させるための２種類のＲＯＭを設ける必要があった。また、α×Ｘ（ｉ，ｊ）とβ×Ｘ（ｋ，ｌ）の演算を行うための２種類のＲＯＭも必要となる。これに対して本実施形態の回路構成を持つ拡大処理回路では、補間係数αを発生させる１種類のＲＯＭと、α×（Ｘ（ｉ，ｊ）−Ｘ（ｋ，ｌ））の演算を行う１種類のＲＯＭとにより拡大処理が行うことができる。
【００７９】
従って、第３実施形態によれば、垂直方向及び水平方向の拡大処理を行う回路を配設した信号処理回路において、補間係数を発生させるＲＯＭ、あるいは演算を行うＲＯＭの個数を少なくすることが可能であり、回路規模の削減及びコストの低下を図ることが可能である。
【００８０】
［付記］
（１） 複数チャンネル読み出し型の固体撮像素子を備えた内視鏡を着脱自在に接続し、前記固体撮像素子で得られた映像信号の信号処理を行う信号処理回路を有する電子内視鏡装置において、
前記固体撮像素子より読み出された複数系統の映像信号をそれぞれデジタル信号に変換するＡ／Ｄ変換器と、
前記複数系統のデジタル映像信号の値をそれぞれ調整するレベル調整手段と、
前記複数系統のデジタル映像信号における所定要素の値に基づき前記レベル調整手段の調整量をそれぞれ独立に制御する制御手段と、
を備えたことを特徴とする電子内視鏡装置。
【００８１】
（２） 前記制御手段は、前記複数系統のデジタル映像信号における所定期間内のそれぞれの平均レベルに基づいて前記レベル調整手段の調整量を制御することを特徴とする付記１に記載の電子内視鏡装置。
【００８２】
（３） 前記レベル調整手段はホワイトバランス補正回路であることを特徴とする付記１に記載の電子内視鏡装置。
【００８３】
（４） 前記制御手段は、前記複数系統のデジタル映像信号における所定期間内のそれぞれの映像信号平均レベルよりレベル差補正係数を算出すると共に、前記各デジタル映像信号における所定期間内の各色成分の映像信号平均レベルよりホワイトバランス補正係数を算出し、これらのレベル差補正係数とホワイトバランス補正係数に基づいて前記ホワイトバランス補正回路の補正量を制御することを特徴とする付記３に記載の電子内視鏡装置。
【００８４】
（５） 前記レベル調整手段は色調調整回路であることを特徴とする付記１に記載の電子内視鏡装置。
【００８５】
（６） 前記レベル調整手段はＡＧＣ（オートゲインコントロール）回路であることを特徴とする付記１に記載の電子内視鏡装置。
【００８６】
（７） 映像信号を信号処理する信号処理回路において、
前記映像信号の画素位置に応じたアドレスを発生するアドレス発生回路と、
前記アドレスに応じて補間係数及び遅延制御信号を発生するＲＯＭと、
前記遅延制御信号に基づき前記映像信号を遅延させる遅延回路と、
前記遅延回路の出力と前記映像信号との差分を演算する減算回路と、
前記補間係数と前記減算回路の差分出力との乗算を行う乗算回路と、
前記乗算回路の出力と前記映像信号とを加算する加算回路と、を有してなり、
前記映像信号の画素の電子拡大処理を行う拡大処理回路を備えたことを特徴とする信号処理回路。
【００８７】
【発明の効果】
以上説明したように本発明によれば、補正のための回路を追加することなく、固体撮像素子の個体間及びチャンネル間のレベル差の補正を確実に行うことができ、かつ出力画像の画質劣化を防ぐことが可能となる効果がある。
【図面の簡単な説明】
【図１】本発明の第１実施形態に係る電子内視鏡装置の映像信号処理系の構成を示すブロック図
【図２】クランプ回路の動作波形を示す波形図
【図３】ＯＢクランプ回路の構成を示すブロック図
【図４】ＣＣＤにおけるＯＢ部のサブサンプリングを示す説明図
【図５】ＣＣＤにおける映像部のサブサンプリングを示す説明図
【図６】ＯＢクランプ回路の動作波形を示す波形図
【図７】第２実施形態に係るＣＣＵに設けられる発振回路の構成を示すブロック図
【図８】第２実施形態に係るＣＣＵに設けられる位相同期発振回路の構成を示すブロック図
【図９】第２実施形態に係る信号処理回路のローパスフィルタ周辺の部分構成を示すブロック図
【図１０】第３実施形態に係るＣＣＵ内の信号処理回路における拡大処理回路の構成を示すブロック図
【図１１】映像信号の拡大処理を説明する作用説明図
【図１２】垂直方向の拡大処理のタイミングチャート
【図１３】水平方向の拡大処理のタイミングチャート
【符号の説明】
２…内視鏡
３…カメラコントロールユニット（ＣＣＵ）
４…ＣＣＤ
５…スコープＩＤ回路
１０ａ，１０ｂ…ローパスフィルタ（ＬＰＦ）
１１ａ，１１ｂ…クランプ回路
１３ａ，１３ｂ…ＯＢクランプ回路
１４ａ，１４ｂ…デジタル乗算器
１５ａ，１５ｂ…ラインメモリ
１７…拡大処理回路
３４…ＣＰＵ
３６…ＯＢレベル平均手段
３７…データラッチ手段
３８…減算器
３９…映像レベル平均手段[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic endoscope apparatus including an imaging unit that drives a solid-state imaging device to perform photoelectric conversion of a subject image.
[0002]
[Prior art]
In recent years, an insertion part is inserted into an observation site such as a body cavity, an illumination light is transmitted by illumination light transmission means such as a light guide fiber bundle, and the observation site is irradiated from the distal end of the insertion unit to obtain an image of the observation site. Endoscope apparatuses for observing and treating an observation site are widely used.
[0003]
One of the endoscope apparatuses is provided with a solid-state image sensor, for example, a CCD at the distal end of the insertion portion, and an image of an observation site is formed on an imaging surface by an objective optical system and converted into an electrical signal. There is an electronic endoscope apparatus that can display an image of an observation site on a monitor or the like by processing a signal, or store it as image data in an information recording apparatus or the like.
[0004]
For example, in Japanese Patent Application No. 8-133631, the present applicant has proposed an electronic endoscope apparatus to which an endoscope having a two-line readout CCD can be connected. This two-line readout CCD has two horizontal transfer registers in order to lower the driving frequency, Odd-numbered signal charges in the horizontal direction and even-numbered signal charges in the horizontal direction Are transferred simultaneously in separate horizontal transfer registers, and two lines are transferred within one horizontal transfer period. Separate odd-numbered and even-numbered signal charges from the horizontal transfer register It is to read. In a CCD with this configuration, if there is a gain variation in an output system such as an FDA (floating diffusion amplifier) that converts signal charges into a voltage, the variation will occur. Output signal level difference variation between horizontal transfer registers, that is, odd and even output signal level difference variation End up. This output level difference appears as vertical stripes in the endoscopic image on the monitor, which causes image quality degradation.
[0005]
Therefore, in order to correct this output level difference, conventionally, a trimming resistor provided on the analog circuit is used to adjust the amplifier gain to correct the level variation. Further, the signal processing circuit performs a filter process for attenuating the repetition frequency of vertical stripes to eliminate the generation of vertical stripes.
[0006]
[Problems to be solved by the invention]
However, in the above-described conventional electronic endoscope apparatus, when the individual output variation occurs in the output level difference of the CCD, the output signal level difference occurs in the signal processing circuit. Further, when the signal processing circuit performs the filtering process, there is a problem in that the characteristic is deteriorated in the high frequency part of the frequency characteristic and the resolution of the output image is lowered.
[0007]
The present invention has been made in view of the above circumstances, and can reliably correct a level difference between individual solid-state image pickup devices and between channels without adding a circuit for correction, and an output image. An object of the present invention is to provide an electronic endoscope apparatus that can prevent image quality degradation.
[0008]
[Means for Solving the Problems]
An electronic endoscope apparatus according to the present invention Multiple In an electronic endoscope apparatus having a signal processing circuit for detachably connecting an endoscope including a channel readout type solid-state image pickup device and performing signal processing of a video signal obtained by the solid-state image pickup device. Read from the element Multiple An A / D converter for converting each system video signal into a digital signal; Multiple Level adjusting means for adjusting the value of each digital video signal of the system; Multiple Control means for independently controlling the amount of adjustment of the level adjusting means based on the value of a predetermined element in the digital video signal of the system.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
1 to 6 relate to a first embodiment of the present invention, FIG. 1 is a block diagram showing a configuration of a video signal processing system of an electronic endoscope apparatus, and FIG. 2 is a waveform diagram showing operation waveforms of a clamp circuit. 3 is a block diagram showing the configuration of the OB clamp circuit, FIG. 4 is an explanatory diagram showing sub-sampling of the OB portion in the CCD, FIG. 5 is an explanatory diagram showing sub-sampling of the video portion in the CCD, and FIG. 6 is an operation of the OB clamp circuit. It is a wave form diagram which shows a waveform.
[0010]
As shown in FIG. 1, an electronic endoscope apparatus 1 according to this embodiment includes an endoscope 2 that has a solid-state imaging device at its tip and observes the inside of a body cavity and the like, and an output signal from the endoscope 2 is electrically transmitted. A camera control unit (hereinafter referred to as CCU) 3 for processing and R, G, B plane sequential illumination light for illuminating the observation site are supplied to a light guide (not shown) provided in the endoscope 2. And a monitor (not shown) for displaying an image of a standard format television signal from the CCU 3.
[0011]
The endoscope 2 is detachably connected to the CCU 3 and has a CCD 4 as a solid-state imaging device at the tip thereof. The R, G, B planes are sequentially irradiated from the light source device to the observation site through the light guide. A subject image corresponding to the illumination light is converted into an electrical signal, and signals of R, G, and B color components are obtained.
[0012]
Further, the endoscope 2 is provided with a scope ID circuit 5 for outputting a scope ID signal for discriminating the scope type, and a scope ID signal corresponding to the type of the mounted CCD 4 is sent to the CCU 3. . There are a plurality of types of CCDs 4 having different numbers of pixels. In an electronic endoscope apparatus, a plurality of types of endoscopes 2 equipped with these types of CCDs 4 are connected to the CCU 3 and used.
[0013]
The scope ID circuit 5 is connected to a photocoupler 35 that transmits a signal between the patient circuit and the secondary circuit of the CCU 3 in an insulated state, and the scope ID signal from the scope ID circuit 5 is connected to the secondary circuit side via the photocoupler 35. To the CPU. The CPU 34 is connected to a ROM 33 and a ROM 27 on the patient circuit side via a photocoupler 29. The CPU 34 discriminates the type of CCD based on the scope ID signal, and sends the CCD discrimination signal to the ROM 33 on the secondary circuit side. To the ROM 27 on the patient circuit side.
[0014]
On the patient circuit side of the CCU 3, a ROM 27, a synchronization signal generation circuit (hereinafter referred to as SSG) 26, a crystal oscillator (hereinafter referred to as CXO) 28, a CCD drive circuit (DRV) 25 are provided, and an output of the SSG 26 Based on the above, a CCD drive signal corresponding to the type of the CCD 4 is generated by the CCD drive circuit 25. On the secondary circuit side, a ROM 33, SSG32, a variable crystal oscillator (hereinafter referred to as VCXO) 31, and a phase synchronization circuit (hereinafter referred to as PLL) 30 are provided, and in the PLL 30, the patient circuit side and the secondary circuit side are provided. Various timing signals for signal processing are generated by the SSG 32 in a phase-synchronized state.
[0015]
SSG 26 and SSG 32 are synchronization signal generation circuits composed of FPGAs (Field Programmable Gate Arrays). Each of the SSGs 26 and SSG 32 corresponds to the type of CCD depending on the program data of the FPGA in the ROM 27 and ROM 33 selected by the CCD discrimination signal from the CPU 34. Internal circuit wiring is defined.
[0016]
The SSG 26 generates a drive timing signal based on the clock from the CXO 28, and the CCD drive circuit 25 generates a CCD drive signal based on this drive timing signal and supplies it to the CCD 4. The SSG 32 generates various timing signals for signal processing by the clock from the VCXO 31 and supplies the timing signals to each circuit block on the secondary circuit side of the CCU 3.
[0017]
The CCD 4 arranged at the distal end of the endoscope 2 is Multiple systems such as Has two horizontal transfer registers Multiple channels eg This is a two-channel readout type that converts a subject image into an electrical signal based on a CCD drive signal and outputs horizontal odd-numbered pixels from one horizontal transfer register and even-numbered pixels from the other horizontal transfer register. . The two CCD output signals are processed by the same two signal processing circuits provided in the CCU 3. The CCD output signal is a signal of each color component obtained by the R, G, B field sequential illumination light, and the signal of each color component of R, G, B is sent to the CCU 3 in time series. .
[0018]
The CCU 3 includes preamplifiers 6a and 6b, amplifiers 8a and 8b, CDS circuits 9a and 9b, low-pass filters (LPF) 10a and 10b, clamp circuits 11a and 11b, an A / D converter 12a, as two signal processing circuits. 12b, OB clamp circuits 13a and 13b, digital multipliers 14a and 14b, and line memories 15a and 15b. The preamplifiers 6a and 6b on the patient circuit side and the amplifiers 8a and 8b on the secondary circuit side are isolated from the transformers 7a and 7b. It is insulated by.
[0019]
The two CCD output signals are amplified by the preamplifiers 6a and 6b on the patient circuit side, sent to the amplifiers 8a and 8b on the secondary circuit side via the isolation transformers 7a and 7b, and amplified. The output of one amplifier 8b is also sent to the PLL 30, and phase synchronization is applied between the clock generated by the VCXO 31 on the secondary circuit side and the clock generated by the CXO 28 on the patient circuit side. The outputs of the amplifiers 8a and 8b are converted into baseband bands by the CDS circuits 9a and 9b, and frequency components higher than the Nyquist frequency are removed by the low-pass filters 10a and 10b.
[0020]
The outputs of the low-pass filters 10a and 10b are analog clamped by the clamp circuits 11a and 11b, and then converted into digital video signals by the A / D converters 12a and 12b. The digital video signal is digitally clamped by the OB clamp circuits 13a and 13b, and the white balance correction of the video signal is performed based on the multiplication coefficient sent from the CPU 34 by the digital multipliers 14a and 14b as level adjusting means in the subsequent stage. The outputs of the digital multipliers 14a and 14b are simultaneously written into the line memories 15a and 15b and alternately read out, whereby the odd-numbered pixel horizontal transfer register output and the even-numbered pixel horizontal transfer in the two systems of digital video signals. The register outputs are rearranged in the original order and output as one system of digital video signals.
[0021]
Following the line memories 15a and 15b are an outline emphasis circuit 16, an enlargement processing circuit 17, a synchronization memory 18, a linear matrix circuit 19, a gamma (γ) correction circuit 20, a moving image memory 21, a still image memory 22, and a D / A. A converter 23 and a 75Ω drive circuit (75ΩDRV) 24 are provided, and are output to a monitor as a standard format television signal.
[0022]
The digital video signals output from the line memories 15a and 15b are subjected to contour component enhancement by the contour enhancement circuit 16, and an enlargement ratio corresponding to the size of the endoscopic image displayed on the monitor by the enlargement processing circuit 17. The electronic enlargement process is performed. In the synchronization memory 18, the frame sequential digital video signals of the R, G, and B color components output from the enlargement processing circuit 17 are written in time series, and are read out as the R, G, and B synchronization signals. The output of the synchronization memory 18 is color-converted by a linear matrix circuit 19 and gamma-corrected by a gamma correction circuit 20. The output of the gamma correction circuit 20 is sent to the D / A converter 23 through the moving image memory 21 and the still image memory 22 and converted into an analog video signal. The video signal converted into the analog R, G, B signal by the D / A converter 23 is impedance matched through the 75Ω drive circuit 24 and then sent to a monitor (not shown).
[0023]
Next, the operation of the main part of the electronic endoscope apparatus 1 of the present embodiment configured as described above will be described.
[0024]
FIG. 2 shows the state of operation waveforms of the clamp circuits 11a and 11b. In FIG. 2, the top and bottom of the reference voltage Vref are the top and bottom of the reference voltage of the A / D converters 12a and 12b in the subsequent stage. The analog clamp potential in the clamp circuits 11a and 11b is set higher than the bottom of the reference voltage of the A / D converters 12a and 12b as shown by the broken line in the figure. This clamp potential is the OB level of the video signal (the output level of the OB portion of the CCD). Therefore, the output signals of the low-pass filters 10a and 10b are clamped by the clamp circuits 11a and 11b to the clamp potential at which the OB level of the video signal is set.
[0025]
In general, the R, G, and B filters mounted on the rotary filter in the light source device have different transmittances for each color component, so that the CCD output signal has an amplitude for each of the R, G, and B color components as shown in FIG. Will cause a difference. The same applies to the case where a primary color subject is imaged. When the amplitude of each color component of such a CCD output signal is greatly different, the clamped OB level is affected by the signal amplitude of each color component, causing a shift.
[0026]
Therefore, in this embodiment, the average value of the OB level for each color is obtained by the OB clamp circuits 13a and 13b and digitally clamped, thereby eliminating the influence due to the variation in the amplitude of each color component.
[0027]
Outputs of the clamp circuits 11a and 11b are converted into digital signals by the A / D converters 12a and 12b and input to the OB clamp circuits 13a and 13b. As shown in FIG. 3, the OB clamp circuits 13a and 13b include an OB level averaging means 36, a data latch means 37, a subtractor 38, and a video level averaging means 39.
[0028]
In the OB clamp circuits 13a and 13b, first, in the OB level averaging means 36, as shown in FIG. 4, the period of the OB portion of the digital video signal is sub-sampled, and the OB level average value for one screen is calculated for each color. . In the case of a CCD of 100 pixels (H) × 100 pixels (V): video portion and 10 pixels (H) × 100 pixels (V): OB portion as in the example of FIG. 4, half the horizontal direction for each channel There is an output of the number of pixels. Here, the output of the OB portion is subsampled by 4 pixels (H) × 64 pixels (V), and the OB level is added and averaged for each color.
[0029]
Next, the data latch means 37 holds the calculated OB level average value for each color until the next frame sequential signal of the same color component is input to the OB clamp circuits 13a and 13b based on the latch timing signal. 38, the OB level average value held by the data latch means 37 is subtracted from the inputted same color component frame sequential signal after one cycle.
[0030]
At this time, the OB level for each color component coincides with the bottom of the reference voltage of the A / D converters 12a and 12b, and digital clamping is performed at this OB level. As a result, it is possible to perform clamping that is not affected by variations in the amplitude of each color component of the video signal.
[0031]
FIG. 6 shows operation waveforms of the OB clamp circuits 13a and 13b. In FIG. 6, the input signal and output signal of the OB clamp circuit are expressed in analog form. The OB level averaging means 36 obtains the average value of the OB level for each color of the input signal, the data latch means 37 holds the OB level average value for one period of each color component output, and the subtractor 38 holds the same color component after one period. By subtracting the output of the data latch means 37 from the frame sequential signal, digital clamping is performed at the OB level that coincides with the bottom of the reference voltage of the A / D converters 12a and 12b, and the subsequent digital signal is output as the output signal. It is sent to the multipliers 14a and 14b.
[0032]
Further, in the video level averaging means 39, as shown in FIG. 5, the period of the video portion of the output of the subtractor 38 (video signal after clamping) is subsampled, and the average value of the video signal for one screen is obtained for each color. calculate. In the example of FIG. 5, the output of the video section is subsampled by 64 pixels (H) × 64 pixels (V), and the video signal level is averaged for each color. The average value of the video signal is sent to the CPU 34 in time series for each color of R, G, and B.
[0033]
When a white balance correction command is issued to the CPU 34 by an operation switch or the like (not shown), the CPU 34 calculates the average values of the two R, G, and B video signals sent in time series from the OB clamp circuits 13a and 13b. For example, averaging is performed every 8 periods, and the ratio of the reciprocal of the average value of each color is calculated to determine the white balance correction coefficient for each system. Further, the ratio of the reciprocal of the average video signal value of the G signal calculated from the output of the OB clamp circuit 13a and the average video signal value of the G signal calculated from the output of the OB clamp circuit 13b is obtained, and the level difference between the channels is corrected. A level difference correction coefficient for determining the level difference is determined.
[0034]
The outputs of the OB clamp circuits 13a and 13b are input to digital multipliers 14a and 14b, respectively, where multiplication processing for white balance correction and inter-channel level difference correction is performed. The digital multipliers 14a and 14b are given multiplication coefficients based on the white balance correction coefficient and the level difference correction coefficient obtained by the CPU 34. At this time, the white multiplier correction coefficient calculated based on the average value of the video signal output from the OB clamp circuit 13a is given to the digital multiplier 14a as a multiplication coefficient, and the OB clamp circuit 13b is supplied to the digital multiplier 14b. A value obtained by multiplying the white balance correction coefficient calculated based on the average video signal value output from the video signal by the level difference correction coefficient calculated from the two video signal average values is given as a multiplication coefficient.
[0035]
In this way, by performing multiplication processing with the multiplication coefficients in the digital multipliers 14a and 14b, white balance correction is performed according to the average value for each color component of the two systems of video signals, and at the same time, between channels. It is possible to correct variations in the output level of the video signal.
[0036]
In the present embodiment, at the time of white balance correction that is always performed every time the endoscope is replaced, the video signal average level within a predetermined period of each channel output of the 2-channel readout CCD is calculated, and the video signal average level of one channel is calculated. A level difference correction coefficient is obtained so as to match the average video signal level of the other channel. At the same time, the video signal average level of each color component of R, G, B for each channel is calculated, and a white balance correction coefficient for performing white balance correction is obtained from this result. Of the two level adjustment means for performing white balance correction, one of the level adjustment means has a white balance correction coefficient calculated from the average video signal level of one channel, and the other level adjustment means has the white balance correction coefficient of the other channel. The white balance correction coefficient calculated from the average video signal level is multiplied by the level difference correction coefficient. Thereby, white balance correction is performed and level difference correction between both channels is performed at the same time.
[0037]
During an endoscopic examination, a treatment tool may be treated by extending a metal treatment tool from the distal end of the endoscope or laser irradiation may be performed. In such a scene, that is, when an image in which excessive reflected light is present on the screen or an image in which spot-like bright spots are present on the screen is captured, the difference in the amount of light input between the pixels is large. There is a difference in the amount of charge transferred to the output stage of the system CCD. If the level difference correction coefficient is obtained under such circumstances, the average level of the video signal may be biased and an accurate correction coefficient may not be obtained. Further, when the amount of illumination light is insufficient, the calculation error at the time of calculating the correction coefficient becomes large, and the inter-channel level difference correction cannot be performed with sufficient accuracy.
[0038]
On the other hand, white balance correction involves inserting the tip of an endoscope into a white balance correction tube with a white interior and capturing an image with uniform brightness under the appropriate illumination light quantity. Since the processing is performed based on the obtained video signal, the average level of the video signal within a predetermined period of each of the two channels is almost the same. Therefore, in the present embodiment, at the time of white balance correction, the white balance correction coefficient is obtained and at the same time the level difference correction coefficient is obtained to correct the variation in the output level of the video signal between channels.
[0039]
As described above, according to the first embodiment, the white balance correction is performed at the same time as the output level difference between the channels is corrected. There is no need to add a circuit for correcting the output level difference, the output level can be corrected reliably, and the image quality can be improved. In addition, stable and accurate correction can be performed by using two systems of outputs at the time of relatively stable white balance correction of the video signal.
[0040]
As an application example of this embodiment, output level difference correction may be performed using a digital multiplier used in an AGC (auto gain control) circuit or a color tone adjustment circuit instead of a digital multiplier that performs white balance correction. good.
[0041]
FIGS. 7 to 9 relate to a second embodiment of the present invention, FIG. 7 is a block diagram showing a configuration of an oscillation circuit provided in the CCU, and FIG. 8 is a block diagram showing a configuration of a phase-locked oscillation circuit provided in the CCU. FIG. 9 is a block diagram showing a partial configuration around the low-pass filter of the signal processing circuit.
[0042]
In the second embodiment, in the CCU of the first embodiment shown in FIG. 1, the configuration of the part that switches the circuit characteristics according to the type of CCD is changed. Specifically, modifications of the CXO 28, PLL 30 and VCXO 31, and low-pass filters 10a and 10b in FIG. 1 are shown in FIGS. Since other parts are the same as those in the first embodiment, the description of the configuration and operation is omitted.
[0043]
As described above, there are a plurality of types of CCDs 4 arranged at the distal end of the endoscope 2 depending on the number of pixels. A drive signal and a drive frequency are different between a CCD having a normal number of pixels and a CCD having a large number of pixels for high resolution. Similar to the first embodiment, the type of the CCD 4 mounted by the CPU 34 is determined according to the scope ID signal output from the scope ID circuit 5 provided in the endoscope, and in the CCU 3 according to the determination result. The circuit characteristics are switched.
[0044]
FIG. 7 shows the configuration of an oscillation circuit that can replace the CXO 28. The oscillation circuit 101 includes a CXO 102 that outputs a clock having a driving frequency for a CCD having a normal number of pixels and a CXO 103 that outputs a clock having a driving frequency for a CCD having a large number of pixels. Regulators 104 and 105 each having an output enable terminal are connected to the power supply terminals. The output ends of the CXOs 102 and 103 are connected to the selector 106, and the output of the selector 106 is supplied to the SSG 26.
[0045]
Depending on the CCD discrimination result from the CPU 34, the selector 106 selects one of the outputs of the CXOs 102 and 103 as appropriate, and a driving clock suitable for the number of pixels of the CCD is sent to the SSG 26. At this time, a control signal is sent to the output enable terminals of the regulators 104 and 105 based on the CCD discrimination result, and the oscillation output of the CXO whose output is not selected is stopped.
[0046]
FIG. 8 shows a configuration of a phase-locked oscillation circuit that replaces the PLL 30 and the VCXO 31. In order to extract the fundamental wave component of the driving frequency from the CCD output signal, the phase-locked oscillation circuit 108 and a band-pass filter (BPF) 109 for the CCD driving frequency having the normal number of pixels and a band for the CCD driving frequency having a large number of pixels are used. A pass filter 110, and the output ends of these band pass filters 109 and 110 are connected to the selector 111. A phase comparator 112 and a low-pass filter 113 are connected in order to the output terminal of the selector 111. A VCXO 114 that generates a clock CLK1 having the same frequency as the drive frequency of the CCD having the number of normal pixels and a multi-pixel are connected to the subsequent stage of the low-pass filter 113. A VCXO 115 that generates a clock CLK2 having the same frequency as the drive frequency of several CCDs is provided in parallel. The output terminals of the VCXOs 114 and 115 are connected to the selector 116, and the output of the selector 116 is supplied to the SSG 32 and fed back to the phase comparator 112.
[0047]
Depending on the CCD discrimination result from the CPU 34, the selector 111 selects one of the outputs of the band pass filters 109 and 110 as appropriate, and the fundamental component of the drive frequency that matches the number of pixels of the CCD is one of the phase comparators 112. Sent to the input terminal. Further, the selector 116 appropriately selects the output of the VCXO 114 or 115 according to the CCD discrimination result, and a clock having the same frequency as the drive frequency suitable for the number of pixels of the CCD is sent to the SSG 32 and the phase comparator 112 Feedback is provided to the other input terminal.
[0048]
FIG. 9 shows a partial configuration of a signal processing circuit provided with a plurality of low-pass filters instead of the low-pass filters 10a and 10b. In the signal processing circuit of the CCU 3, a low-pass filter 118 for a CCD having a normal number of pixels and a low-pass filter 119 for a CCD having a large number of pixels are provided after the CDS circuits 9a and 9b. The output terminals 118 and 119 are connected to the selector 120, and the output terminal of the selector 120 is connected to the clamp circuits 11a and 11b.
[0049]
Depending on the difference between the CCD drive frequency switched according to the CCD discrimination result from the CPU 34 and the sampling frequency of the A / D converters 12a, 12b, the selector 120 selects the output of the low-pass filters 118, 119 as appropriate. Filter processing corresponding to the drive frequency and Nyquist frequency suitable for the number of pixels is performed.
[0050]
Therefore, according to the second embodiment, it is possible to minimize the configuration for switching the circuit characteristics when using an endoscope in which different types of CCDs are mounted. Moreover, EMC performance such as unnecessary radiation can be improved by stopping the oscillation of the unused CXO among the plurality of CXOs arranged in the patient circuit floating with respect to the ground potential. .
[0051]
The switching operation of the circuit characteristics in the second embodiment or the definition of the internal circuit of the synchronization signal generating circuit configured by the FPGA in the first embodiment is such that different CCD discrimination results are detected by chattering when the endoscope is attached / detached. In order to prevent the possibility of erroneous switching of circuit characteristics and erroneous definition of the internal circuit of the FPGA, switching of circuit characteristics based on the CCD determination result, for example, after a sufficient time has elapsed after the CCD determination result is determined It is desirable to define the internal circuit of the FPGA.
[0052]
FIGS. 10 to 13 relate to a third embodiment of the present invention, FIG. 10 is a block diagram showing the configuration of the enlargement processing circuit in the signal processing circuit in the CCU, and FIG. 11 is an operation explanatory view for explaining the enlargement processing of the video signal. 12 is a timing chart of the vertical enlargement process, and FIG. 13 is a timing chart of the horizontal enlargement process.
[0053]
The third embodiment shows the configuration and operation of the enlargement processing circuit 17 in the signal processing circuit in the CCU of the first embodiment shown in FIG.
[0054]
The video signal output from the contour emphasizing circuit 16 is written into a frame memory 40 provided at the input stage of the enlargement processing circuit 17. In the frame memory 40, the video signal is intermittently read according to the enlargement ratio by the RE1 signal described later. The video signals read from the frame memory 40 are sorted and stored for each line in the later-stage line memories 41 and 42 according to WE1 and WE2 signals described later. The outputs of the line memories 41 and 42 are input to an arithmetic circuit 43 constituted by an FPGA.
[0055]
The enlargement processing circuit 17 includes a horizontal counter and a vertical counter (not shown). The vertical address of the vertical counter output is input to the VKROM 44 composed of ROM, and the horizontal address of the horizontal counter output is input to the HKROM 45 composed of the same ROM, and the WE signal and ABSEL signal are generated in the VKROM 44 according to the vertical address. In response to the address, the HKROM 45 generates and outputs an RE signal and a CE signal. Based on these signals, the WE signal, the ABSEL signal, and the RE signal are generated by the flip-flop and logic circuit in the arithmetic circuit 43 to generate the RE1, WE1, and WE2 signals, and the CE signal is used as a control signal in the arithmetic circuit 43. Used.
[0056]
The two video signals read out from the line memories 41 and 42 are input to the arithmetic circuit 43, passed through internal flip-flops (hereinafter referred to as FFs) 46 and 47, and then the ABSEL also passed through the FF 48. Depending on the signal, the signal is selectively input to either the A terminal or the B terminal of the subtractor 49 composed of an inverter and an adder. The output result (B-A) signal and the carry code of the subtractor 49 are temporarily output from the arithmetic circuit 43 via the FFs 50 and 51, respectively.
[0057]
The VKROM 44 outputs a WE signal and an ABSEL signal and a vertical coefficient address VC. The vertical coefficient address VC and the (B-A) signal output from the arithmetic circuit 43 are multiplied by the VROM 54 constituted by the ROM via the FFs 52 and 53, respectively, and pass through the FF 55 and the FF 56 in the arithmetic circuit 43. And input to one input terminal of the adder 57. Further, the B terminal input signal of the subtractor 49 is input to the other input terminal of the adder 57 via the time adjustment FFs 58 to 61.
[0058]
The output of the adder 57 is input to the FF 62, and the signal output from the FF 62 is input to the D terminal of the subtractor 63 configured by an inverter and an adder. The signal output from the FF 62 is appropriately held by the FF 65 having an output enable terminal based on the CE signal via the FF 64 and input to the C terminal of the subtractor 63. The output result (DC) signal and carry code of the subtracter 63 are temporarily output from the arithmetic circuit 43 via the FFs 66 and 67, respectively.
[0059]
The HKROM 45 outputs the RE signal and the CE signal and also outputs the horizontal coefficient address HC. The horizontal coefficient address HC and the (DC) signal output from the arithmetic circuit 43 are multiplied by the HROM 70 constituted by the ROM via the FFs 68 and 69, respectively, and pass through the FF 71 and the FF 72 in the arithmetic circuit 43. And input to one input terminal of the adder 73. Also, the C terminal input signal of the subtracter 63 is input to the other input terminal of the adder 73 via the time adjustment FFs 74 to 77. The output of the adder 73 is output from the computing unit 43 via the FF 78 and sent to the synchronization memory 18.
[0060]
The WE signal, ABSEL signal, and RE signal output from the VKROM 44 and HKROM 45 pass through the FFs 48, 79, and 80 in the arithmetic circuit 43, and then undergo logical operations by the logic circuit. The logical operation results are respectively obtained as the RE1 signal and WE1. Signals and WE2 signals are output from the FFs 81, 82, and 83.
[0061]
Next, the operation of the memory unit at the input stage of the enlargement processing circuit 17 configured as described above will be described. The video signals stored in the frame memory 40 are sequentially read from the frame memory 40 in response to the RE1 signal. The read video signal is distributed to the line memories 41 and 42 according to the WE1 signal and the WE2 signal, and sent to the subsequent vertical enlargement circuit unit in a pattern corresponding to the enlargement ratio.
[0062]
Here, the video signal read from the line memories 41 and 42 will be described. For the sake of simplicity, a case where a video signal of 4 pixels (H) × 4 pixels (V) is enlarged to 5 pixels (H) × 5 pixels (V) will be described. In this embodiment, linear interpolation is performed as enlargement processing. As shown in FIG. 11, linear interpolation is performed in the vertical direction and converted to 4 pixels (H) × 5 pixels (V), and then linear interpolation is performed in the horizontal direction. To enlarge to 5 pixels (H) × 5 pixels (V).
[0063]
The video signal Y (m, n) after the linear interpolation in the vertical direction can be expressed by the following equation (1).

[0064]
Here, in order to perform vertical linear interpolation, it is necessary to read a video signal of a certain line a plurality of times. This is dealt with by storing the video signals read from the frame memory 40 in the line memories 41 and 42 and reading them out a plurality of times. Writing is controlled by the WE1 and WE2 signals so that an odd line video signal is written in one of the two line memories and an even line video signal is written in the other, and these signals are read out simultaneously.
[0065]
After enlarging in the vertical direction, enlargement is performed by linear interpolation in the horizontal direction. The video signal Z (m, n) after horizontal linear interpolation can be expressed by the following equation (2).

[0066]
Here, in order to perform horizontal linear interpolation, it is necessary to read a video signal of a certain pixel a plurality of times. This is achieved by reading the video signal from the frame memory 40 and writing it to the line memories 41 and 42 while controlling the RE1 signal and holding the signal.
[0067]
Next, the operation of the arithmetic circuit 43 will be described. The video signals read from the line memories 41 and 42 are input to the arithmetic circuit 43, and first, vertical enlargement processing is performed in the vertical enlargement circuit unit. Linear interpolation for performing vertical and horizontal enlargement can be expressed by the following equation (3).
Y (m, n) = α × X (i, j) + β × X (k, l) (3)
[0068]
here,
α + β = 1 (4)
Therefore, the equation (3) can be modified as follows.

[0069]
The output of a vertical counter (not shown) in the enlargement processing circuit 17 is input to a VKROM 44 constituted by a ROM. The VKROM 44 uses a vertical address output from the vertical counter as a reference address, a WE signal for generating a vertical interpolation coefficient α according to the vertical line position, a WE1 signal and a WE2 signal to be sent to the line memories 41 and 42, and An ABSEL signal for determining which output of the line memories 41 and 42 is an odd line or an even line is written as a table. In addition, a plurality of the tables are written in the VKROM 44 according to the type of the CCD 4 mounted on the endoscope 2 to be connected. By the CCD select signal based on the CCD discrimination result described in the first embodiment, These tables are selected.
[0070]
In the arithmetic circuit 43, a subtraction process (X (i, j) -X (k, l)) of the video signal read from the line memories 41 and 42 is performed, and the subtraction result is input to the VROM 54. Which of the two line memory outputs is applied to X (i, j) and X (k, l) is selected and executed by the ABSEL signal. In the VROM 54, a table for multiplying the coded vertical interpolation coefficient α output from the VKROM 44 and the subtraction result of the video signal is written. The output of the VROM 54 is returned to the arithmetic circuit 43 and added with X (k, l) delayed for time adjustment, and the vertical enlargement process is performed.
[0071]
FIG. 12 shows a timing chart of the vertical enlargement circuit unit. Here, a case where enlargement of 4/3 times is performed in the vertical direction is shown.
[0072]
The WE signal and the ABSEL signal are output according to the vertical address input to the VKROM 44, and the WE1 signal and the WE2 signal are generated based on these signals. A video signal is written in the line memories 41 and 42 in accordance with the WE1 and WE2 signals, and is output after being delayed by one line. Based on the output signals of the line memories 41 and 42, linear interpolation shown by the above formula is performed in the vertical enlargement circuit unit.
[0073]
The video signal enlarged in the vertical direction in the vertical enlargement circuit unit is then subjected to horizontal enlargement processing in the horizontal enlargement circuit unit.
[0074]
An output of a horizontal counter (not shown) in the enlargement processing circuit 17 is input to an HKROM 45 constituted by a ROM. This HKROM 45 uses the horizontal address of the output of the horizontal counter as a reference address, the horizontal interpolation coefficient α ′ according to the position of the pixel in the horizontal direction, the RE signal for generating the RE1 signal to be sent to the frame memory 40, and the horizontal direction. CE signals for holding video signals are written as a table. Further, a plurality of the tables are written in the HKROM 45 in accordance with the type of the CCD 4 mounted on the endoscope 2 connected thereto, and these tables are selected by a CCD select signal based on the CCD discrimination result. Is called.
[0075]
In the arithmetic circuit 43, the subtraction process (Y (i, j) -Y (k, l)) of the video signal Y (m, n) after the vertical expansion is performed, and this subtraction result is input to the HROM 70. . When the video signal after the vertical enlargement is read from the frame memory 40, the signal of a certain pixel is held and read out a plurality of times. The subtraction result is updated with the CE signal in accordance with the read timing. In the HROM 70, a table for multiplying the coded horizontal interpolation coefficient α ′ output from the HKROM 45 and the subtraction result of the video signal is written. The output of the HROM 70 is returned to the arithmetic circuit 43 and added with Y (k, l) delayed for time adjustment to perform horizontal enlargement processing.
[0076]
FIG. 13 shows a timing chart of the horizontal enlargement circuit unit. Here, a case where 13/10 magnification is performed in the horizontal direction is shown.
[0077]
The RE signal and the CE signal are output according to the horizontal address input to the HKROM 45, and the RE1 signal is generated based on these signals and the ABSEL signal. In response to the RE1 signal, a video signal is read from the field memory 40, output after being delayed by one line in the line memories 41 and 42, enlarged in the vertical direction by the vertical enlargement circuit, and then sent to the horizontal enlargement circuit. . The video signal expanded in the vertical direction is sent to the FF 65 having an output enable terminal for the CE signal. On the basis of the video signal expanded in the vertical direction and the output signal of the FF 65 that is output-controlled by the CE signal, linear interpolation represented by the above equation is performed in the horizontal enlargement circuit unit.
[0078]
When performing linear interpolation by Y (m, n) = α × X (i, j) + β × X (k, l) shown in the above equation (3) in a circuit that performs vertical and horizontal enlargement processing In the conventional configuration, it is necessary to provide two types of ROMs for generating two types of interpolation coefficients α and β. In addition, two types of ROMs are required for performing the calculation of α × X (i, j) and β × X (k, l). On the other hand, in the enlargement processing circuit having the circuit configuration of this embodiment, one kind of ROM that generates the interpolation coefficient α and the calculation of α × (X (i, j) −X (k, l)) are performed. Enlarging processing can be performed with one type of ROM.
[0079]
Therefore, according to the third embodiment, it is possible to reduce the number of ROMs that generate interpolation coefficients or ROMs that perform computations in a signal processing circuit provided with circuits that perform vertical and horizontal enlargement processing. Therefore, it is possible to reduce the circuit scale and the cost.
[0080]
[Appendix]
(1) Multiple In an electronic endoscope apparatus having a signal processing circuit for detachably connecting an endoscope having a channel readout type solid-state imaging device and performing signal processing of a video signal obtained by the solid-state imaging device,
Read from the solid-state image sensor Multiple An A / D converter that converts each video signal of the system into a digital signal;
Said Multiple Level adjusting means for adjusting the values of the digital video signals of the system,
Said Multiple Control means for independently controlling the amount of adjustment of the level adjusting means based on the value of a predetermined element in the digital video signal of the system;
An electronic endoscope apparatus comprising:
[0081]
(2) The control means includes the Multiple The electronic endoscope apparatus according to appendix 1, wherein an adjustment amount of the level adjusting unit is controlled based on an average level in a predetermined period in a digital video signal of a system.
[0082]
(3) The electronic endoscope apparatus according to appendix 1, wherein the level adjusting means is a white balance correction circuit.
[0083]
(4) The control means includes the Multiple The level difference correction coefficient is calculated from the average level of each video signal within a predetermined period in the digital video signal of the system, and the white balance correction coefficient is calculated from the average level of the video signal of each color component within the predetermined period of each digital video signal. The electronic endoscope apparatus according to appendix 3, wherein a correction amount of the white balance correction circuit is controlled based on the level difference correction coefficient and the white balance correction coefficient.
[0084]
(5) The electronic endoscope apparatus according to appendix 1, wherein the level adjusting means is a color tone adjusting circuit.
[0085]
(6) The electronic endoscope apparatus according to appendix 1, wherein the level adjusting means is an AGC (auto gain control) circuit.
[0086]
(7) In a signal processing circuit for processing video signals,
An address generation circuit for generating an address corresponding to a pixel position of the video signal;
A ROM for generating an interpolation coefficient and a delay control signal according to the address;
A delay circuit for delaying the video signal based on the delay control signal;
A subtraction circuit for calculating a difference between the output of the delay circuit and the video signal;
A multiplication circuit for multiplying the interpolation coefficient by the difference output of the subtraction circuit;
An adder circuit for adding the output of the multiplier circuit and the video signal;
A signal processing circuit comprising: an enlargement processing circuit that performs electronic enlargement processing of pixels of the video signal.
[0087]
【The invention's effect】
As described above, according to the present invention, it is possible to reliably perform the correction of the level difference between the individual solid-state image pickup devices and between the channels without adding a correction circuit, and to deteriorate the image quality of the output image. There is an effect that can be prevented.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a video signal processing system of an electronic endoscope apparatus according to a first embodiment of the present invention.
FIG. 2 is a waveform diagram showing an operation waveform of a clamp circuit.
FIG. 3 is a block diagram showing a configuration of an OB clamp circuit.
FIG. 4 is an explanatory diagram showing sub-sampling of an OB portion in a CCD.
FIG. 5 is an explanatory diagram showing sub-sampling of a video part in a CCD.
FIG. 6 is a waveform diagram showing operation waveforms of the OB clamp circuit.
FIG. 7 is a block diagram showing a configuration of an oscillation circuit provided in the CCU according to the second embodiment.
FIG. 8 is a block diagram showing a configuration of a phase-locked oscillation circuit provided in the CCU according to the second embodiment.
FIG. 9 is a block diagram showing a partial configuration around a low-pass filter of a signal processing circuit according to a second embodiment.
FIG. 10 is a block diagram showing a configuration of an enlargement processing circuit in a signal processing circuit in a CCU according to a third embodiment.
FIG. 11 is an operation explanatory diagram illustrating video signal enlargement processing;
FIG. 12 is a timing chart of the vertical enlargement process
FIG. 13 is a timing chart of horizontal enlargement processing;
[Explanation of symbols]
2. Endoscope
3 ... Camera Control Unit (CCU)
4 ... CCD
5. Scope ID circuit
10a, 10b ... Low pass filter (LPF)
11a, 11b ... Clamp circuit
13a, 13b ... OB clamp circuit
14a, 14b ... Digital multiplier
15a, 15b ... line memory
17 ... Expansion processing circuit
34 ... CPU
36 ... OB level averaging means
37. Data latch means
38 ... Subtractor
39 ... Meaning of video level

Claims (1)

In an electronic endoscope apparatus having a signal processing circuit for detachably connecting an endoscope provided with a solid-state imaging device of a multi-channel readout type and performing signal processing of a video signal obtained by the solid-state imaging device,
An A / D converter for converting a plurality of video signals read from the solid-state imaging device into digital signals,
Level adjusting means for adjusting the values of the digital video signals of the plurality of systems,
Control means for independently controlling the amount of adjustment of the level adjusting means based on the value of a predetermined element in the digital video signals of the plurality of systems ,
The level adjusting means includes a white balance correction circuit,
The control means calculates a level difference correction coefficient from each video signal average level in a first predetermined period in the digital video signals of the plurality of systems, and each color in the second predetermined period in each digital video signal. An electronic endoscope characterized in that a white balance correction coefficient is calculated from an average video signal level of a component, and a correction amount of the white balance correction circuit is controlled based on the level difference correction coefficient and the white balance correction coefficient. apparatus.

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