JP3745605B2 - Electronic still camera - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic still camera that records a still image captured by a solid-state imaging device on a recording medium such as a semiconductor memory.
[0002]
[Prior art]
The spread of personal computers to ordinary homes is remarkable, and along with this, electronic still cameras are also becoming popular. This electronic still camera performs information compression coding processing on still images captured using a solid-state image sensor to reduce the amount of data, and compresses still images compressed on a semiconductor recording medium such as an SSFDC (Solid State Floppy Disk Card). The recorded still image can be displayed on a monitor of a personal computer or printed by a home printer. The number of pixels of a still image that can be captured by this electronic still camera is increasing year by year assuming printing by a printer.
[0003]
[Problems to be solved by the invention]
However, increasing the number of pixels in this way places a heavy burden on the internal signal processing circuit. In other words, if the number of pixels increases, the signal processing will take a long time, so the interval between still image captures will increase, or the interval from when the still image is captured until the next operation will be increased. There was a problem of doing.
[0004]
Further, in an electronic still camera, a line buffer for signal processing is generally provided and data is stored and processed for each line. However, when the number of pixels is increased, the number of pixels per line also increases. Therefore, it is necessary to mount a larger line buffer, which leads to an increase in circuit scale.
[0005]
Recently, some still images can be output not only to personal computer monitors, but also to television receivers. However, when outputting to television receivers, the number of pixels has been greatly reduced. Since the image is output, there is a problem that the image cannot be displayed with the original image quality of the still image.
[0006]
In view of these problems, the electronic still camera according to the present invention aims to speed up a signal processing circuit without using a large-capacity line buffer, and further, still image quality inherent in a still image is maintained. It is an object of the present invention to be able to output this still image to a television receiver.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides an electronic still camera having the following configuration.
An electronic still comprising an image pickup device, an A / D converter, a memory, a signal processor, a memory write buffer, a memory read buffer, and an HD read buffer A camera,
The image sensor converts incoming subject light into an electrical signal in the form of an analog signal and outputs it to the A / D converter,
The A / D converter converts an electrical signal output from the image sensor into a digital signal and outputs the digital signal to the signal processor,
When the memory transfers data in parallel in a time-sharing manner between the memory write buffer unit, the memory read buffer unit, and the HD read buffer unit, the memory has a predetermined frequency. Using a first clock having
The signal processing unit performs a predetermined signal processing on the digital signal supplied from the A / D conversion unit and outputs the digital signal to the memory writing buffer unit. When performing a predetermined signal processing and outputting, each is performed using a second clock having a frequency lower than the frequency of the first clock,
The input / output control unit has a capacity smaller than a data amount of data for one horizontal line in the image sensor, the memory write buffer unit, the memory read buffer unit, and a high-definition video signal. Each of which has an HD reading buffer section to read,
When transferring data between the memory write buffer unit, the memory read buffer unit, and the HD read buffer unit, and the memory, the first clock is used,
When transferring data between each of the memory write buffer unit and the memory read buffer unit and the signal processing unit, the second clock is used,
When data is read from the HD read buffer unit, the first clock having a frequency lower than the frequency of the first clock and higher than the frequency of the second clock in accordance with the data rate of the high definition video signal. An electronic still camera using 3 clocks.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram for explaining an electronic still camera according to an embodiment of the present invention, in which 1 is a solid-state image pickup device (CCD) that converts incoming subject light into an electrical signal and outputs it, and 2 is a solid-state image sensor. The analog signal processing unit 3 outputs the signal output from the image sensor 1 by performing processing such as correlated double sampling and automatic gain adjustment, and converts the analog signal output from the analog signal processing unit 2 into a digital signal. This is an A / D conversion unit for output.
[0010]
Reference numeral 4 denotes a digital signal processing unit that performs various signal processing on the digital signal output from the A / D conversion unit 3 or the digital signal from the video signal input / output control unit 5 as described later. The video signal input / output control unit 6 changes the digital signal data rate and controls the input / output when the digital signal is written to the internal memory 6 or read from the internal memory 6. An internal memory that is connected and temporarily stores a digital signal from the video signal input / output control unit 5, and 7 is connected to the video signal input / output control unit 5. Photographic Coding Experts Group) JPEG processing unit that performs compression / decompression processing.
[0011]
Reference numeral 8 denotes a CCD drive control unit for driving the solid-state imaging device 1, and 9 is connected to the video signal input / output control unit 5 to control the operation of the CCD drive control unit 8 and It is a control unit that inputs / outputs digital signals to / from the external recording medium 10. As the external recording medium 10, a removable recording medium such as the above-described SSFDC can be used. Reference numeral 11 denotes a D / A conversion unit that converts a digital signal from the video signal input / output control unit 5 into an analog signal and outputs it to an internal monitor or an external monitor (not shown).
[0012]
Here, an 18 MHz clock is supplied to the A / D conversion unit 3, the digital signal processing unit 4, and the control unit 9, and the A / D conversion processing and digital signal processing unit in the A / D conversion unit 3 are supplied. The digital signal processing at 4 and the control at the control unit 9 all operate with an 18 MHz clock. The JPEG processing unit 7 is supplied with a 45 MHz clock, and the compression / decompression processing in the JPEG processing unit 7 operates with a 45 MHz clock.
[0013]
The operation of the electronic still camera according to the embodiment of the present invention will be described below.
First, the analog signal output from the solid-state imaging device 1 based on the drive signal generated by the CCD drive control unit 8 is processed by the analog signal processing unit 2 and supplied to the A / D conversion unit 3. The analog video signal output from the analog signal processing unit 2 is an analog signal having an RGB signal form, and the A / D conversion unit 3 converts the analog signal into a digital signal. Then, the signal converted into the digital signal is temporarily stored in the internal memory 6 via the video signal input / output control unit 5.
[0014]
When a digital signal for one screen is stored in the internal memory 6, reading of the digital signal having the RGB signal form is started. The read digital signal is output to the digital signal processing unit 4 through the video signal input / output control unit 5, and the digital signal in the RGB signal form in the digital signal processing unit 4 has the signal form of luminance and color difference. Converted into a digital signal. Then, the converted digital signal is written into the internal memory 6 again via the video signal input / output control unit 5.
[0015]
The solid-state imaging device 1 outputs a 2048 × 1536 pixel still image in the horizontal and vertical directions. If the image size needs to be reduced to an image smaller than this, the reduction processing is performed by the digital signal processing unit. Perform in step 4. Therefore, in such a case, a still image is read again from the internal memory 6, and this still image is output to the digital signal processing unit 4 via the video signal input / output control unit 5. Then, the still image that has undergone the reduction process in the digital signal processing unit 4 is written into the internal memory 6 via the video signal input / output control unit 5.
[0016]
Further, when a captured still image is displayed on an internal monitor (not shown), a still image having a size suitable for display on the internal monitor is generated by the reduction process in the digital signal processing unit 4 and then reduced. The still image is written in the internal memory 6 and further displayed on the internal monitor via the video signal input / output control unit 5 and the D / A conversion unit 11. Similarly, when a captured still image is output to an external monitor as a standard definition television signal such as NTSC or PAL, a still image having a size corresponding to the television signal is generated and written to the internal memory 6. It is.
[0017]
In order to reduce the data amount, a video signal input / output control unit is used to reduce the amount of data of a 2048 × 1536 pixel still image stored in the internal memory 6 in the horizontal and vertical directions or a still image subjected to reduction processing as necessary. 5 is output to the JPEG processing unit 7 through JPEG, and JPEG compression processing is performed. When this compression processing is completed, the still image is written again into the internal memory 6 via the video signal input / output control unit 5. After that, the still image that has been subjected to the JPEG compression process is read to the video signal input / output control unit 5 and is recorded on the external recording medium 10 via the control unit 9 by DMA (Direct Memory Access) transfer.
[0018]
When displaying a still image recorded on the external recording medium 10 on the internal monitor or the external monitor, the control unit 9 inputs the video signal when the still image compressed by the JPEG method is read from the external recording medium 10. It is written in the internal memory 6 via the output control unit 5. Thereafter, the still image is output via the video signal input / output control unit 5 for the JPEG decompression process.
[0019]
When the decompression process in the JPEG processing unit 7 is completed, it is written again into the internal memory 6 via the video signal input / output control unit 5, and then, as described above, the reduction process by the digital signal processing unit 4 is performed by the internal monitor. A still image having a size suitable for display or a still image having a size corresponding to a standard definition television signal is generated. Then, the still image reduced in this way is output from the D / A converter 11 via the video signal input / output controller 5.
[0020]
As described above, in the electronic still camera shown in FIG. 1, every time one process is completed, the data is once written in the internal memory 6. At this time, the input / output of the data is always the video signal input / output control unit. 5 will be performed. In addition, when a still image captured by the solid-state image sensor 1 is displayed on the internal monitor without being recorded on the external recording medium 10, a signal output from the solid-state image sensor 1 after being thinned out line by line is A / The signal is supplied from the D conversion unit 3 to the digital signal processing unit 4. Then, a still image that has been thinned out in the horizontal direction in the digital signal processing unit 4 and reduced to a size suitable for display on the internal monitor passes through the video signal input / output control unit 5 and the D / A conversion unit 11. Output to the internal monitor.
[0021]
Next, the configuration of the video signal input / output control unit 5 will be described with reference to FIGS. As shown in FIG. 2, the video signal input / output control unit 5 includes an internal memory write buffer 5a, internal memory read buffers 5b and 5c, an HD read buffer 5d, a control unit buffer 5e, a JPEG processing buffer 5f, The internal memory input / output control unit 5g is configured.
[0022]
Here, as shown in FIG. 3, the buffers 5a to 5d are composed of buffers 5h and 5i and switches SW1 and SW2, and writing to one of the buffers is performed by switching by the switches SW1 and SW2. At this time, the read operation is performed from the other buffer.
[0023]
The buffers 5e and 5f have the same configuration as the buffers 5a to 5d shown in FIG. 3, but are provided with an additional changeover switch so that data can be transferred bidirectionally. That is, in FIG. 3, the data is shown to be output from the switch SW1 side to the switch SW2 side, but the data is bidirectionally limited to the control unit buffer 5e and the JPEG processing buffer 5f in FIG. For this purpose, a changeover switch (not shown) is additionally provided. Each of the buffers 5h and 5i has a capacity capable of holding data for 256 words (256 pixels in a digital signal having luminance and color difference signal forms). Therefore, in order to output data for one horizontal line (for 2048 pixels), writing and reading operations are performed eight times.
[0024]
Here, the internal memory input / output control unit 5g is connected to the internal memory 6, and outputs data from the internal memory write buffer 5a, the control unit buffer 5e, or the JPEG processing buffer 5f to the internal memory 6, Further, the data from the internal memory 6 can be output to the internal memory reading buffer 5b, the internal memory reading buffer 5c, the HD reading buffer 5d, the control unit buffer 5e, and the JPEG processing buffer 5f.
[0025]
The internal memory write buffer 5a is written with a digital signal from the A / D converter 3 or the digital signal processor 4, and the data read from the internal memory read buffers 5b and 5c is a digital signal. The data output to the processing unit 4 or the D / A conversion unit 11 and read from the HD reading buffer 5d is configured to be output to the D / A conversion unit 11. Although only one D / A converter 11 is shown in FIG. 1, a plurality of D / A converters may be used to convert digital signals of various data rates into analog signals. Needless to say.
[0026]
The control unit buffer 5e is bidirectionally connected to the control unit 9, and the JPEG processing buffer 5f is bidirectionally connected to the JPEG processing unit 7, so that the control unit buffer 5e and the JPEG processing buffer 5f are connected. Can exchange data with these components.
[0027]
When the video signal input / output control unit 5 exchanges data with the internal memory 6, the video signal input / output control unit 5 exchanges data with a clock of 90 MHz, and exchanges data with other configurations. In this case, data is transferred with a clock of 18 MHz, 45 MHz or 72.25 MHz. Therefore, the internal memory 6 can perform input / output of a plurality of data in parallel in a time division manner.
[0028]
Therefore, in each of the buffers 5a to 5f shown in FIG. 2, when data written in the buffer is read to the internal memory input / output control unit 5g side, or data from the internal memory input / output control unit 5g side is stored in the buffer. When data is written, data is read or written with a 90 MHz clock.
[0029]
On the other hand, when data is written from the outside of the video signal input / output control unit 5 to the internal memory writing buffer 5a, the control unit buffer 5e, the JPEG processing buffer 5f, or the internal memory reading buffer 5b, the internal memory reading buffer 5c, when reading data from the control unit buffer 5e to the outside of the video signal input / output control unit 5, data is read or written with a clock of 18 MHz. When data is read from the JPEG processing buffer 5f to the JPEG processing unit 7, data is read with a 45 MHz clock, and when data is read from the HD reading buffer 5d to the D / A conversion unit 11, 74 is read. Data is read out with a 25 MHz clock.
[0030]
4A and 4B are diagrams for explaining parallel processing of a plurality of data in the internal memory 6, in which FIG. 4A is a horizontal synchronizing signal in an NTSC television signal, and FIG. 4B is internal memory writing. (C) is a data read operation from the internal memory write buffer 5a, (d) is a data write operation to the internal memory read buffer 5b, and (e) is an internal write operation. Data reading operation from the memory reading buffer 5b, (f) is a data writing operation to the JPEG processing buffer 5f, (g) is a data reading operation from the JPEG processing buffer 5f, and (h) is in the internal memory 6. It is a figure for demonstrating operation | movement.
[0031]
Here, the digital signal having the luminance and color difference signal form stored in the internal memory 6 is reduced by the digital signal processing unit 4 and simultaneously the digital signal having the luminance and color difference signal form is compressed by the JPEG method. The video signal input / output control unit 5 reads the still image from the internal memory 6 and outputs it to the digital signal processing unit 4 and the JPEG processing unit 7, and the still image that has been processed by the digital signal processing unit 4 It is necessary to simultaneously perform the operation of outputting to the memory 6.
[0032]
The operation at that time will be described below. First, as shown in FIG. 4 (d), the still image from the internal memory 6 is written to the internal memory read buffer 5b in units of 256 words with a clock of 90 MHz. The data of 256 words written in the buffer 5b is output to the digital signal processing unit 4 with an 18 MHz clock as shown in FIG.
[0033]
Further, the still image from the internal memory 6 is written to the JPEG processing buffer 5f in units of 256 words with a clock of 90 MHz, and the data of 256 words written to the JPEG processing buffer 5f is as shown in FIG. The data is output to the JPEG processing unit 7 with a 45 MHz clock.
[0034]
As described above, 256 words are output to the digital signal processing unit 4 and the JPEG processing unit 7 in units of 256 words, but the processing in the digital signal processing unit 4 is sequentially performed before all the still images for one screen are output. In order to complete, the processed data is written to the internal memory 6 in parallel. That is, as shown in FIG. 4B, the processed data is written to the internal memory write buffer 5a with an 18 MHz clock, and the data written to the internal memory write buffer 5a is converted to the data shown in FIG. As shown in FIG. 4, the data is written into the internal memory 6 with a 90 MHz clock.
[0035]
In the internal memory 6, as shown in FIG. 4 (h), the processing for the internal memory writing buffer 5a, the processing for the internal memory reading buffer 5b, and the processing for the JPEG processing buffer 5f are time-shared. Therefore, all these processes can be performed in parallel.
[0036]
As shown in FIGS. 4B, 4E, and 4G, data is written to the internal memory write buffer 5a, data is read from the internal memory read buffer 5b, and the JPEG processing buffer 5f. The data read from is performed with a clock of 18 MHz or 45 MHz, respectively, while the data read from the internal memory write buffer 5a is performed as shown in FIGS. 4 (c), (d) and (f). The data writing to the internal memory reading buffer 5b and the data writing to the JPEG processing buffer 5f are each performed with a clock of 90 MHz.
[0037]
Therefore, in calculation, 90 MHz / 18 MHz = 5, and five processes can be performed in parallel. However, when an SDRAM (Synchronous Dynamic Random Access Memory) is used as the internal memory 6, the refresh operation is performed. In practice, up to four processes can be performed in parallel. In the example shown here, the operating frequency of the internal memory 6 is 90 MHz, but it goes without saying that a plurality of processes can be performed in parallel if the operating frequency is 36 MHz, which is twice 18 MHz.
[0038]
Further, the electronic still camera shown in FIG. 1 may be configured such that a plurality of still images are accumulated in the internal memory 6 and these still images can be combined. In order to combine a plurality of still images into a single still image in this way, for example, a plurality of still images output from the video signal input / output control unit 5 can be input simultaneously, and the combined still images can be input to a video signal. A video composition unit that can be returned to the output control unit 5 may be provided.
[0039]
In order to synthesize a plurality of still images into one still image as described above, the internal memory reading buffer 5b and the internal memory reading buffer 5c shown in FIG. A still image may be read out and the synthesized still image may be written into the internal memory 6 using the internal memory writing buffer 5a. By using this function, for example, a still image in which a frame image is combined with a still image is generated, a still image in which a person is combined with a background image is generated, a collage, a chroma key, Processing such as luminance skiing becomes possible.
[0040]
Next, the operation when outputting still images stored in the internal memory 6 to an external monitor (not shown) will be described with reference to FIG. In this figure, (a) is a horizontal synchronizing signal in an NTSC television signal, (b) is a data write operation to the internal memory read buffer 5b, and (c) is a data read operation from the internal memory read buffer 5b. (D) is a horizontal synchronizing signal in the high-definition signal, (e) is a data write operation to the HD read buffer 5d, and (f) is a diagram for explaining a data read operation from the HD read buffer 5d. is there.
[0041]
First, the operation when an NTSC television signal is output to an external monitor will be described. A still image having a size corresponding to the NTSC television signal stored in the internal memory 6 is shown in FIG. As shown in the drawing, 256 words are written to the internal memory reading buffer 5b with a 90 MHz clock, and the 256 word data written to the internal memory reading buffer 5b is D with an 18 MHz clock as shown in FIG. Is output to the / A converter 11.
[0042]
Here, a still image having a size matched to an NTSC television signal is a still image having 640 pixels in the horizontal direction and 480 pixels in the vertical direction. It is necessary to write data to the memory read buffer 5b three times. Then, by repeating this for 480 lines, a still image for one screen can be obtained.
[0043]
On the other hand, when a high-definition television signal is output to an external monitor, the still image before reduction processing stored in the internal memory 6 is a clock of 90 MHz for each 256 words as shown in FIG. Thus, the data of 256 words written in the HD read buffer 5d and written in the HD read buffer 5d is read out with a clock of 72.45 MHz as shown in FIG.
[0044]
Here, since the still image stored in the internal memory 6 and not subjected to the reduction process is a still image having 2048 pixels in the horizontal direction and 1536 pixels in the vertical direction, data for one line is obtained. Needs to write data to the internal memory read buffer 5b eight times. Then, by selecting and outputting 1082 lines near the center of the screen out of 1536 lines, it becomes possible to output a high-definition signal.
[0045]
【The invention's effect】
According to the first aspect of the present invention, when the input / output control unit exchanges data with the memory, each buffer unit is operated with the first clock, and the data processing with the signal processing unit is performed. When transferring, each buffer unit is operated with a second clock having a frequency lower than the frequency of the first clock, so that it is possible to execute high-speed processing of data using a plurality of buffer units in parallel. Become. In addition, since the capacity of each buffer unit is smaller than the data amount of data for one horizontal line in the image sensor, the circuit scale can be suppressed.
[0046]
Furthermore, according to the present invention , the input / output control unit includes an HD output buffer and can output a high-definition video signal, so that even a television receiver displays an image with the original image quality of the still image. There is an effect that can be.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a configuration of an electronic still camera according to the present invention.
FIG. 2 is a diagram illustrating a configuration of a video signal input / output control unit 5;
FIG. 3 is a diagram illustrating an internal configuration of each buffer.
FIG. 4 is a diagram for explaining parallel processing of a plurality of data.
FIG. 5 is a diagram for explaining output of a still image to an external monitor.
[Explanation of symbols]
1 ... Solid-state imaging device (CCD)
2 ... Analog signal processing unit 3 ... A / D conversion unit 4 ... Digital signal processing unit 5 ... Video signal input / output control units 5a to 5f ... Buffer 5g ... Internal memory input / output control unit 6 ... Internal memory 7 ... JPEG processing unit 8 ... CCD drive control unit 9 ... Control unit 10 ... External recording medium 11 ... D / A conversion unit

Claims (1)

An electronic still comprising an image pickup device, an A / D converter, a memory, a signal processor, a memory write buffer, a memory read buffer, and an HD read buffer A camera,
The image sensor converts incoming subject light into an electrical signal in the form of an analog signal and outputs it to the A / D converter,
The A / D converter converts an electrical signal output from the image sensor into a digital signal and outputs the digital signal to the signal processor,
When the memory transfers data in parallel in a time-sharing manner between the memory write buffer unit, the memory read buffer unit, and the HD read buffer unit, the memory has a predetermined frequency. Using a first clock having
The signal processing unit performs a predetermined signal processing on the digital signal supplied from the A / D conversion unit and outputs the digital signal to the memory writing buffer unit. When performing a predetermined signal processing and outputting, each is performed using a second clock having a frequency lower than the frequency of the first clock,
The input / output control unit has a capacity smaller than a data amount of data for one horizontal line in the image sensor, the memory write buffer unit, the memory read buffer unit, and a high-definition video signal. Each of which has an HD reading buffer section to read,
When transferring data between the memory write buffer unit, the memory read buffer unit, and the HD read buffer unit, and the memory, the first clock is used,
When transferring data between each of the memory write buffer unit and the memory read buffer unit and the signal processing unit, the second clock is used,
When data is read from the HD read buffer unit, the first clock having a frequency lower than the frequency of the first clock and higher than the frequency of the second clock in accordance with the data rate of the high definition video signal. An electronic still camera using 3 clocks .

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