JP3580285B2 - Manufacturing method of semiconductor dynamic quantity sensor - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor physical quantity sensor having three layers.
[0002]
[Prior art]
Conventionally, a semiconductor physical quantity sensor composed of three layers is known. The first layer is used as a support plate, on which a second insulating layer is applied. A third layer is deposited on the second insulating layer. The movable element of the semiconductor dynamic quantity sensor is drawn out from the third layer. The electrical lead conductor is located above the third layer. This movable part is insulated from the rest of the third layer by an insulating groove. This semiconductor dynamic quantity sensor is formed by being drawn from silicon.
[0003]
[Problems to be solved by the invention]
An object of the present invention is to reduce the cost and simplify the manufacturing method by forming a semiconductor dynamic quantity sensor using a three-layer system.
[0004]
[Means for Solving the Problems]
In order to solve the above problem, the invention according to claim 1 has a first layer, a second layer made of an insulator is applied on the first layer, and the second layer is formed on the second layer. In a method of manufacturing a physical quantity sensor in which a third layer is provided, a step of applying a first layer structure on the third layer; and a step of attaching the first layer structure to the physical quantity sensor. Structuring into a shape, and etching the third layer using the first layer structure as a mask, and providing a physical quantity sensor including a fixed portion, a displaceable weight portion, and a conductive path from the third layer. A gist of the present invention is a method for manufacturing a physical quantity sensor, comprising: a forming step; and a step of removing the second layer below the displaceable weight portion.
[0005]
Further, according to a third aspect of the present invention, a first layer made of a silicon substrate is prepared, a second layer made of an insulating layer is disposed on the first layer, and a silicon layer is formed on the second layer. A third pattern layer having a shape of a physical quantity sensor is disposed on the third layer, and the third layer is formed using the first pattern layer as a mask. Forming a sensor section having a fixed electrode section and a movable electrode section moving in one direction in parallel with the surface of the first layer, and forming a sensor section on the fixed electrode section and the movable electrode. An electric conductor portion made of metal is formed on substantially the same surface on the portion, and at least the second layer below a movable region of the movable electrode portion is removed, and the fixed electrode portion and the movable electrode portion are formed on the same surface. The first layer is electrically insulated by the second layer. The manufacturing method of the semiconductor dynamic quantity sensor as its gist that.
[0006]
According to the first and third aspects of the present invention, a semiconductor physical quantity sensor and an electric lead conductor can be formed using a three-layer system. This makes the manufacturing method particularly simple. That is, there is an advantage that a semiconductor dynamic quantity sensor can be manufactured using only a few masks and few processing steps. This method is simple and low cost.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
(First embodiment)
An embodiment of the present invention will be described below with reference to the drawings.
[0008]
FIG. 1 shows a plan view of the acceleration sensor, and FIG. 2 shows a cross-sectional view taken along line AA of FIG. This acceleration sensor is a capacitive acceleration sensor, and as shown in FIG. 2, a single crystal silicon substrate 1 is bonded on a single crystal silicon substrate 8 via an SiO 2 film 9, and the single crystal silicon substrate 1 is The cantilever 13 is formed by the trench 3 penetrating through. As shown in FIG. 1, the cantilever 13 has a structure in which the distal end is divided into two. The cantilever 13 is movable in a direction parallel to the surface of the single crystal silicon substrate 1 (in the direction of arrow C in FIG. 1). Further, in the single crystal silicon substrate 1, the signal processing circuit 10 is formed in a state where the signal processing circuit 10 is electrically insulated from the cantilever 13 by the polysilicon film 6 and the SiO2 film 5.
[0009]
3 to 10 show the manufacturing process. Hereinafter, the manufacturing process will be described. As shown in FIG. 3, an n-type (100) single crystal silicon substrate 1 of 1 to 20 Ω · cm is prepared, a SiO 2 film 2 of about 1 μm is formed on the main surface by thermal oxidation, and a SiO 2 film is formed by photolithography. 2 is formed in a predetermined pattern. Subsequently, on the main surface side of the single crystal silicon substrate 1, a trench 3 having a vertical wall of a predetermined depth, for example, about 0.2 to 30 μm is formed by reactive ion etching or the like. In this embodiment, the case of about 3 μm will be described.
[0010]
Then, after removing the SiO2 film 2, as shown in FIG. 4, an n + diffusion layer 4 of phosphorus, arsenic, or the like is formed on the main surface of the single crystal silicon substrate 1 including the inner wall of the trench 3, and further, thermal oxidation or the like is performed. To form a SiO2 film 5 of 0.1 to 1 [mu] m. At this time, in order to remove etching damage, so-called sacrificial oxidation, in which SiO2 is formed and removed by thermal oxidation before forming the n + diffusion layer 4, may be performed.
[0011]
Subsequently, as shown in FIG. 5, a polysilicon film 6 is formed on the main surface of the single crystal silicon substrate 1, and the trench 3 is filled with the polysilicon film 6. When impurities are introduced into the polysilicon film 6 in order to use the polysilicon film 6 as a conductive path for bias, a thin polysilicon layer is formed before the polysilicon film 6 is formed, In this case, impurities can be introduced into the polysilicon film 6.
[0012]
Next, as shown in FIG. 6, the surface of the polysilicon film 6 is mirror-polished so that the polysilicon film 6 having a predetermined thickness remains. Subsequently, a p + diffusion layer 7 of boron is formed in a predetermined region of the polysilicon film 6 by ion implantation or the like.
[0013]
On the other hand, as shown in FIG. 7, another (100) single crystal silicon substrate 8 is prepared, and a 0.1 to 1.0 μm SiO 2 film 9 is formed on the main surface thereof by thermal oxidation. Next, the single-crystal silicon substrate 1 and the single-crystal silicon substrate 8 are placed in, for example, a mixed aqueous solution of a hydrogen peroxide solution and sulfuric acid to perform a hydrophilic treatment. Then, after drying, as shown in FIG. 8, the main surface of the single crystal silicon substrate 1 and the main surface of the single crystal silicon substrate 8 are superposed at room temperature and placed in a furnace at 400 to 1100 ° C. for 0.5 minute. Insert for ~ 2 hours to make a strong bond.
[0014]
Next, as shown in FIG. 9, the back surface of the single crystal silicon substrate 1 is selectively polished using an alkaline aqueous solution, for example, a KOH solution or the like, and is processed until the SiO 2 film 2 appears. As a result, the thickness of the single crystal silicon substrate 1 becomes, for example, about 3 μm, and the thickness is reduced.
[0015]
Then, as shown in FIG. 10, a signal processing circuit (IC circuit section) 10 is formed in a predetermined region of the single crystal silicon substrate 1 by using a normal CMOS process or a bipolar process. 1 and 10, only a MOS transistor is shown as a part of the signal processing circuit 10. Further, a plasma SiN film (P-SiN) is formed as a passivation film 11 on the upper surface of the signal processing circuit 10 by, for example, a plasma CVD method. Subsequently, a window 12 is opened in a predetermined region of the passivation film 11.
[0016]
Then, as shown in FIG. 2, a passivation film 11 is formed from the back side (upper side in FIG. 2) of the single-crystal silicon substrate 1 using an approximately 20% solution of TMAH (tetramethylammonium hydroxide) (CH 3) 4 NOH. The polysilicon film 6 is removed by etching through the window 12 of FIG. At this time, the passivation film 11 (P-SiN), the SiO2 film 5, the aluminum wiring layer, and the p + diffusion layer (p + polysilicon film) 7 are hardly etched by the selective etching.
[0017]
When the polysilicon film 6 is removed by etching, an etching hole 48 is provided in a wide portion of the cantilever 13 in FIG. 1, and the polysilicon film 6 is more reliably removed through the etching hole 48. I am trying to do it.
[0018]
As a result, a cantilever 13 is formed. At this time, as shown in FIG. 2, the thickness L2 of the cantilever 13 in the direction parallel to the surface of the single crystal silicon substrate 1 is smaller than the thickness L1 of the single crystal silicon substrate 1 in the depth direction. Has become.
[0019]
In the capacitive acceleration sensor, the tip portion (a portion divided into two portions) of the cantilever 13 serves as a movable electrode, and as shown in FIG. The substrate 1 becomes the fixed electrodes 14, 15, 16, and 17. As shown in FIG. 1, the fixed electrode 14 and the fixed electrode 16 are taken out by the aluminum wiring layer 18a, the fixed electrode 15 and the fixed electrode 17 are taken out by the aluminum wiring layer 18b, and (Movable electrode) 13 is extracted from aluminum wiring layer 18c. The aluminum wiring layers 18a, 18b, and 18c are connected to a signal processing circuit 10, and the signal processing circuit 10 performs signal processing accompanying displacement of the cantilever (movable electrode) 13 due to acceleration. Further, the potential is kept constant by the n + diffusion layer 4 (see FIG. 2) disposed on the cantilever 13 (movable electrode) and the fixed electrodes 14, 15, 16, and 17.
[0020]
In this embodiment, the acceleration sensor is a capacitive acceleration sensor. However, if a piezoresistive layer is formed on the surface of the root of the cantilever 13, the acceleration sensor can be a piezoresistive acceleration sensor. Of course, if these two types of sensors are formed on the same substrate, the accuracy and reliability can be further improved.
[0021]
In the acceleration sensor manufactured as described above, the single-crystal silicon substrate 1 is bonded to the single-crystal silicon substrate 8 via the SiO2 film to form an SOI structure. Further, in the cantilever 13, the thickness L2 in the direction parallel to the surface of the single crystal silicon substrate 1 is smaller than the thickness L1 in the depth direction of the single crystal silicon substrate 1. Therefore, the cantilever 13 can move on the surface of the single crystal silicon substrate 1 in a direction parallel to the surface, and acceleration in a direction parallel to the substrate surface is detected.
[0022]
As described above, in the present embodiment, the trench (groove) 3 having a predetermined depth for forming the cantilever 13 is formed on the main surface of the single-crystal silicon substrate 1 (first step). A trench 3 was filled with the polysilicon film 6, and the surface of the polysilicon film 6 was smoothed (second step). Then, the main surface of the single-crystal silicon substrate 1 and the single-crystal silicon substrate 8 on which the SiO2 film (insulating film) 9 is formed are joined via the SiO2 film 9 (third step), and the single-crystal silicon substrate 1 The single-crystal silicon substrate 1 was thinned by polishing the back surface by a predetermined amount (fourth step). Further, after the signal processing circuit 10 was formed on the surface of the single crystal silicon substrate 1, the polysilicon film 6 was removed by etching from the back surface side of the single crystal silicon substrate 1 to form the cantilever 13 (fifth step).
[0023]
Therefore, in the formation process of the signal processing circuit 10 in the middle of the wafer process, the trench 3 is buried in the surface portion of the single crystal silicon substrate 1 by the polysilicon film 6, thereby contaminating the IC element, contaminating the manufacturing apparatus, and so on. It is possible to prevent defective and degraded electrical characteristics. In other words, the wafer process prevents contamination and the like by stabilizing the wafer process by preventing surface structures such as concave portions and through-holes from appearing on the wafer surface during heat treatment, photolithography, and the like during the process, A highly accurate acceleration sensor can be supplied stably.
[0024]
The acceleration sensor manufactured in this manner is formed on the single-crystal silicon substrate 1, which is bonded to the single-crystal silicon substrate 8 via the SiO 2 film (insulating film) 9 and thinned, and the single-crystal silicon substrate 1. A cantilever 13 movable in a direction parallel to the surface thereof, and a signal processing circuit 10 formed on the single-crystal silicon substrate 1 and performing signal processing accompanying the operation of the cantilever 13 due to acceleration. When acceleration acts in a direction parallel to the surface of the single-crystal silicon substrate 1, the cantilever 13 formed on the single-crystal silicon substrate 1 operates. Signal processing is performed by the signal processing circuit 10 formed on the single-crystal silicon substrate 1 with the operation of the cantilever 13. Thus, the acceleration sensor is formed by the surface micromachining technology using single crystal silicon, and high accuracy and high reliability can be achieved with a novel structure.
[0025]
In addition, since the surface of the cantilever 13 and the single-crystal silicon substrate 1 facing the cantilever 13 are covered with the SiO2 film (insulator) 5, electrode short-circuit in the capacitive acceleration sensor is prevented. be able to. Note that at least one of the surface of the cantilever 13 and the single-crystal silicon substrate 1 facing the cantilever 13 may be covered with the SiO 2 film (insulator) 5.
[0026]
As an application of this embodiment, as shown in FIGS. 11 and 12, the cantilever 13 may be separated from the signal processing circuit (IC circuit section) 10 to reduce the parasitic capacitance, and may be used as an air bridge wiring. Further, the fixed electrodes 14, 15, 16, 17 may have the same structure. Further, in the above embodiment, the aluminum wiring layer is used, but the wiring portion may be formed by a polysilicon layer. Further, in the above embodiment, two movable electrodes are formed at the tip of the beam and four fixed electrodes 14, 15, 16, 17 are formed. However, in order to further improve the sensitivity, the movable electrode portion and the fixed electrode portion are formed. May be comb-shaped.
[0027]
(Second embodiment)
Next, the second embodiment will be described focusing on the differences from the first embodiment.
[0028]
In the first embodiment, the p + diffusion layer (p + polysilicon film) 7 is formed for the purpose of forming the cantilever 13 in order to separate this portion from the single-crystal silicon substrate by a predetermined distance. A recess is formed before the trench is formed in order to keep the predetermined distance.
[0029]
13 to 21 show the manufacturing process. As shown in FIG. 13, an n-type (100) single-crystal silicon substrate 20 is prepared, and a concave portion 21 is formed on the main surface of the single-crystal silicon substrate 20 by dry etching or wet etching to a predetermined depth, for example, 0.1 to 5 μm. Formed at a depth of Then, as shown in FIG. 14, an SiO 2 film 22 is formed on the main surface of the single crystal silicon substrate 20, and a pattern is formed by photolithography. Subsequently, a trench 23 of about 0.1 to 30 μm is formed on the main surface of the single crystal silicon substrate 20 including the bottom of the concave portion 21 by dry etching or the like.
[0030]
Then, as shown in FIG. 15, an n + diffusion layer 24 is formed on the main surface of the single crystal silicon substrate 20 including the inner wall of the trench 23, and an SiO2 film 25 is formed by thermal oxidation. Thereafter, as shown in FIG. 16, a polysilicon film 26 is buried in the trench 23 by the LPCVD method.
[0031]
Subsequently, as shown in FIG. 17, the surface of the polysilicon film 26 is polished using the SiO 2 film 25 as a stopper to smooth the surface. At this time, it is desirable that the surfaces of the polysilicon film 26 and the SiO2 film 25 be smooth, but if the surface of the SiO2 film 25 is smooth even if the portion of the polysilicon film 26 is dented, There is no problem in the wafer bonding performed.
[0032]
On the other hand, as shown in FIG. 18, another (100) single crystal silicon substrate 27 is prepared, and a 0.1 to 1.0 μm SiO 2 film 28 is formed on the main surface thereof by thermal oxidation. Next, the single-crystal silicon substrates 20 and 27 are placed in, for example, a mixed aqueous solution of a hydrogen peroxide solution and sulfuric acid, and a hydrophilic treatment is performed. After drying, the main surfaces of both single crystal silicon substrates 20 and 27 are overlapped at room temperature, and placed in a furnace at 400 to 1100 ° C. for 0.5 to 2 hours to perform strong bonding.
[0033]
Next, as shown in FIG. 19, the back surface of the single crystal silicon substrate 20 is selectively polished using an alkaline aqueous solution, for example, a KOH solution or the like, and is processed until the SiO 2 film 25 appears. As a result, the thickness of the single crystal silicon substrate 20 becomes, for example, about 3 μm, and the thickness is reduced.
[0034]
Then, as shown in FIG. 20, the signal processing circuit (IC circuit section) 10 is formed through a normal CMOS process, a bipolar process, or the like. Further, a plasma SiN film (P-SiN film) is formed on the upper surface of the signal processing circuit 10 as the passivation film 11 by, for example, a plasma CVD method. Subsequently, a window 12 is opened in a predetermined region of the passivation film 11.
[0035]
Then, as shown in FIG. 21, a polysilicon film is passed through the window 12 of the passivation film 11 from the back side of the single crystal silicon substrate 20 using a solution of about 20% of TMAH (tetramethylammonium hydroxide) (CH3) 4NOH. 26 is removed by etching. At this time, the passivation film 11 (P-SiN), the SiO2 film 25, and the aluminum wiring layer are hardly etched by the selective etching.
[0036]
As a result, a cantilever 13 is formed.
[0037]
(Third embodiment)
Next, a third embodiment will be described focusing on differences from the first embodiment.
[0038]
In the first and second embodiments, polysilicon is buried in the trench before wafer bonding. In this embodiment, polysilicon is buried in the trench after wafer bonding, and the buried polysilicon is removed in the final step. And an acceleration sensor.
[0039]
22 to 28 show the manufacturing process. As shown in FIG. 22, an n-type (100) single-crystal silicon substrate 30 is prepared, and a concave portion 31 having a depth of 0.1 to 5 μm is formed on a main surface thereof. On the other hand, as shown in FIG. 23, a single-crystal silicon substrate 32 is prepared, and a SiO2 film 33 is formed on the main surface by thermal oxidation. Then, the main surface of single crystal silicon substrate 30 and the main surface of single crystal silicon substrate 32 are joined.
[0040]
Further, as shown in FIG. 24, the rear surface of the single crystal silicon substrate 30 is mirror-polished to a predetermined thickness (0.1 to 30 μm). Then, as shown in FIG. 25, a SiO 2 film 34 is formed in a thickness of 0.1 to 2 μm, and then a trench 35 is formed by etching. At this time, the cantilever 13 is formed.
[0041]
Next, N-type impurities such as arsenic and phosphorus are introduced at a high concentration by a thermal diffusion method or the like, and an n + high concentration layer 36 is formed in a region not covered with the SiO 2 films 33 and 34. Subsequently, as shown in FIG. 26, a polysilicon film 37 is formed on the surface of the single crystal silicon substrate 30, and the trench 35 is filled with the polysilicon film 37. Thereafter, as shown in FIG. 27, the surface of the polysilicon film 37 is selectively polished and flattened until the SiO2 film 34 appears. Further, as shown in FIG. 28, after forming the signal processing circuit 10, the polysilicon film 37 is finally removed by etching from the rear surface side (upper surface side) of the single crystal silicon substrate 30 to form the cantilever 13.
[0042]
As described above, in the present embodiment, the main surface of the single-crystal silicon substrate 30 and the single-crystal silicon substrate 32 on which the SiO2 film (insulating film) 33 is formed are bonded via the SiO2 film 33 (first step). The back surface of the single-crystal silicon substrate 30 is polished by a predetermined amount to thin the single-crystal silicon substrate 30 (second step). Then, a trench (groove) 35 having a predetermined depth for forming the cantilever 13 is formed on the back surface of the single crystal silicon substrate 30 (third step), and a polysilicon film 37 is formed on the back surface of the single crystal silicon substrate 30. Is formed, the trench 35 is filled with the polysilicon film 37, and the surface of the polysilicon film 37 is smoothed (fourth step). Further, after a signal processing circuit was formed on the single crystal silicon substrate 30, the polysilicon film 37 was removed by etching from the back surface side of the single crystal silicon substrate 30 to form the cantilever 13 (fifth step).
[0043]
Therefore, in the process of forming the signal processing circuit 10 in the middle of the wafer process, the trench 35 is buried in the upper surface portion of the single crystal silicon substrate 30 by the polysilicon film 37, thereby contaminating the IC element, contaminating the manufacturing apparatus, It is possible to prevent defective and degraded electrical characteristics. In other words, the wafer process prevents contamination and the like by stabilizing the wafer process by preventing surface structures such as concave portions and through holes from appearing on the wafer surface during heat treatment, photolithography, and the like during the process, A highly accurate acceleration sensor can be supplied stably.
[0044]
(Fourth embodiment)
Next, a fourth embodiment will be described focusing on differences from the third embodiment.
[0045]
The present embodiment is for manufacturing a sensor at lower cost than the third embodiment. 29 to 31 show manufacturing steps.
[0046]
As shown in FIG. 29, an SiO 2 film 41 of 0.1 to 2 μm is formed on the main surface of a single crystal silicon substrate 40, and a single crystal silicon substrate 42 is joined with the SiO 2 film 41 interposed therebetween. Then, as shown in FIG. 30, the upper surface of the single crystal silicon substrate 42 is polished to make the single crystal silicon substrate 42 have a predetermined thickness. That is, the thickness of the single crystal silicon substrate 42 is reduced to, for example, about 3 μm. Thereafter, a high concentration n + diffusion layer 43 is formed on the upper surface of the single crystal silicon substrate 42, and a SiO2 film 44 is further formed thereon.
[0047]
Subsequently, as shown in FIG. 31, a trench 45 is formed in the single-crystal silicon substrate 42, and the SiO2 film 41 below the trench 45 is partially etched away with a hydrofluoric acid solution. At this time, the SiO2 film 41 below the portion to be the cantilever 13 is completely removed.
[0048]
Subsequent processing is the same as in FIGS. Next, an application example of the fourth embodiment will be described with reference to FIGS. As shown in FIG. 32, a 0.1-2 μm SiO 2 film 41 is formed on the main surface of single crystal silicon substrate 40, and a depth of 0.1-3 μm is formed in a predetermined region of the main surface of single crystal silicon substrate 42. Is formed. Then, the main surface of the single crystal silicon substrate 42 is joined with the SiO 2 film 41 interposed therebetween. Further, as shown in FIG. 33, the upper surface of the single crystal silicon substrate 42 is polished to make the single crystal silicon substrate 42 have a predetermined thickness. That is, the thickness of the single crystal silicon substrate 42 is reduced to, for example, about 3 μm. Thereafter, a high concentration n + diffusion layer 43 is formed on the upper surface of the single crystal silicon substrate 42, and a SiO2 film 44 is further formed thereon.
[0049]
Subsequently, as shown in FIG. 34, a trench 45 reaching the concave portion 47 is formed in the single crystal silicon substrate 42, and the cantilever 13 is formed. Subsequent processing is the same as in FIGS.
[0050]
By doing so, electrical insulation can be obtained more reliably than in the case where the SiO2 film 41 is partially etched away as shown in FIG.
[0051]
The present invention is not limited to the above embodiments, and can be applied to, for example, a double-supported beam structure and a multi-supported beam structure in addition to the cantilever structure. Further, as shown in FIG. 35, two acceleration sensors 13a and 13b are formed on the single crystal silicon substrate 50, and the acceleration sensor 13a detects the acceleration in the X direction and the acceleration sensor 13b detects the acceleration in the Y direction. Good. Further, an acceleration sensor capable of detecting acceleration in a direction perpendicular to the surface of the X and Y direction acceleration sensors 13a and 13b may be formed on the same substrate to detect three-dimensional acceleration. Further, when the present acceleration sensor is used as a capacitive type, the characteristics can be further stabilized by using a so-called servo type (closed loop circuit configuration).
[0052]
In the above embodiments, the trenches (grooves) 3, 23, and 35 are filled with the polysilicon films 6, 26, and 37. However, a polycrystalline or non-crystalline silicon film or a mixed silicon film may be used. That is, a silicon film in which polysilicon or amorphous silicon or a mixture of polysilicon and amorphous silicon may be used.
[Brief description of the drawings]
FIG. 1 is a plan view of an acceleration sensor.
FIG. 2 is a diagram showing a cross section taken along line AA of FIG. 1;
FIG. 3 is a view showing a manufacturing process of the first embodiment.
FIG. 4 is a diagram showing a manufacturing process.
FIG. 5 is a view showing a manufacturing process.
FIG. 6 is a diagram showing a manufacturing process.
FIG. 7 is a diagram showing a manufacturing process.
FIG. 8 is a diagram showing a manufacturing process.
FIG. 9 is a diagram showing a manufacturing process.
FIG. 10 is a diagram showing a manufacturing process.
FIG. 11 is a plan view showing an application example of the first embodiment.
FIG. 12 is a view showing a BB cross section of FIG. 11;
FIG. 13 is a view showing a manufacturing process of the second embodiment.
FIG. 14 is a view showing a manufacturing process.
FIG. 15 is a diagram showing a manufacturing process.
FIG. 16 is a diagram showing a manufacturing process.
FIG. 17 is a diagram showing a manufacturing process.
FIG. 18 is a diagram showing a manufacturing process.
FIG. 19 is a view showing a manufacturing process.
FIG. 20 is a diagram showing a manufacturing process.
FIG. 21 is a view showing a manufacturing process.
FIG. 22 is a diagram showing a manufacturing process of the third embodiment.
FIG. 23 is a diagram showing a manufacturing process.
FIG. 24 is a view showing a manufacturing process.
FIG. 25 is a diagram showing a manufacturing process.
FIG. 26 is a diagram showing a manufacturing process.
FIG. 27 is a diagram showing a manufacturing process.
FIG. 28 is a diagram showing a manufacturing process.
FIG. 29 is a diagram illustrating a manufacturing process of the fourth embodiment.
FIG. 30 is a diagram showing a manufacturing process.
FIG. 31 is a view showing a manufacturing process.
FIG. 32 is a diagram showing a manufacturing process of an application example of the fourth embodiment.
FIG. 33 is a diagram showing a manufacturing process.
FIG. 34 is a diagram showing a manufacturing process.
FIG. 35 is a plan view of another example of an acceleration sensor.
[Explanation of symbols]
1 Single-crystal silicon substrate 2 SiO2 film (insulating film)
3 trench
6 Polysilicon film 8 Single crystal silicon substrate 9 SiO2 film (insulating film)
10 signal processing circuit 13 cantilever

Claims (4)

Method for manufacturing a physical quantity sensor having a first layer, a second layer made of an insulator is applied on the first layer, and a third layer is disposed on the second layer. At
Depositing a first layer structure on said third layer;
Structuring the first layer structure in the form of the physical quantity sensor;
Etching the third layer using the first layer structure as a mask to form a physical quantity sensor including a fixed portion, a displaceable weight portion, and a conductive path from the third layer;
Removing the second layer below the displaceable weight portion;
A method for manufacturing a physical quantity sensor, comprising: 2. The method according to claim 1, further comprising a step of forming a wiring layer on the conductive path. Prepare a first layer made of a silicon substrate,
Disposing a second layer made of an insulating layer on the first layer;
Disposing a third layer made of a silicon layer on the second layer;
Disposing a first pattern layer having a shape of a physical quantity sensor on the third layer;
Using the first pattern layer as a mask, a predetermined region of the third layer is removed by etching, and the fixed electrode portion and the movable electrode portion moving in one direction in parallel with the surface of the first layer; Forming a sensor unit having
Forming an electric conductor portion made of metal on the fixed electrode portion and the movable electrode portion on substantially the same surface,
Removing at least the second layer below the movable region of the movable electrode portion,
The method of manufacturing a semiconductor dynamic quantity sensor, wherein the fixed electrode portion and the movable electrode portion are electrically insulated from each other by the second layer with respect to the first layer. 4. The semiconductor mechanics according to claim 3, wherein, at the same time as forming the sensor section, a predetermined area around the sensor section is removed by etching to form a peripheral section electrically insulated from the sensor section by an insulator. Manufacturing method of quantity sensor.

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