JP3570530B2 - Manufacturing method of SOI wafer - Google Patents
Manufacturing method of SOI wafer Download PDFInfo
- Publication number
- JP3570530B2 JP3570530B2 JP13072596A JP13072596A JP3570530B2 JP 3570530 B2 JP3570530 B2 JP 3570530B2 JP 13072596 A JP13072596 A JP 13072596A JP 13072596 A JP13072596 A JP 13072596A JP 3570530 B2 JP3570530 B2 JP 3570530B2
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- Prior art keywords
- wafer
- layer
- soi wafer
- gettering
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- Expired - Lifetime
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- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000010410 layer Substances 0.000 claims description 45
- 238000005247 gettering Methods 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 9
- 238000005498 polishing Methods 0.000 claims description 4
- 239000002344 surface layer Substances 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 57
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 238000011109 contamination Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000008119 colloidal silica Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Element Separation (AREA)
Description
【０００１】
【発明の属する技術分野】
この発明はゲッタリング能力を有するＳＯＩ（silicon-on-insulator）ウェーハの製造方法に関する。
【０００２】
【従来の技術】
従来のこの種のイントリンシックゲッタリング層を有するＳＯＩウェーハとしては以下のものが知られていた。すなわち、活性層ウェーハと支持基盤ウェーハとの間に絶縁膜を介してポリシリコン層を挟んでいた。張り合わせ後のＳＯＩウェーハにあっては、このポリシリコン層をゲッタリング層として活用していた。
【０００３】
【発明が解決しようとする課題】
しかしながら、このような従来のＳＯＩウェーハでは、熱処理過程でポリシリコンの粒径が変化し、いったん捕獲した汚染を再放出してしまっていた。また、熱処理によりＳＯＩウェーハが全体として反ってしまっていた。また、このポリシリコン層を研磨することが困難であり、張り合わせＳＯＩウェーハの作製に困難さが生じていた。さらに、形成されたポリシリコン層の厚さは１〜２μｍ程度であって、ゲッタリングサイトが少なくそのゲッタリング能力が低いという問題もあった。
【０００４】
【発明の目的】
そこで、この発明の目的は、汚染を再放出するおそれがないＳＯＩウェーハを提供することである。また、この発明の別の目的は、ＳＯＩウェーハの反りを低減することである。また、この発明の目的は、ゲッタリング層を備えたＳＯＩウェーハの製造を容易に行うことである。さらに、この発明の目的は、ゲッタリングサイトを十分に確保することができたＳＯＩウェーハおよびその製造方法を提供することである。
【０００５】
【課題を解決するための手段】
【０００６】
【０００７】
請求項１に記載の発明は、支持基盤用ウェーハの表層部にＩＧ処理を施す工程と、この支持基盤用ウェーハのＩＧ処理を施した表面層を研磨しゲッタリング層を露出する工程と、この露出したゲッタリング層を、絶縁膜を挟んで、活性層用ウェーハの表面に重ね合わせることにより、支持基盤用ウェーハと活性層用ウェーハとを張り合わせる工程を含むＳＯＩウェーハの製造方法である。
【０００８】
【０００９】
【作用】
請求項１に記載の発明に係る製法により製造されたＳＯＩウェーハにあっては、絶縁層に接してゲッタリング層が形成されているため、絶縁層とゲッタリング層との間にＤＺ（denuded-zone）層を介在させた場合に比較して活性層表面の汚染をより低減することができる。ＤＺ層の幅が大きいほど活性層の汚染が増加するものである。そして、この発明に係るＳＯＩウェーハではゲッタリング層は充分なゲッタリング能力を得ることができる。
【００１０】
請求項１に記載の発明にあっては、ゲッタリング層を露出させ、かつ、この表面を平坦化した後、所定の張り合わせを行う。この結果、ゲッタリング能力が高いＳＯＩウェーハを容易に作製することができる。半導体ウェーハ、特にシリコンウェーハはポリシリコン層に比べて研磨が容易だからである。また、反りが少ないＳＯＩウェーハを製造することができる。ポリシリコン層をゲッタリング層として使用していないからである。また、その後の工程などでのゲッタリング層からの汚染の再放出を防ぐことができる。
【００１１】
【発明の実施の形態】
以下、この発明の一実施例を図面を参照して説明する。図１はこの発明の一実施例に係るＳＯＩウェーハを製造する各工程を順次示すその断面図である。
【００１２】
まず、２枚のシリコンウェーハを準備する。例えばいずれも同一の条件で製造されたウェーハ（６インチ・ＣＺ・ＰＷ）を準備する。一方のウェーハが支持基盤用ウェーハＢであり、他方が活性層用Ａとなる。活性層用ウェーハＡの表面には所定の厚さにシリコン酸化膜ＳｉＯ２を形成しておく。そして、支持基盤用ウェーハＢの鏡面に所定条件でレーザ光を照射する。例えば赤外レーザでその電源入力は（１００Ｖ×１０〜２０Ａ）のものを用いる。この結果、このシリコンウェーハＢにはその表面から所定深さ範囲Ｇに一定のゲッタリングサイトとなる欠陥（例えば酸素析出物）が形成されることとなる。同図（Ａ）はこの状態を示している。
【００１３】
次に、所定の研磨機を用い、所定の条件（例えば研磨剤としてはコロイダルシリカを用いる）でこのシリコンウェーハＢのレーザ光照射面を所定深さだけ鏡面研磨する。少なくとも５μｍの研磨を行う。この結果、シリコンウェーハ表面には平坦なゲッタリング層が露出することとなる。同図（Ｂ）はこの状態を示している。
【００１４】
次に、このゲッタリング層表面を、上記シリコン酸化膜に重ね合わせてシリコンウェーハＡ，Ｂ同士を密着させる。室温、大気圧下で行う。同図（Ｃ）および（Ｄ）はこの状態を示している。そして、この後所定の張り合わせ熱処理を行う。例えば８００℃で加熱する。
【００１５】
さらに、この後、活性層用ウェーハＡの表面に所定の研削・研磨を施すことにより、所定のＳＯＩウェーハを得るものである。同図（Ｅ）はこの状態を示している。
【００１６】
なお、ゲッタリング層の形成としては上記レーザ光の照射に限らず、サンドブラスト法その他を用いることができる。
【００１７】
図２はこの発明の一実施例に係るＳＯＩウェーハでのゲッタリング能力を説明するためのグラフである。ポリシリコン層を介在させず、そのＤＺ幅が０μｍ，１０μｍ，２０μｍ，３０μｍの場合のＳＯＩウェーハをそれぞれ作製する。そして、各ウェーハ表面をＣｕ汚染（１０１３／ｃｍ２）した後、さらに１１００℃，２時間での熱処理を行う。ここで、その表面のＣｕ濃度を測定した結果を図２に示す。表面汚染の測定は公知方法で行う。本発明に係るＤＺ幅が０μｍのＳＯＩウェーハのほうが、他のウェーハに比べてＣｕ汚染が低減されていることが明らかである。
【００１８】
図３はこの発明の一実施例に係るＳＯＩウェーハの反りを説明するためのグラフである。上述の方法で作製された本発明に係るＤＺ幅が０μｍのＳＯＩウェーハのそりを、２μｍの厚さのポリシリコン層を介在させた従来のＳＯＩウェーハのそれと比較すると、そりが大幅に低減されていることは明らかである。また、本発明に係るＳＯＩウェーハでレーザ照射に係るものの反りについても、同様に従来比で大幅に低減されていることが明らかである。
【００１９】
【効果】
この発明に係るＳＯＩウェーハにあっては、汚染を再放出するおそれがない。また、ＳＯＩウェーハの反りを低減することができる。また、ゲッタリング層を備えたＳＯＩウェーハの製造を容易に行うことがきる。さらに、ＳＯＩウェーハにおいてゲッタリングサイトを十分に確保することができる。充分なゲッタリング能力を備えたＳＯＩウェーハを製造することができる。
【図面の簡単な説明】
【図１】この発明の一実施例に係るＳＯＩウェーハの製造方法を示す図である。
【図２】この発明の一実施例に係るＳＯＩウェーハのゲッタリング能力を示すグラフである。
【図３】この発明の一実施例に係るＳＯＩウェーハのそりを示すグラフである。
【符号の説明】
Ａ 活性層用ウェーハ、
Ｂ 支持基板用ウェーハ、
Ｇ ゲッタリング層、
ＳｉＯ２ 二酸化シリコン層（絶縁層）。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing an SOI (silicon-on-insulator) wafer having gettering ability.
[0002]
[Prior art]
As a conventional SOI wafer having this kind of intrinsic gettering layer, the following is known. That is, the polysilicon layer is interposed between the active layer wafer and the support base wafer via the insulating film. In the bonded SOI wafer, this polysilicon layer was utilized as a gettering layer.
[0003]
[Problems to be solved by the invention]
However, in such a conventional SOI wafer, the grain size of polysilicon changes during the heat treatment process, and the once captured contamination is re-emitted. Moreover, the SOI wafer was warped as a whole due to the heat treatment. Further, it is difficult to polish this polysilicon layer, and it has been difficult to manufacture a bonded SOI wafer. Further, the thickness of the formed polysilicon layer is about 1 to 2 μm, and there is a problem that the number of gettering sites is small and the gettering ability is low.
[0004]
[Object of the invention]
Therefore, an object of the present invention is to provide an SOI wafer that does not have a risk of re-release of contamination. Another object of the present invention is to reduce warpage of an SOI wafer. Another object of the present invention is to easily manufacture an SOI wafer provided with a gettering layer. It is a further object of the present invention to provide an SOI wafer capable of sufficiently securing a gettering site and a method for manufacturing the same.
[0005]
[Means for Solving the Problems]
[0006]
[0007]
The invention according to claim 1 includes a step of subjecting the surface layer portion of the support base wafer to IG processing, a step of polishing the IG treated surface layer of the support base wafer to expose the gettering layer , This is a method for manufacturing an SOI wafer including a step of laminating a wafer for a support base and a wafer for an active layer by superposing the exposed gettering layer on the surface of the active layer wafer with an insulating film interposed therebetween.
[0008]
[0009]
[Action]
In the SOI wafer manufactured by the manufacturing method according to the first aspect of the present invention, since the gettering layer is formed in contact with the insulating layer, a DZ (denuded layer) is formed between the insulating layer and the gettering layer. As a result, contamination of the active layer surface can be further reduced as compared with the case where a zone) layer is interposed. As the width of the DZ layer increases, the contamination of the active layer increases. In the SOI wafer according to the present invention, the gettering layer can obtain a sufficient gettering ability.
[0010]
According to the first aspect of the present invention, after exposing the gettering layer and flattening the surface, predetermined bonding is performed. As a result, an SOI wafer having high gettering ability can be easily manufactured. This is because a semiconductor wafer, particularly a silicon wafer, is easier to polish than a polysilicon layer. Further, an SOI wafer with less warpage can be manufactured. This is because the polysilicon layer is not used as a gettering layer. Further, it is possible to prevent the release of contamination from the gettering layer in a subsequent step or the like.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view sequentially showing each step of manufacturing an SOI wafer according to one embodiment of the present invention.
[0012]
First, two silicon wafers are prepared. For example, wafers (6 inches / CZ / PW) manufactured under the same conditions are prepared. One wafer is the wafer B for the support base, and the other is the wafer A for the active layer. The surface of the active layer wafer A previously formed silicon oxide film SiO 2 to a predetermined thickness. Then, the mirror surface of the support base wafer B is irradiated with laser light under predetermined conditions. For example, an infrared laser whose power input is (100 V × 10 to 20 A) is used. As a result, defects (for example, oxygen precipitates) serving as constant gettering sites are formed in a predetermined depth range G from the surface of the silicon wafer B. FIG. 3A shows this state.
[0013]
Next, using a predetermined polishing machine, the laser light irradiation surface of the silicon wafer B is mirror-polished to a predetermined depth under predetermined conditions (for example, colloidal silica is used as an abrasive). Polish at least 5 μm. As a result, a flat gettering layer is exposed on the surface of the silicon wafer. FIG. 7B shows this state.
[0014]
Next, the silicon wafers A and B are brought into close contact with each other by superposing the surface of the gettering layer on the silicon oxide film. Perform at room temperature and atmospheric pressure. FIGS. 3C and 3D show this state. Thereafter, a predetermined bonding heat treatment is performed. For example, heating at 800 ° C.
[0015]
Further, thereafter, a predetermined SOI wafer is obtained by subjecting the surface of the active layer wafer A to predetermined grinding and polishing. FIG. 7E shows this state.
[0016]
Note that the formation of the gettering layer is not limited to the above laser beam irradiation, and a sand blast method or the like can be used.
[0017]
FIG. 2 is a graph for explaining the gettering ability of the SOI wafer according to one embodiment of the present invention. SOI wafers having DZ widths of 0 μm, 10 μm, 20 μm, and 30 μm without a polysilicon layer interposed therebetween are manufactured. After the surface of each wafer is contaminated with Cu (10 13 / cm 2 ), a heat treatment is further performed at 1100 ° C. for 2 hours. Here, the result of measuring the Cu concentration on the surface is shown in FIG. The measurement of surface contamination is performed by a known method. It is clear that the SOI wafer having a DZ width of 0 μm according to the present invention has reduced Cu contamination as compared with other wafers.
[0018]
FIG. 3 is a graph for explaining the warpage of the SOI wafer according to one embodiment of the present invention. When the warp of the SOI wafer having a DZ width of 0 μm according to the present invention manufactured by the above-described method is compared with that of a conventional SOI wafer having a 2 μm thick polysilicon layer interposed therebetween, the warp is significantly reduced. It is clear that. It is also apparent that the warpage of the laser irradiation in the SOI wafer according to the present invention is also significantly reduced as compared with the conventional case.
[0019]
【effect】
In the SOI wafer according to the present invention, there is no possibility of releasing the contamination again. Further, warpage of the SOI wafer can be reduced. In addition, it is possible to easily manufacture an SOI wafer having a gettering layer. Further, a gettering site can be sufficiently secured in the SOI wafer. An SOI wafer having a sufficient gettering ability can be manufactured.
[Brief description of the drawings]
FIG. 1 is a diagram showing a method for manufacturing an SOI wafer according to one embodiment of the present invention.
FIG. 2 is a graph showing the gettering ability of an SOI wafer according to one embodiment of the present invention.
FIG. 3 is a graph showing warpage of an SOI wafer according to one embodiment of the present invention.
[Explanation of symbols]
A wafer for active layer,
B Support substrate wafer,
G gettering layer,
SiO 2 silicon dioxide layer (insulating layer).
Claims (1)
この支持基盤用ウェーハのＩＧ処理を施した表面層を研磨しゲッタリング層を露出する工程と、
この露出したゲッタリング層を、絶縁膜を挟んで、活性層用ウェーハの表面に重ね合わせることにより、支持基盤用ウェーハと活性層用ウェーハとを張り合わせる工程を含むＳＯＩウェーハの製造方法。Performing an IG process on the surface layer of the support base wafer;
Polishing the surface layer of the support base wafer that has been subjected to the IG treatment to expose the gettering layer ;
A method for producing an SOI wafer, comprising a step of laminating the exposed base gettering layer and the active layer wafer by superposing the exposed gettering layer on the surface of the active layer wafer with an insulating film interposed therebetween.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13072596A JP3570530B2 (en) | 1996-04-26 | 1996-04-26 | Manufacturing method of SOI wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13072596A JP3570530B2 (en) | 1996-04-26 | 1996-04-26 | Manufacturing method of SOI wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09293845A JPH09293845A (en) | 1997-11-11 |
| JP3570530B2 true JP3570530B2 (en) | 2004-09-29 |
Family
ID=15041146
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13072596A Expired - Lifetime JP3570530B2 (en) | 1996-04-26 | 1996-04-26 | Manufacturing method of SOI wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3570530B2 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6093623A (en) | 1998-08-04 | 2000-07-25 | Micron Technology, Inc. | Methods for making silicon-on-insulator structures |
| US6423613B1 (en) * | 1998-11-10 | 2002-07-23 | Micron Technology, Inc. | Low temperature silicon wafer bond process with bulk material bond strength |
| JP4556255B2 (en) * | 1998-12-07 | 2010-10-06 | 株式会社デンソー | Manufacturing method of semiconductor device |
| US6852167B2 (en) | 2001-03-01 | 2005-02-08 | Micron Technology, Inc. | Methods, systems, and apparatus for uniform chemical-vapor depositions |
| KR100543252B1 (en) | 2001-05-29 | 2006-01-20 | 신닛뽄세이테쯔 카부시키카이샤 | SOI substrate |
| US7589029B2 (en) | 2002-05-02 | 2009-09-15 | Micron Technology, Inc. | Atomic layer deposition and conversion |
| US7160577B2 (en) | 2002-05-02 | 2007-01-09 | Micron Technology, Inc. | Methods for atomic-layer deposition of aluminum oxides in integrated circuits |
| US7927948B2 (en) | 2005-07-20 | 2011-04-19 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
| US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
| JP2010258083A (en) | 2009-04-22 | 2010-11-11 | Panasonic Corp | SOI wafer, method for manufacturing the same, and method for manufacturing a semiconductor device |
| DE102014219648A1 (en) | 2014-09-29 | 2015-10-15 | Carl Zeiss Smt Gmbh | Method for producing a mirror element |
-
1996
- 1996-04-26 JP JP13072596A patent/JP3570530B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09293845A (en) | 1997-11-11 |
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