JP3543725B2 - Packet switching device and packet switching method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a packet switching device, for example, an ATM (Asynchronous Transfer Mode) for switching between a specific input port and an output port using packet communication technology, a packet switching device applied to the Internet, and the like. It relates to a packet switching method.
[0002]
[Prior art]
2. Description of the Related Art Demand for packet switching devices has been increasing with the recent spread of the Internet. In addition, with the increase in demand, an exchange having a large capacity and capable of guaranteeing QoS (Quality of Service) is required. As means for realizing this large-capacity exchange, an input-buffer-type exchange that can suppress the memory access speed and the required buffer amount is considered to be promising.
[0003]
However, in the case of the input buffer type exchange, the HOL (Head of Head) cannot be transmitted until the packet of the rank reaching the head of the buffer is transmitted, even if the target output route is empty. Line) There is a problem that blocking occurs and throughput decreases.
[0004]
In order to avoid this problem, a concept has been proposed in which the input buffer side has a FIFO (First In First Out) for each output route and each QoS class. In realizing this proposal, a scheduler for performing scheduling is required so that data transmitted from an input buffer does not collide between output routes. Here, in order to guarantee QoS, a configuration having a scheduler for each QoS class as shown in FIG. 5 has been proposed. In this conventional example, two schedulers 30 and 31 are provided depending on the priority level, and a transfer request signal from a FIFO with a higher priority is transmitted by one scheduler unit 30 to a transfer request signal from a FIFO with a lower priority. The signals are processed by the other scheduler unit 31 respectively.
[0005]
First, scheduling is performed by one scheduler unit 30. Based on the result of the scheduling, the transfer request signal from the FIFO with the lower priority is masked for the route to which the scheduler unit 30 has already issued the transfer permission signal.
[0006]
Second, scheduling is performed by the other scheduler unit 31 on the transfer request signal that has been subjected to the mask processing. As a result, for a route for which permission has been obtained on the high priority side, no permission is obtained on the low priority side, and QoS is guaranteed.
[0007]
[Problems to be solved by the invention]
However, the above-described conventional packet switching device and packet switching method have the following problems. The first problem is that a scheduler unit is required for each QoS class, and the scale of the scheduler unit is increased.
[0008]
As means for realizing a large-capacity exchange, there is a tendency to increase the rate of lines and increase the number of routes. Due to this increase, the scheduler unit is required to realize extremely complicated processing at high speed, and as a result, the scale of the scheduler unit must be increased. Here, having a scheduler unit for each class requires a considerable scale and is difficult to realize.
[0009]
The second problem is that control between scheduler units is required. As described above, in order to guarantee the QoS, it is necessary to start the process from the scheduler unit 30 having a higher priority and reflect the result of the scheduling to the process of the scheduler unit 31 having a lower priority. For this reason, it is necessary to perform control between scheduler units for each class. When a configuration of one scheduler is used for one class, it is necessary to control the scheduler units for the number of classes to be supported, which further complicates the processing and increases the scale.
[0010]
An object of the present invention is to provide a packet switching device and a packet switching method that guarantee QoS with a small-scale scheduler.
[0011]
More specifically, the present invention uses a concept in which a block is formed from a plurality of packets described in Japanese Patent Application No. 11-034409 of the prior application by the same applicant, and the block is used as a unit of data transmission. Accordingly, it is an object of the present invention to provide a packet switching device and a packet switching method that solve the problems of the above-mentioned conventional methods.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, a packet switching device according to the present invention forms a block in order from a packet having a high priority corresponding to an input line and destined for the same output route, and assembles data formed by assembling the formed block. An input buffer unit for transmitting the data, a scheduler unit for adjusting the contention of the transmitted data, and a switch unit for switching the connection of the data to the output line based on the contention adjustment. The contention adjustment is performed based on the transfer request signal, and the result of the contention adjustment is sent to the input buffer unit as a transfer permission signal, and at the same time, the connection address signal is sent to the switch unit.
[0013]
Further, in the packet switching apparatus according to the present invention, the input line and the output line are N (where N is a positive integer of 2 or more) lines, and the switch unit has N × N lines corresponding to N input lines and output lines. It is a switcher of N lines.
[0014]
Further, in the packet switching apparatus according to the present invention, the input buffer unit includes a FIFO ( First In First Out ) for each output route and each QoS class , a packet distribution unit, an input buffer control unit, and a block generation unit. The packet distribution unit distributes a packet input from an input line to a corresponding FIFO based on information of a header attached to the packet, and the input buffer control unit manages the number of packets stored in each FIFO, A transfer request signal is sent to the scheduler unit, and when a transfer permission signal is received from the scheduler unit, a block generation permission signal is sent to the block generation unit, and the block generation unit receives the block generation permission signal, Is constructed and transmitted to the scheduler unit.
[0015]
Further, a packet switching method according to the present invention is a packet switching method in a packet switching device having an input buffer unit, a switch unit, and a scheduler unit, wherein the input buffer unit corresponds to an input line and has the same output. An input buffer step of forming a block in order from a packet having a higher priority addressed to a route, and sending data obtained by assembling the formed block to a scheduler section, and a scheduler section for adjusting contention of the sent data by the scheduler section And a switching step in which the switch unit switches the connection of the data to the output line based on the contention adjustment. The scheduler unit includes a scheduler unit in which the scheduler unit adjusts the data contention based on a transfer request signal from the input buffer unit. And transmits the result of the contention adjustment to the input buffer unit as a transfer permission signal, and at the same time, Characterized in that it sends a signal to the switch unit.
[0016]
Also, in the packet switching method according to the present invention, the input line and the output line are N (where N is a positive integer of 2 or more) lines, and the switch step is such that the switch section includes N input lines and output lines. The switching of the N × N line corresponding to the above is performed.
[0017]
In the packet switching method according to the present invention, the input buffer unit includes a FIFO ( First In First Out ) for each output route and each QoS class , a packet distribution unit, an input buffer control unit, and a block generation unit. In the input buffer step, the packet distribution unit distributes the packet input from the input line to the corresponding FIFO based on the information of the header accompanying the packet, and the input buffer control unit determines the number of packets stored in each FIFO. And sends a transfer request signal to the scheduler unit, and upon receiving a transfer permission signal from the scheduler unit, sends a block generation permission signal to the block generation unit, and the block generation unit Receiving data, constructing data, and transmitting the data to the scheduler unit.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, an embodiment of a packet switching device and a packet switching method according to the present invention will be described in detail with reference to the accompanying drawings. 1 to 4, there is shown an embodiment of a packet switching device and a packet switching method according to the present invention. FIG. 1 is a diagram for explaining the overall configuration of a packet switching device and a packet switching method according to the present invention. FIG. 2 is a diagram illustrating a more detailed configuration example of the input buffer unit. FIG. 3 shows an example of a block configuration of the block generator, and FIG. 4 shows an example of a block format of data output from the block generator.
[0019]
(Constitution)
FIG. 1 is a diagram showing the basic configuration of a packet switching apparatus and a packet switching method according to the present invention. The packet switching device and the packet switching method according to the present embodiment are input buffer type switching devices, and include input buffer units 1-1 to 1-N corresponding to respective input lines and a scheduler unit 6 for performing contention arbitration. The scheduler unit 6 performs scheduling based on the transfer request signals 2-1 to 2-N from the input buffer units 1-1 to 1-N, and inputs the scheduling results as transfer permission signals 3-1 to 3-N. The connection address signals 5-1 to 5-N are sent to the buffer units 1-1 to 1-N, and simultaneously the connection address signals 5-1 to 5-N are sent to the N × N switch unit 4.
[0020]
Next, a detailed configuration of the input buffer units 1-1 to 1-N will be described with reference to FIG. 2 illustrating a more detailed configuration example of the input buffer unit 1-1. The input buffer units 1-2 to 1-N have the same configuration as the input buffer units 1-1 to 1-N. The input buffer unit 1-1 includes FIFO (First In First Out) 1-11H to 1-1NL for each output route and for each QoS class, a packet distribution unit 10, an input buffer control unit 12, and a block generation unit 15. You.
[0021]
The packet distribution unit 10 distributes a packet input from the input line 1 to corresponding FIFOs 1-11H to 1-1NL based on information of the header. The input buffer control unit 12 manages the number of packets stored in each FIFO, and sends a transfer request signal 2-1 to the scheduler unit 6. When the transfer permission signal 3-1 is received from the scheduler section 6, the block generation permission signal 14 is sent to the block generation section 15. When receiving the block generation permission signal 14, the block generation unit 15 constructs data in which the blocks shown in FIG. 4 are assembled, and sends out the constructed data.
[0022]
FIG. 3 shows a configuration of a block transmitted as data. The block is composed of packets with different QoS destined for the same output route. However, in order to guarantee QoS, it is assumed that blocks are formed in order from a packet having a higher priority.
[0023]
The packet switching apparatus and the packet switching method described above have a scale in which a block in which a plurality of packets are combined is used as a data transmission unit, and packets having different QoS (Quality of Service) are transmitted to the same output route as one block. The QoS is guaranteed by a small scheduler.
[0024]
Transfer request signals 2-1 to 2-N are sent from the input buffer units 1-1 to 1-N of the packet switching apparatus and the packet switching method of the present embodiment to the scheduler unit 6. The scheduler 6 performs scheduling. As a result, the transfer enable signals 3-1 to 3-N are input to the input buffers 1-1 to 1-N, and the connection address signals 5-1 to 5-N are supplied to the N × N switch 4. N are sent out. The input buffer units 1-1 to 1-N that have received the transfer permission generate the blocks shown in FIG. 4 by the block generation unit 15 in FIG. 3 and send them as data. This will be described in detail below.
[0025]
(motion)
The operation of the embodiment of the present invention will be described with reference to FIGS.
First, the operation of the input buffer unit will be described with reference to FIG. 2 showing the configuration of the input buffer unit 1-1 of FIG. 1 as an example. Packets input from the input line 1 are stored in the corresponding FIFOs of the FIFOs 1-11H to 1-1NL for each output route and for each QoS class by the packet distribution unit 10 based on the information of the header. Here, the packet distribution unit 10 sends a packet management signal 11 indicating that the packet has been newly stored to the input buffer control unit 12.
[0026]
The input buffer control unit 12 has a map corresponding to each FIFO, and stores the number of stored packets. The timing at which the number of packets stored in each FIFO reaches the beginning of the block is set as a transfer request condition. If any of the high / low priority FIFOs addressed to the same route satisfies this condition, the scheduler unit 6 in FIG. Then, a transfer request signal 2-1 for each output route is transmitted. The “timing to reach the beginning of the block” is, for example, 1, K + 1, 2 × K + 1,..., When the number of unit packets in one block is “K”.
[0027]
The scheduler unit 6 in FIG. 1 receives transfer request signals 2-1 to 2-N from the input buffer units 1-1 to 1-N corresponding to each input line, and receives from each of the input buffer units 1-1 to 1-N. Scheduling is performed so that transmitted data does not collide. As a result of this scheduling, transfer permission signals 3-1 to 3-N are sent to input buffer units 1-1 to 1-N. At the same time, connection address signals 5-1 to 5-N are also sent to the N × N switch unit 4 in FIG.
[0028]
Here, the transfer permission signals 3-1 to 3-N represent output route addresses to which data is transmitted, and the connection address signals 5-1 to 5-N are reception destinations in each output route. It represents a certain input route address. The N × N switch unit 4 switches the data transmitted from the input buffer units 1-1 to 1-N based on the connection address signals 5-1 to 5-N, and transmits the data to the corresponding output line.
[0029]
In FIG. 2, the input buffer control unit 12 that has received the transfer permission signal 3-1 from the scheduler unit 6 sends a block generation permission signal 14 to the block generation unit 15 when permission is obtained.
[0030]
FIG. 3 shows a detailed view of the high-priority FIFO 1-11H, the low-priority FIFO 1-11L, and the block generation unit 15, taking the FIFO addressed to the output route 1 in FIG. 2 as an example. FIG. 4 shows a configuration diagram of the generated data block.
[0031]
In FIG. 3, upon receiving the block generation permission signal 14, the block generation unit 15 forms a data block from the packets stored in the high-priority FIFO 1-11H and the low-priority FIFO 1-11L. At the beginning of the block, information such as the address of an output route serving as a data destination is added. When a block is formed, packets are assembled in order from the packets H1 to H3 stored in the high-priority FIFO 1-11H in order to guarantee QoS. When the number of packets of the high-priority FIFO 1-11H is less than the number of packets per block “K”, a block is formed by supplementing the packets stored in the low-priority FIFO 1-11L. At this time, the number of packets forming a block is sent to the input buffer control unit 12 in FIG. 2 as a block configuration signal 13 for each of the high-priority FIFO 1-11H and the low-priority FIFO 1-11L. The input buffer control unit 12 updates the value of the map that manages the number of stored packets based on this signal.
[0032]
(effect)
A first advantage of the above embodiment is that a QoS class-specific scheduler is not required. Therefore, the size of the scheduler can be considerably reduced. The reason is that, by processing packets having different QoS as the same data, the scheduler can be configured without being aware of the class.
[0033]
The second effect is that the processing time of the input buffer and the scheduler can be extended. Therefore, the processing of the input buffer and the scheduler becomes easy, and the scale can be reduced. The reason is that, since a block composed of a plurality of packets is processed as a unit of data transmission, data transmission in the input buffer and scheduling in the scheduler need only be processed in the time required for block transmission. This is because there is a considerable time margin as compared with the case of processing as a unit.
[0034]
A third effect is that high throughput can be obtained in traffic. The reasons are as follows. Considering that blocks are formed from a single QoS class, in order to guarantee the QoS, even if the number of packets of the high-priority FIFO is less than the number of packets per block, they must be transmitted one after another. In this case, data is transmitted to a portion less than the block by filling empty packets or the like, and the average output delay from the exchange increases. On the other hand, in the present embodiment, by forming packets having different QoS as one block, the number of packets forming a block can be made closer to the number of unit packets, and the above-mentioned drawback due to the block unit is compensated. , High throughput can be obtained.
[0035]
(Other embodiments)
Another embodiment of the present invention will be described.
In FIG. 2, a transfer request signal 2-1 to the scheduler unit 6 is transmitted when any of the number of high priority FIFO 1-11H and low priority FIFO 1-11L packets addressed to the same output route satisfies the condition. did. Here, an example is considered in which the condition for transmitting the transfer request signal 2-1 is only when the number of packets stored in the high-priority FIFO 1-11H satisfies the condition. However, in this case, when no packet is stored in the high-priority FIFO 1-11H destined for the output route 1, the transfer request signal 2-1 is not sent to the scheduler unit 6, and the packet is stored in the low-priority FIFO 1-11L. It is possible that the transmitted packet is not transmitted. To avoid this problem, if no packets are stored in the high-priority FIFO 1-11H and the number of packets stored in the low-priority FIFO 1-11L exceeds a certain threshold, the transfer request signal 2 Processing for transmitting -1 is required.
[0036]
Another embodiment will be described.
In the present invention, two classes of QoS have been specifically described in the embodiments. Here, a case where the QoS of the Z (Z> 2) class is guaranteed will be considered. It is assumed that one scheduler performs scheduling on the basis of a transfer request signal that extends over two classes, and that the scheduling process proceeds in descending order of priority using a Z / 2 scheduler. In this case, control between the Z / 2 scheduler units is required, but the number of scheduler units can be reduced to half that of the case where one scheduler unit is used for one class. In this way, by making the transfer request signal processed by the scheduler unit span a plurality of classes (the number of classes is arbitrary), a further reduction in the scale of the scheduler unit can be expected.
[0037]
The above embodiment is an example of a preferred embodiment of the present invention. However, the present invention is not limited to this, and various modifications can be made without departing from the scope of the present invention.
[0038]
【The invention's effect】
As is clear from the above description, the packet switching apparatus and the packet switching method of the present invention provide data obtained by assembling blocks in which blocks corresponding to an input line and formed in the order of higher priority packets destined for the same output route are formed. The contention is performed, the contention of the transmitted data is arbitrated, and the connection of the data to the output line is switched based on the contention adjustment. This eliminates the need for a QoS class-specific scheduler while guaranteeing the QoS, reduces the size of the scheduler, and enables the scheduler to be configured without considering the class. Further, the processing time of the input buffer and the scheduler can be made longer, the processing of the input buffer and the scheduler can be facilitated, and high throughput in traffic can be obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a packet switching device and a packet switching method of the present invention.
FIG. 2 is a more detailed block diagram of an input buffer unit.
FIG. 3 is a more detailed block diagram 2 of an input buffer unit.
FIG. 4 is a diagram illustrating a configuration example of a block format.
FIG. 5 is a block diagram showing a configuration example of a conventional packet switching measure.
[Explanation of symbols]
1-1 to 1-N input buffer unit 2-1 to 2-N transfer request signal 3-1 to 3-N transfer enable signal 4 N × N switch unit 5-1 to 5-N connection address signal 6 scheduler unit 10 Packet distribution unit 11 Packet management signal 12 Input buffer control unit 13 Block configuration signal 14 Block generation permission signal 15 Block generation unit 1-11H to 1-1NH High priority FIFO
1-11L to 1-1NL Low priority FIFO
30, 31 Scheduler section

Claims (6)

An input buffer unit for forming a block in order from a packet having a higher priority corresponding to the input line and destined for the same output route, and transmitting data obtained by assembling the formed block;
A scheduler unit for adjusting contention of the transmitted data;
Anda switch section for switching the connection to the output line of the data based on the contention adjustment,
The scheduler unit performs contention adjustment of the data based on a transfer request signal from the input buffer unit, the result of the conflict adjustment sent to the input buffer unit as the transfer permission signal, simultaneously the connection address signal switch A packet switching device for transmitting the packet to a communication unit. The input line and the output line are N (where N is a positive integer of 2 or more) lines, and the switch unit is an N × N line switch corresponding to the N input lines and output lines. The packet switching device according to claim 1, wherein: The input buffer unit includes a first in first out (FIFO) for each output route and a QoS class, a packet distribution unit, an input buffer control unit, and a block generation unit.
The packet distribution unit distributes a packet input from the input line to the corresponding FIFO based on information of an accompanying header of the packet ,
The input buffer control unit manages the number of accumulated packets in each FIFO, and sending the transfer request signal to the scheduler section, upon receiving the transfer permission signal from the scheduler unit, the block generation permission signal Sent to the block generator,
The block generator receives the block generation permission signal, packet switching apparatus according to claim 1, wherein building the data, wherein the sending to the scheduler section. An input buffer unit, a switch unit, a packet switching method in a packet switching device having a scheduler unit,
An input buffer step in which the input buffer unit corresponds to an input line, forms a block in order from a packet having a high priority destined for the same output route, and sends data obtained by assembling the formed block to the scheduler unit ; ,
A scheduler step in which the scheduler unit performs contention adjustment of the transmitted data;
The switch unit performs a switching step of switching connection to an output line of the data based on the competition adjustment ,
The scheduler process, the scheduler unit performs the conflict adjustment of the data transfer request signal based on from the input buffer unit, and sends the result of the conflict adjustment to the input buffer unit as the transfer permission signal, connected at the same time A packet switching method comprising transmitting an address signal to the switch unit . The input line and the output line are N (where N is a positive integer of 2 or more) lines, and the switch step is such that the switch section includes an N × N line corresponding to the N input lines and output lines. 5. The packet switching method according to claim 4 , wherein the switching is performed . The input buffer unit includes a FIFO (First In First Out) for each output route and a QoS class, a packet distribution unit, an input buffer control unit, and a block generation unit .
In the input buffer step, the packet distribution unit distributes a packet input from the input line to a corresponding FIFO based on information of a header attached to the packet ,
The input buffer controller manages the number of accumulated packets in each FIFO, and sending the transfer request signal to the scheduler section, upon receiving the transfer permission signal from the scheduler unit, the block generation permission signal sent to the block generator,
5. The packet switching method according to claim 4 , wherein the block generation unit receives the block generation permission signal, constructs the data , and sends the data to the scheduler unit .

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