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JP3543251B2 - IC chip bonding equipment - Google Patents

IC chip bonding equipment Download PDF

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Publication number
JP3543251B2
JP3543251B2 JP02021797A JP2021797A JP3543251B2 JP 3543251 B2 JP3543251 B2 JP 3543251B2 JP 02021797 A JP02021797 A JP 02021797A JP 2021797 A JP2021797 A JP 2021797A JP 3543251 B2 JP3543251 B2 JP 3543251B2
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Japan
Prior art keywords
chip
circuit board
another
electrode pads
electrode pad
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Expired - Fee Related
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JP02021797A
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Japanese (ja)
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JPH10223680A (en
Inventor
和孝 柴田
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP02021797A priority Critical patent/JP3543251B2/en
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to KR10-1998-0707403A priority patent/KR100522223B1/en
Priority to PCT/JP1998/000281 priority patent/WO1998033217A1/en
Priority to KR10-2004-7000090A priority patent/KR100467946B1/en
Priority to EP98900725A priority patent/EP0890989A4/en
Priority to US09/155,134 priority patent/US6133637A/en
Publication of JPH10223680A publication Critical patent/JPH10223680A/en
Priority to US09/612,480 priority patent/US6458609B1/en
Application granted granted Critical
Publication of JP3543251B2 publication Critical patent/JP3543251B2/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member

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  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、回路素子の多数個を形成したＩＣチップを、別のＩＣチップ又は回路基板に対して、これらにおける各電極パッドの相互間を電気的に接続した状態で、ボンディング（接合）するための装置に関するものである。
【０００２】
【従来の技術】
従来、ＩＣチップを、別のＩＣチップ又は回路基板に対して、これらにおける各電極パッドの相互間を電気的に接続した状態で、ボンディングするに際しては、前記ＩＣチップに形成した各電極パッドと、前記別のＩＣチップ又は回路基板に形成した各電極パッドのうちいずれか一方にバンプを設けて、このバンプを、他方の電極パッドに対して圧着するか、両方の電極パッドの各々にバンプを設けて、このバンプ同士を圧着すると言う方法を採用している。
【０００３】
【発明が解決しようとする課題】
しかし、この方法において、ＩＣチップの別のＩＣチップ又は回路基板へのボンディングを、ＩＣチップと別のＩＣチップ又は回路基板とのうちいずれか一方の電極パッドに設けたバンプの他方の電極パッドへの圧着、又は、一方の電極パッドに設けたバンプと他方の電極パッドに設けたバンプとの圧着のみに依存することができず、前記した圧着後において、ＩＣチップと別のＩＣチップ又は回路基板との間に、その両者を一体的に接着するための合成樹脂を充填するようにしなければならないから、ＩＣチップを別のＩＣチップ又は回路基板にボンディングすることに要するコストが大幅にアップするばかりか、そのバンプの圧着に大きい押圧力を必要とするから、ＩＣチップに欠け又は割れが発生するおそれが大きいと言う問題があった。
【０００４】
本発明は、これらの問題を解消することを技術的課題とするものである。
【０００５】
【課題を解決するための手段】
この技術的課題を達成するため本発明は、
「ＩＣチップを、別のＩＣチップ又は回路基板の片面側に、当該ＩＣチップの片面に形成した電極パッドを前記別のＩＣチップ又は回路基板の片面に形成した電極パッドに対面して配設し、前記ＩＣチップの各電極パッド及び前記別のＩＣチップ又は回路基板の各電極パッドのうちいずれか一方の各電極パッドに、当該電極パッドより突出するバンプを設ける一方、前記他方の各電極パッドを、当該他方の各電極パッドが設けられるＩＣチップ又は別のＩＣチップ或いは回路基板の片面から突出するように構成して、この他方の各電極パッドのうち前記バンプに対応する部分に、前記バンプが嵌まる凹所を、当該凹所の深さを前記他方の電極パッドの突出高さよりも浅くして設け、更に、前記ＩＣチップを、前記別のＩＣチップ又は回路基板に対して、その間に介挿した導電粒子混入の接着フィルムにて、前記各バンプが当該接着フィルムを前記凹所内に向かって圧縮変形するようにして接着し、前記各バンプの先端を、前記他方の各電極パッドを形成したＩＣチップ又は別のＩＣチップ或いは回路基板の片面に対して略平行な平面にする一方、前記凹所の底面を、前記他方の各電極パッドを形成したＩＣチップ又は別のＩＣチップ或いは回路基板の片面に対して略平行な平面に構成して、これら両平面間にて前記接着フィルムを挟むように構成し、更に、前記凹所の底面における周囲に、当該底面から立ち上がる内周面を設ける。」
と言う構成にした。
【０００６】
【発明の作用・効果】
このように構成することにより、ＩＣチップを、別のＩＣチップ又は回路基板に対して接着フィルムにて強固にボンディングすることができる一方、前記接着フィルムを、バンプにて圧縮変形することにより、この接着フィルムに混入されている導電粒子が、バンプと電極パッドとの間に挟まれることになって、この導電粒子を介して前記バンプと電極パッドとが互いに電気的に導通することになる。
【０００７】
この場合において、前記バンプと電極パッドとの電気的な導通をより確実にするために、前記接着フィルムへの導電粒子の混入量を多くすると、前記ＩＣチップと、別のＩＣチップ又は回路基板とは、その各バンプ及び電極パッド以外の部分においても電気的に導通すると言うように、前記ＩＣチップと別のＩＣチップ又は回路基板との間における電気的絶縁性が低下することになる。また、この電気的絶縁性を向上するために、前記接着フィルムへの導電粒子の混入量を少なくすると、前記バンプによる接着フィルムの圧縮変形に際して、このバンプと電極パッドとの間に挟まれる導電粒子の頻度が小さくなるから、その間における電気的接続に不良が発生することになる。
【０００８】
これに対して、本発明は、電極パッドに凹所を設けることにしたのであり、このように構成したことにより、前記接着フィルムがバンプによって圧縮変形するときに、この接着フィルムに混入した導電粒子が前記バンプと電極パッドとの間から横方向に逃げるのを、電極パッドに設けた凹所にて阻止でき、換言すると、電極パッドにおける凹所内に、多くの導電粒子を確保することができる。
【０００９】
しかも、前記バンプが凹所に嵌まるように構成したことにより、前記凹所内に導電粒子を確保することを、当該導電粒子の粒径に関係なく確実に達成できるから、前記接着フィルムへの導電粒子の混入量を多くすることなく、電気的接続の確実性を向上できる。
【００１０】
従って、本発明によると、ＩＣチップを、別のＩＣチップ又は回路基板に対して、その相互間における電気絶縁性を確保し、且つ、その電極パッド同士を確実に電気的に接続した状態のもとで、強固にボンディングすることができるものでありながら、前記ＩＣチップを、別のＩＣチップ又は回路基板に対して、その間に接着フィルムを介挿したのち押圧するだけで良いから、ボンディングの工程が簡単になり、これに要するコストを大幅に低減できるのであり、しかも、前記の押圧は、従来におけるバンプ接合の場合よりも遙かに軽いから、ＩＣチップに欠け又は割れが発生することを大幅に低減できると言う効果を有する。
【００１１】
【発明の実施の形態】
以下、本発明の実施の形態を、図１〜図６の図面について説明する。
【００１２】
この図において、符号１は、矩形状のチップマウント部１ａと、このチップマウント部１ａにおける四つの各辺から外向きに延びる複数本のリード端子１ｂとを備えたリードフレームを示す。
【００１３】
また、符号２は、前記リードフレーム１におけるチップマウント部１ａに対してダイボンディングされる第１ＩＣチップを示し、この第１ＩＣチップ２の上面には、図示しない能動素子又は受動素子等のような回路素子の多数個が形成されている共に、その周囲にワイヤボンディングパッド２ａの多数個が形成されている。更に、前記第１ＩＣチップ２の上面のうち前記各ワイヤボンディングパッド２ａより内側には、後述する第２ＩＣチップ３に対する接続用の電極パッド２ｂの多数個が、第１ＩＣチップ２の上面から適宜寸法だけ突出するように形成されている。
【００１４】
更にまた、符号３は、前記第１ＩＣチップ２の上面にボンディングされる第２ＩＣチップを示し、この第２ＩＣチップ３における表裏両面のうち少なくとも片面には、前記第１ＩＣチップ２と同様に図示しない能動素子又は受動素子等のような回路素子の多数個が形成されていると共に、前記第１ＩＣチップ２における各電極パッド２ｂの各々に対応する箇所ごとに接続用の電極パッド３ａが形成されている。
【００１５】
そして、前記第２ＩＣチップ３を、前記第１ＩＣチップ２に対して、これらにおける電極パッド２ｂ，３ａの相互間を電気的に接続した状態でボンディングするに際しては、前記第２ＩＣチップ３における各電極パッド３ａの各々に、当該電極パッド３ａから突出するバンプ３ｂを設ける一方、前記第１ＩＣチップ２における各電極パッド２ｂの各々に、前記バンプ３ｂが嵌まる凹所２ｃを、当該凹所２ｃにおける深さ寸法を前記電極パッド２ｂの突出高さ寸法よりも浅くして設ける。
【００１６】
次いで、前記第２ＩＣチップ３を、その回路素子、電極パッド３ａ及びバンプ３ｂを形成した片面を下向きにして、前記第１ＩＣチップ２の上面側に配設し、その間に導電粒子を混入した接着フィルム４を介挿したのち、前記第２ＩＣチップ３を、第１ＩＣチップ２に向かって、その間における前記接着フィルム４を、各バンプ３ｂにより圧縮変形するように押圧し、この押圧を保持した状態で、加熱等にて前記接着フィルム４を乾燥・硬化することにより、前記第２ＩＣチップ３を、第１ＩＣチップ２に対して、その間に介挿した接着フィルム４により確実に且つ強固にボンディングできるのである。
【００１７】
また、前記第２ＩＣチップ３における各バンプ３ｂが、前記接着フィルム４を圧縮変形することにより、この接着フィルム４に混入されている導電粒子が、この各バンプ３ｂと、第１ＩＣチップ２における各電極パッド２ｂとの間に挟まれることにより、第２ＩＣチップ３における各電極パッド３ａと、第１ＩＣチップ２における各電極パッド２ｂの相互間を電気的に接続することができる。
【００１８】
しかし、この場合において、第１ＩＣチップ２における各電極パッド２ｂに、前記バンプ３ｂが嵌まる凹所２ｃが設けられていないときには、前記バンプ３ｂにて接着フィルム４が圧縮変形するとき、この接着フィルム４に混入されている導電粒子が、前記バンプ３ｂと電極パッド２ｂとの間の部分から横方向に逃げることになるから、前記接着フィルム４における導電粒子の混入量を多くしないと、確実な電気的接続を確保することができない。
【００１９】
これに対して、前記したように、第１ＩＣチップ２における各電極パッド２ｂに、前記バンプ３ｂが嵌まる凹所２ｃを設けた場合には、前記接着フィルム４がバンプ３ｂによって圧縮変形するときに、この接着フィルム４に混入した導電粒子が前記バンプ３ｂと電極パッド２ｂとの間から横方向に逃げるのを、電極パッド２ｂに設けた凹所２ｃにて阻止でき、換言すると、電極パッド２ｂにおける凹所２ｃ内に、多くの導電粒子を確保することができるから、前記接着フィルム４への導電粒子の混入量を多くすることなく、電気的接続の確実性を向上できるのである。
【００２０】
このようにして、第１ＩＣチップ２に対して第２ＩＣチップ３をボンディングすると、この第１ＩＣチップ２を、図６に示すように、前記リードフレーム１におけるチップマウント部１ａに対してダイボンディングし、次いで、この第１ＩＣチップ２における各ワイヤボンディングパッド２ａと、リードフレーム１における各リード端子１ｂとの間を、細い金属線５によるワイヤボンディングにて電気的に接続したのち、これらの全体を、合成樹脂製のパッケージ体６にて密封することにより、密封型の半導体装置とするのである。
【００２１】
なお、前記の説明は、バンプ３ｂを、第２ＩＣチップ３における各電極パッド３ａに、このバンプ３ｂが嵌まる凹所２ｃを、第１ＩＣチップ２における各電極パッド２ｂに各々設けた場合であったが、これに代えて、バンプ３ｂを、第１ＩＣチップ２における各電極パッド２ｂに、このバンプ３ｂが嵌まる凹所２ｃを、第２ＩＣチップ３における各電極パッド３ａに各々設けた構成にしても良く、また、本発明は、前記のように、ＩＣチップ３を、別のＩＣチップ２に対してボンディングする場合に限らず、ＩＣチップ３を、回路基板に対してボンディングする場合にも適用できることは言うまでもない。
【図面の簡単な説明】
【図１】本発明の実施の形態を示す分解斜視図である。
【図２】図１の縦断正面図である。
【図３】図２の要部拡大図である。
【図４】第２ＩＣチップを第１ＩＣチップに対してボンディングした状態を示す縦断正面図である。
【図５】図４の要部拡大図である。
【図６】密封型半導体装置の縦断正面図である。
【符号の説明】
１ リードフレーム
１ａ チップマウント部
１ｂ リード端子
２ 第１ＩＣチップ
２ｂ 第１ＩＣチップの電極パッド
２ｃ 凹所
３ 第２ＩＣチップ
３ａ 第２ＩＣチップの電極パッド
３ｂ バンプ
４ 接着フィルム
５ 金属線
６ パッケージ体[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention is for bonding (bonding) an IC chip on which a large number of circuit elements are formed to another IC chip or a circuit board in a state where the respective electrode pads of the IC chip are electrically connected to each other. Related to the device.
[0002]
[Prior art]
Conventionally, when bonding an IC chip to another IC chip or a circuit board in a state in which the respective electrode pads are electrically connected to each other, each electrode pad formed on the IC chip is A bump is provided on one of the electrode pads formed on the another IC chip or the circuit board, and the bump is pressed against the other electrode pad, or a bump is provided on each of the two electrode pads. Then, a method of pressing these bumps together is adopted.
[0003]
[Problems to be solved by the invention]
However, in this method, bonding of the IC chip to another IC chip or circuit board is performed by bonding the bump provided on one of the electrode pads of the IC chip and another IC chip or circuit board to the other electrode pad. Crimping, or the crimping of only the bump provided on one electrode pad and the bump provided on the other electrode pad, and after the above-mentioned crimping, the IC chip and another IC chip or circuit board In order to bond the IC chip to another IC chip or a circuit board, it is necessary to fill a synthetic resin for bonding the two together. Alternatively, since a large pressing force is required to press the bumps, there is a problem that there is a high possibility that the IC chip is chipped or cracked. .
[0004]
An object of the present invention is to solve these problems.
[0005]
[Means for Solving the Problems]
To achieve this technical problem, the present invention
"An IC chip is provided on one side of another IC chip or circuit board , with the electrode pad formed on one side of the IC chip facing the electrode pad formed on one side of the another IC chip or circuit board. , to either the electrode pads of the respective electrode pads of each electrode pad and the another IC chip or the circuit board of the IC chip, while providing a bump protruding from the electrode pads, the electrode pads of the other The other electrode pad is provided so as to protrude from one surface of an IC chip or another IC chip or a circuit board, and the other electrode pad is provided with a bump at a portion corresponding to the bump. the whole recess fitting, provided the depth of the recess is shallower than the projection height of the other electrode pad, further, the IC chip, the another IC chip or the circuit board In contrast, in the adhesive film of the conductive particles mixed with interposed therebetween, said bonded as each bump is compressed and deformed toward the adhesive film in said recess, the tip of each bump, of the other While making the IC chip on which each electrode pad is formed or another IC chip or a plane substantially parallel to one surface of the circuit board , the bottom surface of the recess, the IC chip on which the other electrode pad is formed or another It is configured on a plane substantially parallel to one surface of the IC chip or the circuit board, and the adhesive film is sandwiched between these two planes, and further, rises from the bottom surface around the bottom surface of the recess. Provide an inner peripheral surface. "
It was configured to say.
[0006]
[Action and Effect of the Invention]
With this configuration, the IC chip can be firmly bonded to another IC chip or a circuit board with an adhesive film, while the adhesive film is compressed and deformed with bumps, so that The conductive particles mixed in the adhesive film are sandwiched between the bump and the electrode pad, so that the bump and the electrode pad are electrically connected to each other via the conductive particle.
[0007]
In this case, in order to further ensure electrical continuity between the bump and the electrode pad, if the amount of conductive particles mixed into the adhesive film is increased, the IC chip and another IC chip or circuit board may In other words, the electrical insulation between the IC chip and another IC chip or a circuit board is reduced, so that electrical conduction is also provided in portions other than the respective bumps and electrode pads. Further, when the amount of conductive particles mixed into the adhesive film is reduced to improve the electrical insulation, the conductive particles sandwiched between the bump and the electrode pad during the compression deformation of the adhesive film by the bumps , The electrical connection between them becomes defective.
[0008]
On the other hand, according to the present invention, a concave portion is provided in the electrode pad. With this configuration, when the adhesive film is compressed and deformed by the bump, the conductive particles mixed in the adhesive film are formed. Can be prevented from laterally escaping from between the bump and the electrode pad by the recess provided in the electrode pad, in other words, a large number of conductive particles can be secured in the recess in the electrode pad.
[0009]
Moreover, since the bumps are configured to fit into the recesses, it is possible to reliably secure the conductive particles in the recesses regardless of the particle size of the conductive particles. The reliability of electrical connection can be improved without increasing the amount of mixed particles.
[0010]
Therefore, according to the present invention, it is possible to secure the electrical insulation between the IC chip and another IC chip or circuit board, and to ensure that the electrode pads are electrically connected to each other. Thus, although the IC chip can be firmly bonded, it is only necessary to insert the adhesive film between the IC chip and another IC chip or a circuit board and press the IC chip between them, so that the bonding process is performed. Can be simplified, and the cost required for this can be greatly reduced. In addition, since the above-mentioned pressing is much lighter than the conventional bump bonding, chipping or cracking of the IC chip is greatly reduced. This has the effect of being able to be reduced to
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
[0012]
In this drawing, reference numeral 1 denotes a lead frame including a rectangular chip mount 1a and a plurality of lead terminals 1b extending outward from four sides of the chip mount 1a.
[0013]
Reference numeral 2 denotes a first IC chip that is die-bonded to the chip mount portion 1a of the lead frame 1. On the upper surface of the first IC chip 2, a circuit such as an active element or a passive element (not shown) is provided. A large number of elements are formed, and a large number of wire bonding pads 2a are formed therearound. Further, on the inner surface of the upper surface of the first IC chip 2, a plurality of electrode pads 2 b for connection to the second IC chip 3, which will be described later, are provided only within appropriate dimensions from the upper surface of the first IC chip 2. It is formed so as to protrude.
[0014]
Further, reference numeral 3 denotes a second IC chip bonded to the upper surface of the first IC chip 2, and at least one of the front and back surfaces of the second IC chip 3 has an active (not shown) like the first IC chip 2. A large number of circuit elements such as elements or passive elements are formed, and connection electrode pads 3a are formed at locations corresponding to the respective electrode pads 2b on the first IC chip 2.
[0015]
When bonding the second IC chip 3 to the first IC chip 2 in a state where the electrode pads 2b and 3a are electrically connected to each other, each electrode pad in the second IC chip 3 is required. Each of the electrode pads 3a is provided with a bump 3b protruding from the corresponding electrode pad 3a, while each of the electrode pads 2b of the first IC chip 2 is provided with a recess 2c in which the bump 3b fits, and a depth of the recess 2c. The dimension is set to be smaller than the protruding height dimension of the electrode pad 2b .
[0016]
Then, the second IC chip 3 is disposed on the upper surface of the first IC chip 2 with one surface on which the circuit elements, the electrode pads 3a and the bumps 3b are formed facing downward, and an adhesive film containing conductive particles mixed therebetween. 4, the second IC chip 3 is pressed toward the first IC chip 2 so that the adhesive film 4 therebetween is compressed and deformed by the bumps 3 b. By drying and curing the adhesive film 4 by heating or the like, the second IC chip 3 can be securely and firmly bonded to the first IC chip 2 by the adhesive film 4 interposed therebetween.
[0017]
Each bump 3b of the second IC chip 3 compresses and deforms the adhesive film 4, so that conductive particles mixed in the adhesive film 4 cause the bumps 3b and each electrode of the first IC chip 2 to be deformed. By being sandwiched between the pads 2b, the electrode pads 3a of the second IC chip 3 and the electrode pads 2b of the first IC chip 2 can be electrically connected to each other.
[0018]
However, in this case, when each electrode pad 2b of the first IC chip 2 is not provided with a recess 2c in which the bump 3b is fitted, when the adhesive film 4 is compressed and deformed by the bump 3b, Since the conductive particles mixed in the adhesive film 4 escape laterally from the portion between the bump 3b and the electrode pad 2b, if the amount of the conductive particles mixed in the adhesive film 4 is not increased, a reliable electric power is generated. Connection cannot be secured.
[0019]
On the other hand, as described above, when the recesses 2c into which the bumps 3b fit are provided in the electrode pads 2b of the first IC chip 2, when the adhesive film 4 is compressed and deformed by the bumps 3b. The conductive particles mixed in the adhesive film 4 can be prevented from laterally escaping from between the bump 3b and the electrode pad 2b by the recess 2c provided in the electrode pad 2b. Since a large number of conductive particles can be secured in the recess 2c, the reliability of the electrical connection can be improved without increasing the amount of the conductive particles mixed into the adhesive film 4.
[0020]
When the second IC chip 3 is bonded to the first IC chip 2 in this manner, the first IC chip 2 is die-bonded to the chip mount portion 1a of the lead frame 1 as shown in FIG. Next, after electrically connecting each wire bonding pad 2a of the first IC chip 2 and each lead terminal 1b of the lead frame 1 by wire bonding with a thin metal wire 5, the whole of them is synthesized. By sealing with a resin package 6, a sealed semiconductor device is obtained.
[0021]
In the above description, the bump 3b is provided in each electrode pad 3a in the second IC chip 3, and the recess 2c in which the bump 3b is fitted is provided in each electrode pad 2b in the first IC chip 2. However, instead of this, the bump 3b may be provided in each electrode pad 2b of the first IC chip 2, and the recess 2c in which the bump 3b fits may be provided in each electrode pad 3a of the second IC chip 3. Also, the present invention can be applied not only to the case where the IC chip 3 is bonded to another IC chip 2 but also to the case where the IC chip 3 is bonded to a circuit board, as described above. Needless to say.
[Brief description of the drawings]
FIG. 1 is an exploded perspective view showing an embodiment of the present invention.
FIG. 2 is a vertical sectional front view of FIG.
FIG. 3 is an enlarged view of a main part of FIG. 2;
FIG. 4 is a longitudinal sectional front view showing a state where a second IC chip is bonded to a first IC chip.
FIG. 5 is an enlarged view of a main part of FIG. 4;
FIG. 6 is a vertical sectional front view of the sealed semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Lead frame 1a Chip mount part 1b Lead terminal 2 First IC chip 2b Electrode pad 2c of first IC chip Depression 3 Second IC chip 3a Electrode pad 3b of second IC chip Bump 4 Adhesive film 5 Metal wire 6 Package body

Claims (1)

ＩＣチップを、別のＩＣチップ又は回路基板の片面側に、当該ＩＣチップの片面に形成した電極パッドを前記別のＩＣチップ又は回路基板の片面に形成した電極パッドに対面して配設し、
前記ＩＣチップの各電極パッド及び前記別のＩＣチップ又は回路基板の各電極パッドのうちいずれか一方の各電極パッドに、当該電極パッドより突出するバンプを設ける一方、
前記他方の各電極パッドを、当該他方の各電極パッドが設けられるＩＣチップ又は別のＩＣチップ或いは回路基板の片面から突出するように構成して、この他方の各電極パッドのうち前記バンプに対応する部分に、前記バンプが嵌まる凹所を、当該凹所の深さを前記他方の電極パッドの突出高さよりも浅くして設け、
更に、前記ＩＣチップを、前記別のＩＣチップ又は回路基板に対して、その間に介挿した導電粒子混入の接着フィルムにて、前記各バンプが当該接着フィルムを前記凹所内に向かって圧縮変形するようにして接着し、
前記各バンプの先端を、前記他方の各電極パッドを形成したＩＣチップ又は別のＩＣチップ或いは回路基板の片面に対して略平行な平面にする一方、
前記凹所の底面を、前記他方の各電極パッドを形成したＩＣチップ又は別のＩＣチップ或いは回路基板の片面に対して略平行な平面に構成して、
これら両平面間にて前記接着フィルムを挟むように構成し、
更に、前記凹所の底面における周囲に、当該底面から立ち上がる内周面を設けたことを特徴とするＩＣチップのボンディング装置。Disposing an IC chip on one side of another IC chip or a circuit board , with the electrode pad formed on one side of the IC chip facing the electrode pad formed on one side of the another IC chip or circuit board;
To either the electrode pads of the respective electrode pads of each electrode pad and the another IC chip or the circuit board of the IC chip, while providing a bump protruding from the electrode pads,
The other electrode pads are configured to protrude from one surface of an IC chip or another IC chip or a circuit board on which the other electrode pads are provided, and correspond to the bumps of the other electrode pads. A portion where the bump fits, the depth of the recess is set to be smaller than the protruding height of the other electrode pad ,
Furthermore, the bumps compress and deform the adhesive film into the recess with an adhesive film containing conductive particles interposed between the IC chip and the another IC chip or circuit board. And glue
While the tip of each of the bumps is a plane substantially parallel to one surface of the IC chip on which the other electrode pads are formed or another IC chip or a circuit board ,
The bottom surface of the recess is formed as a plane substantially parallel to one surface of the IC chip or another IC chip on which the other electrode pads are formed or one surface of a circuit board ,
It is configured to sandwich the adhesive film between these two planes,
Furthermore, an IC chip bonding apparatus, wherein an inner peripheral surface rising from the bottom surface is provided around the bottom surface of the recess.
JP02021797A 1997-01-24 1997-02-03 IC chip bonding equipment Expired - Fee Related JP3543251B2 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP02021797A JP3543251B2 (en) 1997-02-03 1997-02-03 IC chip bonding equipment
PCT/JP1998/000281 WO1998033217A1 (en) 1997-01-24 1998-01-22 Semiconductor device and method for manufacturing thereof
KR10-2004-7000090A KR100467946B1 (en) 1997-01-24 1998-01-22 Method for manufacturing a semiconductor chip
EP98900725A EP0890989A4 (en) 1997-01-24 1998-01-22 SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE DEVICE
KR10-1998-0707403A KR100522223B1 (en) 1997-01-24 1998-01-22 Semiconductor device and method for manufacturing thereof
US09/155,134 US6133637A (en) 1997-01-24 1998-01-22 Semiconductor device having a plurality of semiconductor chips
US09/612,480 US6458609B1 (en) 1997-01-24 2000-07-07 Semiconductor device and method for manufacturing thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP02021797A JP3543251B2 (en) 1997-02-03 1997-02-03 IC chip bonding equipment

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JP3543251B2 true JP3543251B2 (en) 2004-07-14

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