JP3498018B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having an improved etching prevention layer and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent MOS transistors, the PN junctions of the source / drain regions are extremely shallow. Therefore, when the contact is opened above the source / drain regions, the silicon substrate may be dug by overetching, which may destroy the PN junction immediately below the contact.

Considering various factors such as the thickness of the interlayer insulating film on which the contact is to be formed and variations in the etching rate, overetching to some extent is essential. Therefore, it is necessary not to dig the silicon substrate at the time of contact opening by dry etching.

For this purpose, a method of forming an etching preventive layer between a silicon substrate and an interlayer insulating film (BPSG film or other silicon oxide film) is disclosed in JP-A-60-2611.
32 and JP-A-61-247073.

For example, in JP-A-60-261132, a thermal oxide film is used as an etching prevention layer.

Further, in JP-A-61-247073, a silicon nitride film having a thickness of several hundred angstroms is used as an etching prevention layer.

The process proposed in JP-A-61-247073 will be described below with reference to FIGS. 9 and 10.

First, as shown in FIG. 9A, a silicon nitride film 20 having a thickness of 500 Å is formed on a silicon substrate 1 on which a transistor is formed, and further, a silicon oxide film 21 of 9000 Å is formed on the silicon nitride film 20. To form a film. Figure 9
In (a), the transistor is not shown, and only the buried silicon oxide film 2 formed on the surface of the silicon substrate 1 for element isolation is shown.

The surface of the silicon oxide film 21 is assumed to be planarized by chemical mechanical polishing (CMP) or other method.

Subsequently, a resist 7 is formed, and the resist 7 is patterned by a photolithography technique to form a contact opening 8.

Next, as shown in FIG. 9B, the silicon oxide film 21 is etched under the etching condition that the etching rate of the silicon nitride film 20 is slow. The etching is stopped when the silicon nitride film 20 recedes by 100 to 200Å.

Next, as shown in FIG. 10A, the silicon nitride film 20 is etched under the etching condition that the etching rate of silicon is slow. Since it suffices to etch the thin silicon nitride film 20, the amount of overetching can be set to be small, and the silicon substrate 1 is not excessively dug.

After that, the resist 7 is peeled and removed, and the opening is filled with metal to form a contact.

[0014]

However, this process has a problem that it is difficult to form a local wiring in the same layer (same mask) as the contact.

Here, the local wiring is to connect adjacent diffusion layers or the diffusion layer and the gate electrode via a contact layer (slit contact). Figure 4
An example is shown in. In the structure shown in FIG. 4, the contact layer 12 is formed on one diffusion layer 11, and the other two adjacent diffusion layers 11 are connected via the slit-shaped local wiring 13.

The etching rate of contact etching is generally faster when the area of the opening is larger. Therefore, the slit-shaped local wiring 13 is opened earlier than the contact 12.

Further, as can be seen from FIG. 4, the local wiring 1
3 has a silicon portion (inside the rectangle showing the diffusion layer 11) and a silicon oxide portion (outside the rectangle showing the diffusion layer 11). In the above-mentioned process, if the etching rate of silicon is reduced when etching the silicon nitride film, the etching rate of the silicon oxide film increases, so that the silicon oxide portion at the bottom of the local wiring 13 is dug. .

If the buried silicon oxide film is dug in this way, a leak current will flow through the side wall of the element isolation portion, which will adversely affect the transistor operation.

For example, as shown in FIG. 14, when the buried silicon oxide film 2 is dug, the tungsten or other metal 10 buried in the contact opening and the silicon substrate 1 come into contact with each other on the side wall of the buried silicon oxide film 2. Therefore, the leak current A flows from the metal 10 to the silicon substrate 1 via the contact portion.

The process of generating the leak current A will be described below with reference to FIGS. 11 and 12 which are sectional views taken along the line AA 'in FIG.

First, as shown in FIG. 11A, a silicon nitride film 20 having a thickness of 500Å is formed on a silicon substrate 1 on which a transistor is formed, and further, a silicon nitride film 2 is formed.
A 9000Å silicon oxide film 21 is formed on the substrate 0. In FIG. 11A, the transistor is not shown, and only the buried silicon oxide film 2 formed on the surface of the silicon substrate 1 for element isolation is shown.

The surface of the silicon oxide film 21 is assumed to be planarized by chemical mechanical polishing (CMP) or another method.

Subsequently, a resist 7 is formed, and the resist 7 is patterned by a photolithography technique to form a contact opening 8 and a local wiring opening 9.

Next, as shown in FIG. 11B, the silicon oxide film 21 is etched under the etching condition that the etching rate of the silicon nitride film is slow. The amount of recession of the silicon nitride film 20 due to this etching is 100 to 200Å in the contact opening 8 and 3 in the local wiring opening 9.
00 to 400Å, and the silicon nitride film 20 becomes thinner in the local wiring opening 9.

Next, as shown in FIG. 12, the silicon nitride film 20 is etched under the etching condition that the etching rate of silicon is slow.

Even if the contact portion can be formed well by this etching, the silicon substrate 1 is excessively etched in the local wiring portion. As a result, the silicon substrate 1 recedes about 100 Å, and the buried silicon oxide film 2 recedes about 500 Å.

After that, the resist 7 is peeled and removed, and the opening is filled with tungsten or another metal to form a contact and a local wiring.

As described above, as a method for solving the problem that the silicon substrate 1 is dug by etching,
For example, as shown in FIG. 13, there is a method of forming a 100 to 200 Å silicon oxide film 4 under the silicon nitride film 20.

In this method, the contact opening is etched in the following three steps. (1) First-stage etching for removing the silicon nitride film 20 to an intermediate depth (2) Second-stage etching for removing the entire silicon nitride film 20 (3) Third-stage etching for removing the thin silicon oxide film 4 Etching of the contact opening portion in this manner makes it possible to suppress excessive etching of the local wiring portion, and thus to suppress digging of the silicon substrate 1 as compared with the above-described conventional technique.

However, since the silicon oxide film 4 formed directly on the silicon substrate 1 is a silicon oxide film made of the same material as the element isolation burying film 2, the silicon oxide portion as the element isolation burying film 2 in the local wiring portion is After all it will be dug.

In order to avoid this, a film made of a material that is dense and has a different etching rate from the buried silicon oxide film 2 is formed on the silicon substrate 1, such as an extremely thin thermal oxide film. However, it is impossible to form such a film on the silicon substrate 1 after forming the transistor.

Therefore, even if the etching preventing layer having the two-layer structure of the silicon nitride film 20 and the silicon oxide film 4 as shown in FIG. 13 is used, the contact and the local wiring cannot be formed well at the same time.

Further, Japanese Patent Publication No. 6-58902 and Japanese Patent Application Laid-Open No. 9-129730 also propose an etching prevention layer having a two-layer structure. However, similar to the structure shown in FIG. It has a problem that it cannot be formed well at the same time.

There is another problem in the above-mentioned conventional technique.

In order for the silicon nitride film to function as an etching prevention layer, a thickness of about 500 Å or more is required. However, since a thick silicon nitride film does not allow hydrogen to easily pass through, if the thickness of the silicon nitride film as the etching prevention layer is set to 500 Å or more, hydrogen will not be transferred to the transistor during the hydrogen heat treatment at about 400 ° C. performed at the end of the manufacturing process. There is a possibility that it will not be delivered.

This hydrogen heat treatment is a step necessary for improving transistor characteristics with hydrogen. By raising the temperature of the hydrogen heat treatment or by considerably lengthening the heat treatment time, the problem that hydrogen does not reach the transistor can be avoided, but conversely, the throughput decreases.

In order to make sure that hydrogen reaches the transistor in the hydrogen heat treatment without lowering the throughput, for example, Japanese Patent Laid-Open No. 61-154174 discloses
A process for opening a hydrogen permeation window in the silicon nitride film is proposed.

However, as described with reference to FIGS. 11 and 12, when the silicon nitride film 20 is present immediately above the silicon substrate 1, the silicon substrate 1 is dug when the window is etched. It will be. Therefore,
The same problem as described above occurs.

Further, as shown in FIG. 13, if the silicon oxide film 4 is formed between the silicon substrate 1 and the silicon nitride film 20, there is an effect to the above-mentioned problem that hydrogen does not reach the transistor, As described above, the contact and the local wiring cannot be formed well at the same time.

The present invention has been made in view of the above problems in the conventional semiconductor device and the manufacturing method thereof, and even if the contact and the local wiring having different opening areas are present in the same layer, the substrate It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that enable etching without excessively digging.

It is another object of the present invention to provide a semiconductor device and its manufacturing method which can maintain the effect of hydrogen heat treatment even when a silicon nitride film is used as a contact / local wiring etching prevention layer. And

[0042]

In order to achieve this object, a first aspect of the present invention provides a semiconductor device comprising a semiconductor substrate and an etching prevention layer formed on the semiconductor substrate. The etching prevention layer includes a first silicon nitride layer formed on the semiconductor substrate, a silicon oxide layer formed on the first silicon nitride layer, and a second silicon nitride layer formed on the silicon oxide layer. And a silicon nitride layer , wherein the first silicon nitride layer is
Smaller than the silicon oxide layer and the second silicon nitride layer
The first silicon nitride layer, the oxide layer
The silicon layer and the second silicon nitride layer are thicker in this order.
There is provided a semiconductor device having a large value .

[0043]

[0044]

For example, as described in claim 2 , the first silicon nitride layer has a thickness of about 50 Å,
The silicon oxide layer can be set to a thickness of about 200 Å and the second silicon nitride layer can be set to a thickness of about 500 Å.

According to a third aspect of the present invention, a first silicon nitride film, a first silicon oxide film, a second silicon nitride film and a second oxide film are formed on a semiconductor substrate having a semiconductor element formed thereon. A first step of forming a silicon film in this order, a second step of forming a photoresist having a contact formation opening and a local wiring formation opening on a second silicon oxide film, and using the photoresist as a mask , A third step of etching the second silicon oxide film over the entire depth, and the second silicon nitride film over the partial depth, and the second silicon nitride film over the entire depth, And, a fourth step of etching the first silicon oxide film over a partial depth, and a fifth step of etching the first silicon oxide film until the first silicon nitride film is exposed, A sixth step of etching the first silicon nitride film over the entire depth, and a seventh step of filling the contact formation opening and the local wiring formation opening formed by the third to sixth steps with metal. A method for manufacturing a semiconductor device is provided.

The etching in the third step is preferably performed under the condition that the etching rate of the silicon nitride film is slower than the etching rate of the silicon oxide film, as described in claim 4. .

The etching in the fourth step is preferably performed under the condition that the etching rate of the silicon oxide film is slower than the etching rate of the silicon nitride film, as described in claim 5. .

As described in claim 6 , the etching in the fifth step is preferably performed under the condition that the etching rate of the silicon nitride film is slower than the etching rate of the silicon oxide film. .

The semiconductor substrate is made of silicon, and the etching in the sixth step is performed under the condition that the etching rate of silicon is slower than the etching rate of the silicon nitride film, as described in claim 7. It is preferable that the

According to a eighth aspect of the present invention, a first silicon nitride film, a first silicon oxide film and a second silicon nitride film are formed in this order on a semiconductor substrate on which a semiconductor element is formed. One process, the semiconductor device is formed
A second step of forming a first photoresist having a hydrogen permeation opening on the region on the second silicon nitride film, and using the first photoresist as a mask, the second silicon nitride film is formed into a first film. A third step of etching until the silicon oxide film is exposed, a fourth step of forming a second silicon oxide film after removing the first photoresist, and a second step of forming a contact formation opening. The fifth step of forming a photoresist on the second silicon oxide film, and using the second photoresist as a mask, the second silicon oxide film over the entire depth and the second silicon nitride film is formed. Sixth step of etching to some depth,
The second silicon nitride film over all depths, and
A seventh step of etching the first silicon oxide film to a partial depth, an eighth step of etching the first silicon oxide film until the first silicon nitride film is exposed, and a first nitriding step. Provided is a method for manufacturing a semiconductor device, comprising: a ninth step of etching a silicon film to all depths; and a tenth step of filling a contact formation opening formed by the third to sixth steps with a metal. To do.

In the present method, as described in claim 9 , in the fifth step, the second photoresist is preferably formed so as to also have a local wiring opening.

In the present method, as described in claim 10 , the etching in the third step is performed under the condition that the etching rate of the silicon oxide film is slower than the etching rate of the silicon nitride film. Is preferred.

In the present method, as described in claim 11 , the etching in the sixth step is performed under the condition that the etching rate of the silicon nitride film is slower than the etching rate of the silicon oxide film. Is preferred.

In the present method, as described in claim 12 , the etching in the seventh step is performed under the condition that the etching rate of the silicon oxide film is slower than the etching rate of the silicon nitride film. Is preferred.

In the present method, as described in claim 13 , the etching in the eighth step is performed under the condition that the etching rate of the silicon nitride film is slower than the etching rate of the silicon oxide film. Is preferred.

In the method, as described in claim 14 , the semiconductor substrate is made of silicon,
The etching in the ninth step is preferably performed under the condition that the etching rate of silicon is slower than the etching rate of the silicon nitride film.

In the present method, as described in claim 15 , in the second step, it is preferable that the hydrogen permeation opening is formed only directly above the gate electrode of the semiconductor element .

In this method, as described in claim 16 , the first silicon nitride layer is formed to have a smaller film thickness than the silicon oxide layer and the second silicon nitride layer. Is preferred.

In the present method, as described in claim 17 , the first silicon nitride layer, the silicon oxide layer and the second silicon nitride layer are formed in this order of increasing thickness. It is preferable.

In the method, as described in claim 18 , for example, the first silicon nitride layer comprises about 5
The thickness of 0 Å, the silicon oxide layer can be about 200 Å, and the second silicon nitride layer can be about 500 Å.

According to the present invention, even if the contact and the local wiring having different opening areas are present in the same layer, it is possible to etch the contact and the local wiring opening without excessively digging the substrate.

As described above, the etching prevention layer formed directly on the silicon substrate needs to have a different etching rate from both the silicon substrate and the embedded silicon oxide film. Therefore, the silicon nitride film is prevented from etching. It is the optimum material for the layer. Low pressure C of silicon nitride film
If the film is formed by VD (LPCVD), it can be made as thin as about 50Å.

However, unlike the prior art, the contact and the local wiring cannot be simultaneously formed in the etching preventing layer of the silicon nitride film single layer. Further, when the etching prevention layer is formed as a two-layer structure, it is impossible to use a silicon nitride film as a lower layer (substrate side).

On the other hand, in the semiconductor device and the method of manufacturing the same according to the present invention, the contact etching prevention layer includes a silicon nitride film (for example, about 50Å), a silicon oxide film (about 200Å), and a silicon nitride film (about 500Å)
It has a three-layer structure. With such a structure, it is possible to obtain an effect that the contact and the local wiring can be favorably opened.

Further, when a window for hydrogen permeation is opened in the silicon nitride film in order to enhance the effect of hydrogen heat treatment, the semiconductor layer and the manufacturing method thereof according to the present invention do not damage the silicon substrate. You can also get the effect.

[0067]

FIG. 4 is a plan view of a semiconductor device according to the first embodiment of the present invention.

The contact 12 is formed on the first diffusion layer 11a.
Is formed, and local wirings (that is, slit-shaped contacts) 13 are formed over the second and third diffusion layers 11b and 11c adjacent to each other. For simplification of description, the transistor is not shown in FIG. 4, and only the diffusion layer 11, the contact 12 and the local wiring 13 are shown.

Diffusion layer frames 11a, 11b of the silicon substrate,
The outside of 11c becomes an element isolation layer filled with a silicon oxide film. The bottom of the contact 12 is silicon,
At the bottom of the local wiring 13, a silicon portion (diffusion layer 11a,
11b and 11c) and a silicon oxide portion (outside of the rectangles showing the diffusion layers 11a, 11b and 11c).

1 to 3 are sectional views taken along the line AA 'in FIG. Hereinafter, the method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 1A, a first silicon nitride film 3 having a thickness of 50Å, a first silicon oxide film 4 having a thickness of 200Å and a thickness of 500Å are formed on a silicon substrate 1 on which a transistor is formed. A second silicon nitride film 5 is formed, and then a second silicon oxide film 6 of 9000Å is formed.
A buried silicon oxide film 2 for element isolation is formed on the surface of a silicon substrate 1. The surface of the second silicon oxide film 6 is flattened by CMP or another method.

Subsequently, a resist 7 is formed on the second silicon oxide film 6, and the resist 7 is patterned by a photolithography technique to form a contact opening 8 and a local wiring opening 9.

Next, as shown in FIG. 1B, the second etching is performed under the etching condition that the etching rate of the silicon nitride film is slow.
The silicon oxide film 6 is etched. Etching is second
It is stopped in the middle of the silicon nitride film 5. By this etching, the amount of recession of the second silicon nitride film 5 becomes 100 to 200Å in the contact opening portion 8 and 300 to 400Å in the local wiring opening portion 9, and the second silicon nitride film 5 becomes thinner in the local wiring portion.

Next, as shown in FIG. 2A, the second etching is performed under the etching condition in which the etching rate of the silicon oxide film is slow.
The silicon nitride film 5 is etched and etching is stopped in the middle of the first silicon oxide film 4. Since the film to be etched is thin in the first place, the over-etch amount is small, and the receding amount of the first silicon oxide film 4 in the local wiring portion is several tens.
Can be suppressed to Å.

Next, as shown in FIG. 2B, the first etching is performed under the etching condition in which the etching rate of the silicon nitride film is slow.
The silicon oxide film 4 is etched, and the etching is stopped at the surface of the first silicon nitride film 3. Also in this etching, since the etching time is short, the over-etching amount can be reduced, the difference in the etching amount between the contact and the local wiring can be suppressed, and the bottom of each of the contact opening 8 and the local wiring opening 9 can be suppressed. The thickness of the remaining film of the first silicon nitride film 3 is about the same.

Next, as shown in FIG. 3A, the first silicon nitride film 3 is etched under the etching condition that the etching rate of silicon is slow. By this etching, the buried silicon oxide film 2 at the bottom of the local wiring opening 9 is also etched at the same time.
Since the silicon nitride film 3 is only etched, the amount of the buried silicon oxide film 2 dug down can be suppressed to a small amount. Number 10 on the silicon substrate 1 as in the prior art
The situation is different from the case where the 0Å silicon nitride film 20 (see FIG. 9) is etched.

Next, as shown in FIG. 3B, after removing the resist 7, the contact opening and the local wiring opening are filled with tungsten 10.

After that, a metal wiring is formed, or a via hole (connection hole) is further formed immediately above.

In the method of manufacturing a semiconductor device according to this embodiment, the etching prevention layer has a three-layer structure of silicon nitride film 3 / silicon oxide film 4 / silicon nitride film 5, and the film thickness thereof is close to that of the silicon substrate 1. It is set thicker in order from one. The first silicon nitride film 3 formed directly on the silicon substrate 1 is the thinnest of the three layers (about 50Å in the first embodiment). Therefore, the difference in etching amount between the contact portion and the local wiring portion can be buffered, and the contact opening portion 8 and the local wiring opening portion 9 can be buffered.
It is possible to obtain the advantage of being able to simultaneously form the same.

In the above embodiment, the film thicknesses of the first silicon nitride film 3, the first silicon oxide film 4 and the second silicon nitride film 5 which form the etching prevention layer are not limited to those specified. It is also possible to set another film thickness. However, the film pressure of each film is set so that the first silicon nitride film 3 closest to the silicon substrate 1 becomes thinnest.

Further, the active region may be silicidized.

As the second silicon oxide film 6, BP is used.
An SG film may be used, or a laminated structure of a non-doped film and a BPSG film may be used.

The etching may be performed by using a plurality of etchers, or the steps may be changed by one etcher.

In the above-described first embodiment, the method for manufacturing a semiconductor device according to the present invention is applied to the simultaneous formation of contacts and local wirings. However, as described below, the method for manufacturing a semiconductor device according to the present invention. Can also be applied to open windows for hydrogen permeation.

FIG. 8 is a plan view of a semiconductor device according to the second embodiment of the present invention.

A gate electrode 18 is formed on the first diffusion layer 11a.
Is formed, and a hydrogen permeation window 19 is arranged on the gate electrode 18 for facilitating the hydrogen to reach the transistor during the hydrogen heat treatment. Second diffusion layer 11
A contact hole 12 is formed on b.

5 to 7 are sectional views taken along the line BB 'of FIG. Hereinafter, the method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 5A, a first silicon nitride film 3 having a thickness of 50 Å, a first silicon oxide film 4 having a thickness of 200 Å and a thickness of 500 Å are formed on a silicon substrate 1 on which a transistor is formed. The second silicon nitride film 5 is formed.
A buried silicon oxide film 2 for element isolation is formed on the surface of the silicon substrate 1, and a gate electrode 14 is formed on the silicon substrate 1.

Subsequently, a resist 7 is formed on the second silicon nitride film 5, the resist 7 is patterned by the photolithography technique, and the hydrogen permeation window 15 is opened.

Next, as shown in FIG. 5B, the second etching is performed under the etching condition in which the etching rate of the silicon oxide film is slow.
The silicon nitride film 5 is etched. Etching is the first
Stop at the surface of the silicon oxide film 4.

Next, as shown in FIG. 6A, after removing the resist 7, the second silicon oxide film 6 having a thickness of 9000Å is formed. The surface of the second silicon oxide film 6 is CM
P is assumed to have been flattened by another method.

Next, as shown in FIG. 6B, a second resist 16 is formed on the second silicon oxide film 6, the second resist 16 is patterned by photolithography, and the contact opening 17 is formed. Open.

When patterning the second resist 16, the local wiring opening may be formed at the same time as in the first embodiment.

Next, as shown in FIG. 7A, the contact is opened by the same method as that used in the first embodiment.

Next, as shown in FIG. 7B, after removing the second resist 16 by peeling, the contact is filled with tungsten 10.

After that, a metal wiring is formed, or a via hole (connection hole) is further formed immediately above.

In the method of manufacturing the semiconductor device according to the present embodiment, the hydrogen permeation window is opened only in the second silicon nitride film 5. Therefore, the silicon substrate 1 is not dug by etching when forming the hydrogen permeation window. Although the first silicon nitride film 3 still exists on the silicon substrate 1, since the first silicon nitride film 3 is as thin as 50 Å, there is no problem in hydrogen permeability.

Therefore, according to the present embodiment, it is possible to obtain the effect that the hydrogen permeation window can be favorably opened in the etching prevention layer made of silicon nitride.

Since the thin first silicon nitride film 3 can be left on the transistor, diffusion of moisture or the like from the interlayer insulating film can be suppressed. Therefore,
There is also the additional benefit of improved hot carrier resistance.

In this embodiment, the hydrogen permeation window is formed over the gate electrode 14 and its periphery, but the hydrogen permeation window may be opened just above the gate electrode 14, and the layout is the same as that of this embodiment. It is not limited to the example.

[0101]

According to the present invention, the etching prevention layer is made of silicon nitride film / silicon oxide film / silicon nitride film.
It has a layered structure, and the silicon nitride film formed directly on the silicon substrate is preferably formed to be the thinnest of the three layers. With such a three-layer etching structure, the difference in etching amount between the contact portion and the local wiring portion can be buffered, and the contact opening portion and the local wiring opening portion can be formed well at the same time.

Further, in the present invention, the hydrogen permeation window is opened only in the second silicon nitride film. Therefore, the silicon substrate is not dug by etching when forming the hydrogen permeation window. Although the first silicon nitride film still exists on the silicon substrate, since the first silicon nitride film is formed as a thin film, there is no problem in hydrogen permeability. Therefore, the effect that the hydrogen permeation window can be favorably opened in the etching prevention layer made of silicon nitride can be obtained.

Further, since the thin first silicon nitride film remains on the transistor, diffusion of moisture and the like from the interlayer insulating film can be suppressed and hot carrier resistance can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device showing a manufacturing process in a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of the semiconductor device showing a manufacturing process in the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of the semiconductor device showing a manufacturing process in the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a plan view of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a sectional view of a semiconductor device showing a manufacturing process in a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a sectional view of a semiconductor device showing a manufacturing process in a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a sectional view of a semiconductor device showing a manufacturing process in a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 8 is a plan view of a semiconductor device according to a second embodiment of the present invention.

FIG. 9 is a cross-sectional view of a semiconductor device showing a manufacturing process in a method for manufacturing a semiconductor device according to a first conventional example.

FIG. 10 is a cross-sectional view of a semiconductor device showing a manufacturing process in a method of manufacturing a semiconductor device according to a first conventional example.

FIG. 11 is a cross-sectional view of a semiconductor device showing a manufacturing process in a method of manufacturing a semiconductor device according to a second conventional example.

FIG. 12 is a cross-sectional view of a semiconductor device showing a manufacturing process in a method of manufacturing a semiconductor device according to a second conventional example.

FIG. 13 is a sectional view of a semiconductor device according to a third conventional example.

FIG. 14 is a cross-sectional view of a semiconductor device showing a leak current path in the semiconductor device according to a third conventional example.

[Explanation of symbols]

1 Silicon substrate 2 Embedded silicon oxide film 3 First silicon nitride film 4 First silicon oxide film 5 Second silicon nitride film 6 Second silicon oxide film 7 Resist 8 Contact openings 9 Local wiring opening 10 Tungsten 11a, 11b, 11c Diffusion layer 12 contacts 13 Local wiring 14 Gate electrode 15 Hydrogen permeation window 17 Contact opening 18 Gate electrode 19 Hydrogen permeation window

Claims (18)

(57) [Claims] 1. A semiconductor device comprising: a semiconductor substrate; and an etching prevention layer formed on the semiconductor substrate, wherein the etching prevention layer is a first silicon nitride layer formed on the semiconductor substrate, A silicon oxide layer formed on the first silicon nitride layer, and a second silicon nitride layer formed on the silicon oxide layer , wherein the first silicon nitride layer is the silicon oxide layer and Previous
Note that the second silicon nitride layer has a smaller film thickness, and the first silicon nitride layer, the silicon oxide layer and the front layer.
The thickness of the second silicon nitride layer is increased in this order.
Wherein a is what is. 2. The first silicon nitride layer has a thickness of about 50 Å, the silicon oxide layer has a thickness of about 200 Å, and the second silicon nitride layer has a thickness of about 500 Å. The semiconductor device according to claim 1, wherein: 3. A semiconductor substrate on which a semiconductor element is formed,
The first process of forming the first silicon nitride film, the first silicon oxide film, the second silicon nitride film, and the second silicon oxide film in this order, the contact formation opening, and the local wiring formation opening are formed. A second step of forming a photoresist having on the second silicon oxide film, and using the photoresist as a mask, the second silicon oxide film over the entire depth, and the second silicon nitride. A third step of etching the film to a partial depth; and a fourth step of etching the second silicon nitride film to a full depth and the first silicon oxide film to a partial depth. And a fifth step of etching the first silicon oxide film until the first silicon nitride film is exposed, and the first silicon nitride film over the entire depth. The method of manufacturing a semiconductor device comprising: a sixth step, a seventh step of the third to sixth contact forming openings and local interconnect formation opening formed by a process filled with a metal, an etched. 4. The etching in the third step comprises:
4. The method of manufacturing a semiconductor device according to claim 3, wherein the etching rate of the silicon nitride film is set to be slower than the etching rate of the silicon oxide film. 5. The etching in the fourth step comprises:
5. The method for manufacturing a semiconductor device according to claim 3, wherein the etching rate of the silicon oxide film is lower than that of the silicon nitride film. 6. The etching in the fifth step comprises:
6. The method of manufacturing a semiconductor device according to claim 3, wherein the etching rate of the silicon nitride film is lower than that of the silicon oxide film. 7. The semiconductor substrate is made of silicon, and the etching in the sixth step is performed under the condition that the etching rate of silicon is slower than the etching rate of the silicon nitride film. A method for manufacturing a semiconductor device according to claim 3. 8. A semiconductor substrate on which a semiconductor element is formed,
A first step of forming a first silicon nitride film, a first silicon oxide film, and a second silicon nitride film in this order, and a first step of forming a hydrogen permeation opening on a region where the semiconductor element is formed . Second step of forming a photoresist on the second silicon nitride film, and using the first photoresist as a mask until the second silicon nitride film is exposed to the first silicon oxide film A third step of etching, a fourth step of forming a second silicon oxide film after removing the first photoresist, and a second photoresist having an opening for contact formation with the second photoresist A fifth step of forming the second silicon nitride film on the silicon oxide film, and using the second photoresist as a mask, the second silicon oxide film over the entire depth and the second silicon nitride film A sixth step of etching the entire depth of the second silicon nitride film, and a seventh step of etching the first silicon oxide film over a partial depth, An eighth step of etching the first silicon oxide film until the first silicon nitride film is exposed, a ninth step of etching the first silicon nitride film over all depths, and A tenth step of filling a contact forming opening formed by the third to sixth steps with a metal, and a method of manufacturing a semiconductor device. 9. The method of manufacturing a semiconductor device according to claim 8, wherein in the fifth step, the second photoresist is formed so as to also have an opening for local wiring. 10. The etching in the third step is performed under the condition that the etching rate of the silicon oxide film is slower than the etching rate of the silicon nitride film. A method for manufacturing a semiconductor device as described above. 11. The etching in the sixth step is performed under the condition that the etching rate of the silicon nitride film is slower than the etching rate of the silicon oxide film. The method for manufacturing a semiconductor device according to any one of claims. 12. The etching in the seventh step is performed under the condition that the etching rate of the silicon oxide film is slower than the etching rate of the silicon nitride film. The method for manufacturing a semiconductor device according to any one of claims. 13. The etching in the eighth step is performed under the condition that the etching rate of the silicon nitride film is slower than the etching rate of the silicon oxide film. The method for manufacturing a semiconductor device according to any one of claims. 14. The semiconductor substrate is made of silicon,
9. The etching in the ninth step is performed under the condition that the etching rate of silicon is slower than the etching rate of the silicon nitride film.
14. The method for manufacturing a semiconductor device according to any one of items 13 to 13. 15. The method according to claim 8, wherein in the second step, the hydrogen permeation opening is formed only immediately above the gate electrode of the semiconductor element. A method for manufacturing a semiconductor device as described above. 16. The method according to claim 3, wherein the first silicon nitride layer is formed to have a smaller film thickness than the silicon oxide layer and the second silicon nitride layer. 16. The method for manufacturing a semiconductor device according to any one of 15. 17. The method according to claim 3, wherein the first silicon nitride layer, the silicon oxide layer, and the second silicon nitride layer are formed in the order of increasing thickness. The method for manufacturing a semiconductor device according to any one of claims. 18. The first silicon nitride layer is deposited to a thickness of about 50 Å, the silicon oxide layer is deposited to a thickness of about 200 Å, and the second silicon nitride layer is deposited to a thickness of about 500 Å. The method of manufacturing a semiconductor device according to claim 17, wherein