JP3468180B2 - Driving capability adjustment circuit and information processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive capacity adjusting circuit and an information processing apparatus, and more particularly to a technology for automatically adjusting the drive capacity of a signal connected to a memory.

[0002]

2. Description of the Related Art Most of the main memory of an information processing apparatus is composed of a memory module having a memory chip mounted on a small board. Since the memory module can be mounted on the connector mounted on the substrate of the main storage unit and can be easily attached and detached, it is possible to add memory modules as needed to obtain a desired memory capacity. Therefore, the load on the signal supplied to the memory module varies depending on the number of mounted memory modules.

There are two types of memory modules, one having a buffer circuit for distributing signals to a plurality of memory chips mounted on the memory module and the other having no buffer circuit. In the type in which the buffer circuit is mounted, the signal load is one of the buffer circuits, but in the type in which the buffer circuit is not mounted, the signal load is the number of memory chips mounted in the memory module. If a memory chip is installed, the load will be eight times as large. Therefore, the load of the signal supplied to the memory module varies greatly depending on the type.

Further, the waveform of the signal supplied to the memory module changes intricately depending on the number of mounted memory modules, their types, and their mounting positions. For this reason, it is not possible to avoid the effect that the operation becomes unstable due to the distortion of the waveform of the signal, etc., simply by selecting the driving capacity more than necessary,
It is necessary to set the optimum driving capability that can avoid the distortion of the signal waveform.

Conventionally, in order to cope with the above load fluctuation and waveform distortion, means for changing the driving ability of the output circuit of the signal supplied to the memory module is provided on the substrate in the device and manually switched. While adjusting. In addition, as a method for automatically selecting the driving ability, Japanese Patent Laid-Open No. HEI-8
No. 305629 discloses that the identification information of the mounted memory module is read and the driving capability is automatically changed based on the read identification information.

[0006]

However, the above-mentioned conventional technique has a problem that manual operation is required to set the driving ability and it takes time to set.

Further, in the current situation where main memory is becoming faster and faster, in the method of adjusting the driving ability based only on the identification information of the memory module, the type of memory chip mounted on the memory module, the manufacturer, There was a problem that the optimum setting could not be made against the delicate influence due to the difference in characteristics due to the manufacturing time and the like.

[0008]

[0009]

Drive dynamic capability adjusting circuit of the present invention According to an aspect of the one or more signals to be connected to the memory module and can output driver circuit by switching the driving capability to a plurality of values of the driving of the driver circuit A drive capacity control circuit for controlling the capacity, a test execution section for instructing the drive capacity control circuit to switch the drive capacity and executing a test on the memory module, and a test module connected to the memory module An SPD control circuit for reading identification information, wherein the test execution unit has a buffer circuit included in the identification information read by the SPD control circuit.
Refer to the type information indicating
If yes, set the smallest drive capacity first and type
If the information does not have a buffer circuit, the largest drive first
The capability is set and the driving capability of the driver circuit is sequentially switched and tested, and based on the test result, the most
It has a means to set the driving capacity that can secure a large margin.

[0010]

In the first information processing apparatus of the present invention, the memory capacity can be changed by selecting the number of memory modules to be mounted, and the driving ability of the signal connected to the memory module can be switched to a plurality of values and output. Driver circuit, a driving capability control circuit for controlling the driving capability of the driver circuit, a memory control unit for controlling access to the memory module, and an SPD for connecting with the memory module and reading identification information of the memory module A control circuit, and the memory control unit indicates whether there is a buffer circuit included in the identification information read by the SPD control circuit .
If there is a buffer circuit if the type information is
In case of
If there is no buffer circuit, set the largest drive capacity first.
Constant and tested by sequentially switching the driving capability of the driver circuit, automatically most margin on the basis of the test results
It has a means for setting a driving capacity that can secure a large value.

[0012]

According to the second information processing apparatus of the present invention, the memory capacity can be changed by selecting the number of memory modules to be mounted, and the driving ability of the signal connected to the memory module can be switched to a plurality of values and output. Driver circuit, a driving capability control circuit for controlling the driving capability of the driver circuit, a memory control unit for controlling access to the memory module, and an SPD for connecting with the memory module and reading identification information of the memory module A control circuit,
The CPU includes a CPU, and the memory control unit has command processing means for receiving a command from the CPU and controlling switching of the driving capability of the driver circuit and reading of identification information of the memory module by the SPD control circuit. The CPU determines whether or not there is a buffer circuit included in the identification information read by the SPD control circuit using the command.
Refer to the type information shown, and the type information has a buffer circuit
In the case of
If there is no buffer circuit in the report, the drive capacity is the largest first.
Force is set, the drive capability of the driver circuit is sequentially switched, and a test is performed.
It has a means to set the driving capacity that can secure a large engine.

The third information processing apparatus of the present invention is the first or
The second information processing apparatus has a bidirectional driver circuit that connects the address signal and the control signal of the memory module to the driver circuit, and connects the address signal and the control signal of the memory module to the data signal of the memory module.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows the first of the present invention.
It is a block diagram of an embodiment of. DIMM (Dual
Inline Memory Module) 5
1. The DIMM 52 is a memory module and is made of a small board having a connector part on which a plurality of memory chips such as DRAM are mounted. Usually, a plurality of boards are mounted to form a memory, and the number and type of mounting can be changed. Can change the memory capacity. Although only two are shown in FIG. 1, the number of mountings varies depending on the memory capacity, and the maximum number of mountings is usually several to several tens, although it varies depending on the information processing apparatus. In a device having a large maximum mounting number, a plurality of driver circuits 41 described below may be arranged and shared to connect signals to the DIMM.

The driver circuit 41 comprises a plurality of driver circuits 41-1 (FIG. 2) for outputting address signals, control signals and the like to the DIMMs 51 and 52.
Reference numeral 1-1 is composed of a plurality of driver gates, and the driver gate is selected by an instruction from the drive capacity control circuit 31. The bidirectional driver circuit 42 sends the data signal to the DIMM 5
The output of the driver gate is controlled by an instruction from the memory control unit 10, which is composed of a driver gate for outputting to the first and the second 52 and a receiver gate for receiving the data signal from the DIMMs 51 and 52. In a device in which the load of data signals becomes large, it is also effective to have a plurality of driver gates and adjust the driving capability like the driver circuit 41.
In FIG. 1, the driving capability of the driver gate is not adjusted. A detailed circuit diagram of the driver circuit 41 is shown in FIG.

The drive capacity control circuit 31 is a memory control unit 10.
According to the instruction from, the setting information of the driving capability of the driver circuit 41 is held and the selection signal X76 is output to the driver circuit 41. SPD (Serial Presence D)
The control circuit 32 is a circuit which is connected to the DIMMs 51 and 52 and reads out whether or not each DIMM has a buffer circuit and identification information such as a memory capacity through a serial interface.

The memory controller 10 includes DIMMs 51 and 52.
Is a circuit for controlling access to the test execution unit 11
Is included. The test execution unit 11 is a circuit that changes the drive capacity of the driver circuit 41, writes test data, checks the read data, and sets the optimum drive capacity. The signal X61 is a signal including address and command information sent from the higher-level device, the signal X62 is write data sent from the higher-level device, and the signal X63 is read data returned to the higher-level device. Signal X81 is signal X
A signal converted into an address signal and a control signal for the DIMMs 51 and 52 based on 61 and driven by the driver circuit 41, and X82 is a data signal of the DIMMs 51 and 52.

FIG. 2 is a detailed circuit diagram for one signal in the driver circuit 41. In the entire driver circuit 41, the driver circuits 41-1 in FIG. 2 are assembled by the number of signal lines X81. The outputs of the driver gates 43 to 47 are ORed to become the output signal X81-1. The drive capability control circuit 31 determines which driver gate output is valid.
It is possible to make adjustments in the range of 1 to 5 times that of one driver gate depending on the number of driver gates that are valid in FIG. X76 is a collective expression of X76-1 to X5, and actually consists of five signals.
Are distributed to all the circuits 41-1 that configure the above.

As described above, five types of drive capabilities can be selected in FIG. 2, but if the drive capabilities of the respective driver gates are set to 1, 2, 4, 8, and 16 times. 1
A wide range of adjustment from double to 31 times is possible, and
Finer adjustment is possible by combining a driver gate with a small drive capacity for fine adjustment and a driver gate with a large drive capacity for coarse adjustment. Further, the number of driver gates does not have to be 5, and if the number of driver gates is increased, finer adjustment can be performed, but since the circuit amount increases, it may be determined according to the situation.

Next, the operation of the embodiment of the present invention will be described. The drive capacity is adjusted when the DIMM is first mounted, and then the DIM is adjusted by increasing or decreasing or replacing the DIMM.
It needs to be implemented when M is changed. When the mounting of the DIMM is changed, it is generally performed in the power-off state, and therefore the drive capability may be adjusted when the DIMM is started by turning on the power. Upon receiving the power supply confirmation signal X64 transmitted when the power is turned on, the memory control unit 10 activates the test execution unit 11 after initializing the inside.

FIG. 3 is a flow chart for explaining the operation of the test execution unit 11 or 21. When the test execution unit 11 is activated, the SPD control circuit 32 causes the DIMM 51,
The identification information 52 is read (S901). An address area to which each DIMM is allocated is obtained from the information on the memory capacity in the read identification information, and one or more addresses in the area are extracted for each DIMM (S902).

Next, it is checked from the read identification information whether the DIMMs 51 and 52 are of a type having a buffer circuit (S903). If the DIMMs 51 and 52 are of a type having a buffer circuit, the smallest driving capability is obtained (S904). If it is not the type that mounts the
Set 5) and start the test. The setting information of the driving capacity to be set is provided from the test execution unit 11 to the driving capacity control circuit 3
Sent to 1. When the drive capacity control circuit 31 receives the setting information, it holds the setting information and outputs the output signal X7 according to a predetermined method.
Convert to 6 and output. The driver circuit 41 outputs the signal X76
Enable the output of the driver gate specified according to
The output is switched to the designated drive capacity. This allows
The address signal output from the memory control unit 10 and the control signal X71 are set to the DIMM with the set driving capability.
It is ready to be sent to 51, 52.

In this state, predetermined test data is written in the address extracted in S903, and then read and read to see if the read data and the written data match. By executing this for all the extracted addresses, it is determined whether all DIMMs can be normally accessed. If there is a mismatch in any one of the addresses, the test result is determined to be abnormal (S906),
The test result is held (S907).

If the first test result is normal, the driving capability is changed and the operations from S906 are repeated. The drive capacity is changed by increasing the drive capacity by 1 when the DIMM is a type equipped with a buffer circuit, and by decreasing the drive capacity by 1 if not (S90).
9). When the test result changes from normal to abnormal (S91
0), or the test ends at the time when the test with all driving capabilities ends (S908). If the first test result is abnormal, the process proceeds from S910 to S907,
Switch the drive capacity and continue the test. Finally, the test result is judged, the driving capability is determined at the point where the largest margin can be secured, and the setting information is sent to the driving capability control circuit 31 for setting (S911).

As described above, when the apparatus is started up, the drive capability is automatically switched in order and tested, and the actually mounted DIMM 5 is based on the test result.
It is possible to set the optimum driving ability for 1, 52.

In the above-described first embodiment, the test execution unit 11 is provided in the memory control unit 10. However, the function of the test execution unit 11 is provided in the CPU (central processing unit) and executed. Is also influential. This will be described below as a second embodiment.

FIG. 4 is a block diagram of the second embodiment, and those having the same functions as those in the first embodiment are given the same numbers as in FIG. CPU 20 outputs signals X61 to 6
3 is connected to the memory control unit 12. X61
˜63 may be configured by a bus, and are generally connected to an input / output control unit, but they are omitted in FIG. The means corresponding to the test execution unit 11 is the test execution unit 21 in the CPU 20. The test execution unit 21 uses the CP
From U20 to the memory control unit 12, the drive capacity control circuit 31
By sending a command instructing control to the SPD control circuit 32 or the SPD control circuit 32, the test execution unit 1 of the first embodiment
The same process as 1 can be executed.

The memory control unit 12 does not include the test execution unit 11, but instead, the above-mentioned drive capacity control circuit 31 and SP.
A command processing unit 13 that receives a command instructing control of the D control circuit 32 and controls the drive capacity control circuit 31 and the SPD control circuit 32 is provided. Drive capacity control circuit 31, SPD control circuit 32, driver circuit 4
1, the bidirectional driver circuit 42, and the DIMMs 51 and 52 have the same configuration as the first embodiment and perform the same operation. Therefore, as compared with the first embodiment, the driver circuit 4 of FIG.
The detailed circuit diagram of No. 1 is the same, and the flowchart of FIG. 3 is also executed by the test execution unit 21 in the CPU 20 instead of the test execution unit 11, and that the drive capability control circuit 31 and the SPD control are executed by the command from the CPU 20 The processing contents are the same except that the circuit 32 is controlled.

With respect to the operation of the second embodiment, the part different from that of the first embodiment will be mainly described. The power supply confirmation signal X64 output when the power is turned on is supplied to the memory control unit 12 and the CPU 20. When the memory control unit 12 receives the signal X64, the memory control unit 12 initializes the inside of the memory control unit 12 to C
The state of waiting for a request from the PU 20 or the like is entered. The initialization program is started by the signal X64, and the CPU 20 starts initialization in the apparatus. Memory (DIM
M51, 52) is initialized, but the adjustment of the driving capability for the memory needs to be performed before the initialization of the memory. Therefore, the test execution unit 21 is activated from the initialization program before the memory initialization is executed.
Alternatively, the test execution unit 21 may be incorporated in the initialization program.

Since the operation contents are the same as those in the first embodiment except the procedure for controlling the drive capacity control circuit 31 and the SPD control circuit 32, the test execution unit 21 outputs the drive capacity control circuit 31 and the SPD. A procedure for controlling the control circuit 32 will be described. In S901 of FIG. 3, the test execution unit 21
When the identification information of the DIMMs 51 and 52 is read by the SPD control circuit 32, the DIMM identification information read command is sent to the memory control unit 12 by the signal X61. The command processing means 13 in the memory control unit 12 receives the above command, decodes the content of the request, and sends to the SPD control circuit 32 a DIMM.
It is instructed to read the identification information of 51 and 52. SPD
In response to the instruction, the control circuit 32 reads the identification information of the DIMMs 51 and 52 and sends it back to the command processing means 13. The command processing means 13 sends the read data to the signal X6.
It returns to CPU20 in 3.

Next, in S904 or S905 of FIG. 3, when setting the driving capability, the driving capability setting command is sent to the signal X61, and the command processing means 13 receives the setting information sent from the test execution unit 21. Based on this, the setting information is sent to the drive capacity control circuit 31. The drive capacity control circuit 31 switches the drive capacity of the driver circuit 41 according to the instruction.

As described above, the drive performance control circuit 31 and the SPD control circuit 32 can be controlled from the test execution unit 21 as in the case of the test execution unit 11 of the first embodiment. The writing and reading of the test data to and from the DIMMs 51 and 52 can be executed by a normal memory access command issued from the CPU 20, and the other processes of FIG. 3 are performed by the test execution unit 21 instead of the test execution unit 11. The operation is the same only when executed.

The test execution unit 21 of the second embodiment is actually realized by a program executed on the CPU 20, but in the case of the test execution unit 11 of the first embodiment, the test execution unit 21 is stored in the memory control unit 10. It may be realized by a dedicated hardware circuit of, or may be realized by a circuit that incorporates a simple program and executes the procedure by the program. Test execution unit 11
The circuit for realizing the above is more complicated and larger in circuit scale than the command processing means 13 because the procedure is controlled.

As described above, in the second embodiment, the memory control unit 12 is the test execution unit 11 of the first embodiment.
Since the relatively complicated circuit of can be eliminated and only the relatively simple circuit for processing the above command can be used, the circuit amount can be reduced. On the other hand, there is also a problem that the time for adjusting the driving ability becomes long and the start-up time also increases. Therefore, it is not simply which one is superior, but the first embodiment and the second embodiment. Which to choose,
The selection may be made according to the conditions required of the information processing device.

[0036]

As described above, according to the first embodiment of the present invention, whether the memory access can be normally executed by changing the driving capability is tested, and based on the result of the test. Since the optimum drive capacity is set by using the optimum drive capacity, the drive capacity suitable for the characteristics of the mounted memory module can be set in the optimum state.

Further, in the second embodiment of the present invention, by providing the CPU with means for executing the test, the first embodiment is provided.
There is an effect that the circuit scale of the memory control circuit for obtaining the same effect as that of the embodiment can be reduced.

Further, the test time can be shortened by reading the identification information of the memory module in advance by the SPD control circuit and determining the test order of the driving capability depending on whether or not the memory module has the buffer circuit. is there.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment.

FIG. 2 is a driver circuit 41 according to the first or second embodiment.
3 is a detailed circuit diagram of FIG.

FIG. 3 is a test execution unit 11 according to the first or second embodiment.
Alternatively, it is a flowchart illustrating the operation of the test execution unit 21.

FIG. 4 is a block diagram of a second embodiment.

[Explanation of symbols]

10 Memory controller 11 Test execution section 31 Drive capacity control circuit 32 SPD control circuit 41 Driver circuit 42 Bidirectional driver circuit 43-47 Driver gate 51 DIMM 52 DIMM 12 Memory controller 13 Command processing means 20 CPU 21 Test execution section

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Claims (4)

(57) [Claims] 1. A driver circuit capable of outputting the drive capability of a signal connected to one or more memory modules by switching it to a plurality of values, a drive capability control circuit for controlling the drive capability of the driver circuit, and the drive capability control. A test execution unit for instructing the circuit to switch the driving capability and executing a test on the memory module, and an SP for connecting to the memory module and reading identification information of the memory module.
A D control circuit, and the test execution unit is a type information indicating presence / absence of a buffer circuit included in the identification information read by the SPD control circuit.
If there is a buffer circuit in the type information, refer to
First, set the smallest driving capacity and buffer the type information.
When there is no circuit, the largest driving capacity is set first, and the driving capacity of the driver circuit is sequentially switched and tested, and the largest margin is automatically set based on the test result.
A drive capacity adjustment circuit characterized by setting a drive capacity that can be secured . 2. An information processing apparatus capable of changing the memory capacity by selecting the number of memory modules to be mounted, and a driver circuit capable of switching the driving ability of a signal connected to the memory module to a plurality of values and outputting the plurality of values. A drive capability control circuit that controls the drive capability of the driver circuit, a memory control unit that controls access to the memory module, and an SPD control circuit that is connected to the memory module and reads identification information of the memory module are provided. The memory control unit includes a type information indicating presence / absence of a buffer circuit included in the identification information read by the SPD control circuit.
If there is a buffer circuit in the type information, refer to
First, set the smallest driving capacity and buffer the type information.
When there is no circuit, the largest driving capacity is set first, and the driving capacity of the driver circuit is sequentially switched and tested, and the largest margin is automatically set based on the test result.
An information processing device characterized by setting a driving capacity that can be secured . 3. An information processing apparatus capable of changing the memory capacity by selecting the number of memory modules to be mounted, and a driver circuit capable of switching the driving ability of a signal connected to the memory module to a plurality of values and outputting the plurality of values. A drive capability control circuit that controls the drive capability of the driver circuit, a memory control unit that controls access to the memory module, an SPD control circuit that is connected to the memory module and reads identification information of the memory module, and a CPU The memory control unit includes command processing means for receiving a command from the CPU and controlling switching of the driving capability of the driver circuit, reading of identification information of the memory module by the SPD control circuit, and the like. the CPU included in the identification information read by the SPD control circuit using the command The type information indicating the presence or absence of that buffer circuit
Refer to, if the type information has a buffer circuit, first
Set the smallest drive capacity and type information is a buffer circuit
If not, first, set the largest drive capacity, switch the drive capacity of the driver circuit in sequence, and perform a test, and automatically determine the largest margin based on the test results.
An information processing device, characterized in that a drive capacity that can be maintained is set. 4. A connecting the address signal and the control signal of the memory module to the driver circuit, the memory module of the data signal line information of claim 2 or 3 drivability is connected to a constant bidirectional driver circuit Processing equipment.