JP3456009B2 - Communication method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a case where time series data such as digital video data and digital audio data is transmitted using a communication control bus (hereinafter abbreviated as "bus") such as P1394 serial bus. The present invention relates to a communication system suitable for.

[0002]

2. Description of the Related Art A system for connecting a plurality of devices by a communication control bus capable of mixing control signals and information signals, such as a P1394 serial bus, and communicating information signals and control signals between these devices is considered. Has been.

FIG. 9 shows an example of such a system. This system includes devices A, B, C, D and E. And between the devices A-B, between A-C, between C-D, and C-E
The parts are connected by a twisted pair cable of P1394 serial bus. These devices are, for example, digital VTRs, tuners, monitors and the like. Since each device has a function of relaying an information signal and a control signal input from the twisted pair cable, this system is equal to a system in which each device is connected to a common bus as shown in FIG.

Data transmission between the devices A to E sharing a bus has a predetermined communication cycle (for example, 125 μse).
It is performed by time division multiplexing for each c). The management of the communication cycle on the bus uses a synchronization packet (cycle start packet: hereinafter referred to as "CQ") indicating that a predetermined device that manages the communication system, for example, the device A, is in communication synchronization, that is, the start of the communication cycle. By transmitting to another device on the bus, data transmission in the communication cycle is started.

The time information on the bus is managed by the clock register of each device. The clock register of each device has a self-cycle (125 μse shown in FIG.
It is reset by CQ every c). Then, during the self cycle, time information is generated by counting the clocks of the respective devices. Therefore, if the communication cycle is ideally repeated every 125 μsec,
As shown in FIG. 11, CQ and the self cycle start at the same time and end at the same time.

The data format transmitted during one communication cycle includes synchronous data such as digital video data and digital audio data (hereinafter referred to as "Iso data") and asynchronous data such as connection control commands (hereinafter referred to as "Async data"). "). Transmission of these two types of data is performed according to the following protocols (1) to (6).

(1) As shown in FIG. 12A, data is transmitted after CQ is transmitted. (2) As shown in FIG. 12A, the priority of the data format to be transmitted after CQ is Asy for Iso data.
higher than the nc data.

(3) As shown in FIG. 12 (a), when the next self cycle starts at the end of communication of Iso data 2, CQ has priority over Async data.
sync data 2 cannot be transmitted in the communication cycle,
It must be transmitted in subsequent communication cycles.

(4) The maximum delay time of CQ is determined by the maximum length of Async data which is predetermined in the system (for example, 41 μsec). (5) As shown in FIG. 12B, when CQ2 is lost due to an abnormality on the bus, each device cannot receive CQ2 normally, and as a result, packets are not transmitted on the bus during the communication cycle. It will not be transmitted. Then, the device managing the communication system transmits CQ3 for the next communication cycle at the same time as the start of the next self cycle.

(6) When at least one of the CQ and the data packet cannot be normally received by the receiving device, the receiving device generates an error code corresponding to the data packet and Instead of a normal data packet. If the CQ cannot be received normally, the CQ may be lost as described in (5) above. In addition, if the data packet cannot be received normally, it may not be received because the data packet is not transmitted as a result of CQ loss on the transmission side, or it may have been received but is not a correct packet (header error, etc.). As a result, there are cases where the data could not be received and cases where there was an error in the data portion of the received packet.

When data is transmitted in accordance with the above protocol, one Iso data packet and one Async data packet are transmitted after the CQ which is the start signal of the communication cycle comes as shown in FIG. One communication cycle until the end is not necessarily finished in 125 μsec.

Next, in the communication system described above, a case will be described in which digital video data and digital audio data (hereinafter referred to as "VTR data") output from a digital VTR are transmitted to another digital VTR as Iso data.

First, when data to be processed in block units such as VTR data is transmitted through a communication system having a communication cycle asynchronous with the block cycle,
As shown in FIG. 13, FIFOs 23 and 24 for temporarily holding data in the digital VTRs 21 and 22 are generally required.

In FIG. 13, V of the digital VTR 21
When transmitting the TR data to the digital VTR 22, first, the VT generated by the VTR main body 25 in the digital VTR 21 is transmitted.
The R data is temporarily stored in the FIFO 23. And FI
The data stored in the FO 23 is sequentially transmitted from the communication control I / F 27 to the digital VTR 22 via the bus in accordance with the communication cycle. The digital VTR 22 sequentially receives the data packets received in each communication cycle.
It is stored in FO24, and finally the VTR main body 26 is FIFO2.
You will receive data from 4.

[0015]

When transmitting VTR data packetized as shown in FIG. 14 using the above-mentioned communication system, if there is always a CQ indicating the beginning of one communication cycle on the bus, As shown in FIG. 15, one VTR data packet in one communication cycle (or one Async data packet if there is an Async data packet)
Is transmitted.

On the other hand, in the device on the VTR data receiving side, unless the CQ or the data packet is lost on the bus due to noise or the like, the same data state as in FIG. 15 (similar to the transmitting side device). CQ or data packet is received in the data state).

However, the digital VT which is the device on the transmitting side
In R21, a data packet is normally transmitted to a normal CQ, but when the receiving device cannot normally receive the CQ or the data packet or both for some reason on the bus, the data packet of the communication cycle Is an error, and the error code is the VTR body 26 on the receiving side.
Transferred to.

Further, as shown in FIG. 16, in the device on the transmission side, the device that manages the above-mentioned communication system outputs C
If Q, for example CQ2, is lost due to noise on the bus, it will not be possible to send data packets in that communication cycle. Therefore, in the digital VTR 21, which is the device on the transmission side, when CQ2 is lost as shown in FIG. 17A, the VTR data packet 2 that should be originally transmitted after CQ2 is transmitted in the communication cycle starting from CQ3. Although it is a conventional method, the method has the following problems (1) and (2).

(1) When the CQ2 is lost in the digital VTR 21 on the transmission side where the size of the FIFO becomes large, if the VTR data packet 2 that should be originally sent in the communication cycle is to be sent in the communication cycle of CQ3, it will be normal. FIFO23 compared to when CQ is received
The time saved in the file becomes longer by one communication cycle, and the block data is periodically transmitted from the VTR main body 25 to the FI.
Considering that data is transferred to the FO 23, the size of the FIFO must be increased by the number of communication cycles in which the CQ is lost, compared with the normal case.

(2) Complicated processing in the device on the receiving side When CQ2 is lost in the digital VTR 21 on the transmitting side, VTR data packet 2 which should be originally sent in that communication cycle is sent in the communication cycle of CQ3. Then, it becomes difficult for the receiving-side digital VTR 22 to uniquely determine the order of the received data packet.

FIG. 17A shows a VTR data packet 2 when CQ2 is lost in the digital VTR on the transmitting side.
17 is an example of transmission of CQ3 in the communication cycle of FIG.
(B) is a digital V of the receiving side that normally received the VTR data packet transmitted in the configuration of FIG.
This is the state of TR.

Further, FIG. 18A shows a digital V on the transmitting side.
This is an example of a state in which a VTR data packet is normally transmitted in TR, and FIG.
When the VTR data packet is normally transmitted as shown in (a), the CQ2 receives the digital VT on the receiving side when receiving.
It is an example of a reception state when only R is lost. FIG.
In (b), if the CQ is lost only on the receiving side, the data packet to be received during the communication cycle is not received at the same time, which is defined by the protocol.

As can be seen by looking at these four states, two state examples on the transmitting side (FIGS. 17A and 18) are shown.
While (a)) is different, the data packet reception state is the same in the two examples on the receiving side (FIGS. 17B and 18B). However, FIG. 17 (b) and FIG.
Normal CQ3 following CQ2 lost in (b)
The numbers of the VTR data packets received during the communication cycle starting from are different, such as VTR data packet 2 in FIG. 17B and VTR data packet 3 in FIG. 18B.

Therefore, unless the VTR data packet transmitted / received in this communication system holds the index indicating the order of the data packet in the VTR data packet, from the receiving side, FIG. 17 (b) and FIG.
In the case of (b), even if the received data packet has the same state, the number of VTR data packet received in the communication cycle starting from the normal CQ received next to the lost CQ may be different, Furthermore, that VT
It is impossible to uniquely determine what number data packet the R data packet is.

Even if the index indicating the order of the data packets is held in the VTR data packet, VQ is lost due to CQ loss in the case of FIG. 18B.
Since it can be determined that the TR data packet 2 is lost only after receiving the VTR data packet 3, it is difficult in time to generate an error code for the lost VTR data packet 2.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a communication method capable of minimizing the size of the FIFO on the transmission side.

The present invention also provides a communication method that facilitates uniquely determining the number of a data packet even if the receiving side loses the synchronization packet or cannot receive the data packet. With the goal.

[0028]

In order to solve the above-mentioned problems, the invention according to claim 1 is a communication system in which data communication is performed by a communication cycle including CQ and data packets, and CQ is lost on the transmitting side. In this case, the data packet to be transmitted is not transmitted in the communication cycle period starting from the CQ.

The invention according to claim 2 is characterized in that, in the invention according to claim 1, when the CQ is lost on the receiving side or the data packet cannot be received normally, data error processing is performed. To do.

Furthermore, the invention according to claim 3 is the same as claim 1.
In the invention according to, the data error processing is performed when at least the data packet cannot be normally received on the receiving side.

The invention according to claim 4 is the invention according to claim 1,
In the invention of 2 or 3, after detecting one of the CQs, the next CQ is detected within the time required for the periodic interval of the synchronization packet.
Is detected, the CQ loss is detected.

The invention according to claim 5 is the invention according to claim 1, 2, 3 or 4, wherein the data to be transmitted is synchronous data and asynchronous data.

[0033]

According to the invention of claim 1, when the device on the transmitting side detects the loss of CQ, it does not transmit the data packet which should be originally transmitted during the communication cycle period starting from the CQ. FIF temporarily stored
The capacity of the storage means such as O may be the same as that at the normal time.

According to the second aspect of the invention, the device on the receiving side performs the data error process when the CQ is lost or the data packet cannot be received normally.
It becomes easy to uniquely determine the number of the received data packet with or without Q loss.

According to the third aspect of the invention, the device on the receiving side performs the data error process at least when the data packet cannot be normally received. Therefore, for example, when a data packet transmitted in a communication cycle period starting from the CQ is received before the CQ loss is detected, the data packet can be normally processed even if the CQ loss is detected later.

According to the fourth aspect of the invention, when the CQ is lost, the device on the transmitting side and the device on the receiving side receive the C
The loss can be detected within the communication cycle beginning with Q.

Further, according to the invention of claim 5, it is possible to communicate synchronous data and asynchronous data.

[0038]

Embodiments of the present invention will be described in detail below with reference to the drawings. (First Embodiment) FIG. 1 is a diagram showing an example of a data state on a bus when CQ is lost on the transmitting side in the first embodiment of the present invention.

In the present embodiment, the transmitting side does not transmit the VTR data packet that should be transmitted in the communication cycle in which the CQ is lost, in the communication cycle. For example, when CQ2 is lost as shown in FIG. 1, in the communication cycle starting from CQ2, the VTR data packet 2 that should originally be transmitted in that communication cycle is discarded in the FIFO. Then, in the communication cycle starting from CQ3, the VTR data packet 3 that should originally be transmitted in that communication cycle is transmitted. By doing so, the size of the FIFO can be suppressed to the minimum size, so that the problem (1) can be solved.

On the receiving side, if the CQ is lost or the data packet is not normally received, an error code corresponding to the data packet is generated and used as a substitute for the normal data packet. And

For example, as shown in FIG. 2 (a), CQ is set on the receiving side.
2 and VTR data packet 2 cannot be received, and when CQ2 is normally received on the receiving side as shown in FIG. 2B, but VTR data packet 2 is not normally received, the VTR Data packet 2 cannot be received after that, and the state is reported to the VTR main unit as a data error. Specifically, an error packet is sent instead of the VTR data packet 2 which is the originally received packet. When a packet is normally received in the next communication cycle starting from CQ3, the packet is supposed to be the original packet VTR data packet 3 (assuming that the VTR data packet 2 which should be originally received in the previous communication cycle was received. And then received as VT
Send to R body. As a result, the VTR main body can still receive the original packet during the communication cycle in which the original packet should be received.

In this way, even if CQ is normally received in a certain communication cycle, the VTR data packet that should be originally received in the subsequent communication cycles is uniquely determined. The state in which the VTR data packet 2 is received in the normal communication cycle following the lost CQ as in (b) can no longer occur, and the problem (2) can be solved.

Next, referring to FIGS. 3 and 4, this C
The conditions for detecting the Q loss will be described. Figure 3
When CQ2 is lost at, the VTR data packet 2 which should be originally transmitted needs to be discarded from the FIFO during the communication cycle starting from CQ2. Therefore, the transmitting digital VTR 21 must detect the loss of CQ2 during the communication cycle starting from CQ2. The condition required for the timing to be detected is to leave in the communication cycle the time necessary to completely discard the data to be discarded from the FIFO during the communication cycle. In FIG. 3, VTR data packet 2 in FIFO
Assuming that the time required for discarding the data from the FIFO is t0, the digital VTR 21 on the transmitting side must detect the loss of CQ2 at the latest timing T1 t0 earlier than the timing T2 at the beginning of the next communication cycle.

However, according to the conventional method, the digital VTR
21 can detect the loss of CQ2 as shown in FIG.
It is the timing T2 when CQ3 is normally transmitted next to the communication cycle in which Q2 is lost. However, when the loss of CQ2 is detected at this timing, the time t1 (the time when CQ3 is transmitted + g when CQ3 is transmitted) until the VTR data packet 3 of the communication cycle starting from CQ is transmitted.
aptime) is much smaller than the time t0 required to discard the VTR data packet 2, the VTR data packet 2 to be transmitted in the previous communication cycle is discarded from the FIFO within t1 and starts from CQ3. It is temporally impossible to put the VTR data packet 3 to be transmitted in the communication cycle into a state in which it can be immediately transmitted.

Similarly, in the digital VTR 22 on the receiving side, when the CQ2 is lost, an error code corresponding to the VTR data packet 2 to be received in the communication cycle in the communication protocol is generated and the VTR main body 26 is caused. It has to be sent, but conventional CQ
When CQ loss is detected at the loss detection timing T2, an error code is generated and the VTR main unit 2
There is no time to send to 6.

Therefore, in this embodiment, in order to allow a sufficient time for discarding the packet in the FIFO, the timing at which CQ2 is considered to be lost during the communication cycle in which CQ2 is lost is predicted and detected. Further, in order to allow sufficient time for generating the error code, the timing at which CQ2 is considered to have been lost is predicted and detected during the communication cycle in which CQ2 has been lost.

Next, the detection timing of CQ loss in this embodiment will be described with reference to FIG. In a certain communication cycle, the latest timing T0 at which CQ may come from the above-mentioned protocol (4) is about 50 μsec after the self cycle starts (the maximum delay time of Async data in the immediately preceding communication cycle ( 41 μsec) + gapti until the next communication cycle
me (0.04 to 0.05 μsec) + time for transmitting CQ (several μsec)).

Therefore, in the state where CQ is normally transmitted, the self cycle starts 50 even in the worst case.
CQ must be transmitted at the time when μsec has elapsed. Therefore, in the present embodiment, for example, in the case of CQ2,
In the communication cycle in which CQ2 is lost, the VTR data packet 2 that should originally be transmitted in the communication cycle is FIF
The time t0 for discarding from O is the self cycle length 125μ
The time T1 subtracted from sec was set as the latest timing at which the loss of CQ2 should be detected. Then, within about 50 μsec after the start of the self-cycle, until the time T0, C
If Q2 does not come, it means that CQ2 has been lost on the bus and if so, by the time T1 VTR data packet 2 in the FIFO can begin to be discarded. In reality, if CQ2 does not arrive even after the time T0, the discarding of the VTR data packet 2 in the FIFO is started from the time T0 without waiting for the time T1. Note that at t3 in FIG. 5, the packet transmission is completed,
This is the time until CQ comes for the next communication cycle.

The case of detecting the CQ loss in the transmission side device has been described above, but the same method can be used in the reception side device.

FIG. 6 shows the configuration of the device on the transmission side in the first embodiment of the present invention. This circuit is used when transmitting VTR data, and is present inside the FIFO 23 and the communication control I / F 27 in the digital VTR 21 shown in FIG.

First, the VT generated by the 25 VTR bodies
The R data packet is written by the packet writing circuit 1
Write to the FIFO 23 packet by packet. The written packet is accumulated in the FIFO 23 until it is read by the packet reading circuit 3. And F
When the packet is read from the IFO 23, the VTR data packet to be transmitted thereafter is written in the FIFO 23 by the packet writing circuit 1. This operation is repeated without depending on the operation of other circuits as long as the FIFO 23 has a free capacity.

The self-cycle counter 4 changes the counter value a from 0 sec to 125 by the clock CLK in the self-device.
Count up to μsec. When the counter value a of the self-cycle counter 4 reaches 125 μsec, it is reset to 0 sec by the counter value reset command b output from the counter reset circuit 5, and the clock CLK is again counted up to 125 μsec.
Further, the counter value a of the self-cycle counter 4 is corrected for each CQ by the self-cycle counter value g written in the CQ transmitted from the device managing the communication system, which is absolute in the communication protocol. To be done. This operation is repeated without depending on the operation of other circuits.

The CQ detection circuit 7 can always see the state on the reception transmission line 11, and if the CQ is transmitted from the media access control unit 9 on the reception transmission line 11, the CQ detection circuit 7 detects that the CQ is normal. The signal d for reporting to the CQ arrival determination circuit 8 that the signal has arrived at is output. The value of the self-cycle counter 4 when the CQ normally reaches should be smaller than T0 (here, about 50 μsec) on the protocol. T0
<Self-cycle determination circuit 6 compares the value a of self-cycle counter 4 with T0, and determines the determination value c according to the magnitude relationship.
To the CQ arrival determination circuit 8.

The CQ arrival determination circuit 8 is based on T0 <the output c of the self-cycle determination circuit 6 and the output d of the CQ detection circuit 7,
When it is determined that the CQ has arrived normally, the switch 31 in the packet reading circuit 3 is set to the normal reading circuit 3
Close to 3. Then, the CQ arrival determination circuit 8 closes the switch 31 of the packet read circuit 3 toward the normal read circuit 33, and then, until the read end report f from the packet read circuit 3 is obtained, T0 <self cycle determination circuit 6 The judgment value c of is invalidated.

When the switch 31 is closed, the normal read circuit 33 reads the data in the FIFO 23 packet by packet in accordance with the access command h from the media access control unit 9. When the reading of one packet is completed, the CQ arrival determination circuit 8 is read and the end report f is issued.
Is sent. Upon receiving this report f, the CQ arrival determination circuit 8 opens the switch 31 in the packet reading circuit 3.

If T0 <the judgment value c by the self-cycle judgment circuit 6 is true before the CQ detection report signal d by the CQ detection circuit 7, it is interpreted that CQ is lost on the reception transmission line 11. Then, the CQ arrival determination circuit 8 closes the switch 31 in the packet read circuit 3 to the packet discard circuit 32.

When the switch 31 is closed, the packet discard circuit 32 immediately starts reading the packet in the FIFO 23, and the read data is invalidated as it is. When the packet discarding circuit 32 finishes reading one packet of data, it sends out a reading end report signal f to the CQ arrival determination circuit 8. Upon receiving this signal f, the CQ arrival determination circuit 8 opens the switch 31.

The CQ arrival determination circuit 8 waits for the CQ detection report d from the CQ detection circuit 7 and the determination result c of T0 <self cycle determination circuit 6 again after the completion report f read from the packet read circuit 3 comes. .

FIG. 7 shows the configuration of the receiving side device in the first embodiment of the present invention. In this figure, the same numbers are assigned to the parts corresponding to the devices on the transmission side in FIG. Further, this circuit is a circuit used at the time of receiving VTR data, and is present inside the FIFO 24 and the communication control I / F 28 in the digital VTR 22 shown in FIG.

The operation of the apparatus on the receiving side is basically the same as the operation of the apparatus at the time of transmission described above. However, since the write circuit at the time of transmission becomes the read circuit at the time of reception and the read circuit at the time of transmission becomes the write circuit at the time of reception, the packet write circuit 1 is the packet read circuit 13 and the packet read circuit 3 is the packet write circuit 14. Then, the packet discard circuit 32 becomes the error code writing circuit 142, the normal read circuit 33 becomes the normal write circuit 143, and the read end report f becomes the write end report i.

Further, the CQ arrival determination circuit 8 determines whether or not CQ has arrived in a certain communication cycle, and the packet reception determination circuit 17 determines whether or not a packet is normally received in that communication cycle.

The packet reception determination circuit 17 first
When the error code or the packet is normally written in the FIFO 24 in the previous communication cycle, the write end report i arrives from the packet write circuit 14 to the packet reception determination circuit 17. As a result, the packet reception determination circuit 17 knows that the previous communication cycle ends and the next communication cycle starts.

When a new communication cycle starts, the packet reception judgment circuit 17 receives the packet reception detection report m from the packet reception detection circuit 16 or the communication cycle end from the media access control unit 9 before receiving the packet reception detection report m. The determination result k is distinguished depending on whether the report j is received.

If the packet reception detection report m comes first after entering a new communication cycle, the packet reception determination circuit 17 determines that the packet is normally received,
The determination result k is reported to the switch control circuit 18. On the other hand, when a new communication cycle starts and the communication cycle end report j is received from the media access control unit 9 before the packet reception detection report m by the packet reception detection circuit 16, the packet reception determination circuit 17 determines the communication. It is determined that the packet cannot be normally received within the cycle, and the result k is reported to the switch control circuit 18.

After sending the judgment result k to the switch control circuit 18, the packet reception judgment circuit 17 waits for the write end report i from the packet write circuit 14 to know the end of the communication cycle.

The above is the operation of the circuit for determining whether or not a packet is normally received during a certain communication cycle.

The switch control circuit 18 determines whether the switch 141 in the packet writing circuit 14 is closed to the error code writing circuit 142 or the normal time writing circuit 143. The switch control circuit 18 generates a switch control signal based on the judgment result e ′ of the CQ arrival judgment circuit 8 and the judgment result k of the packet reception judgment circuit 17, and operates as in (1) to (4) below.

(1) The result of the CQ arrival determination circuit 8 is "CQ
Is normally received ”and the result of the packet reception determination circuit 17 is“ normally received packet ”, that is, in the normal state, the switch 141 is closed to the normal time writing circuit 143.

(2) The result of the CQ arrival determination circuit 8 is "CQ
Is received normally ”and the result of the packet reception determination circuit 17 is“ the packet is not received normally ”,
The switch 141 closes the error code writing circuit 142.

(3) The result of the CQ arrival determination circuit 8 is "CQ
Is not normally received ”, and the result of the packet reception determination circuit 17 is“ normally received packet ”,
The switch 141 closes the error code writing circuit 142.

(4) The result of the CQ arrival determination circuit 8 is "CQ
Is not normally received ”and the result of the packet reception determination circuit 17 is“ not normally received packet ”, the switch 141 determines that the error code writing circuit 142
Close to.

The above is the operation of the switch control circuit 18. After sending the switch control signal n, the switch control circuit 18 waits for the judgment results e ′, k from the upper two judgment circuits 8 and 17 to arrive.

(Second Embodiment) First, with reference to FIG. 8, a description will be given of a process and a problem when CQ is lost only on the receiving side in the communication system of the first embodiment.

In this case, as shown in FIG. 8A, the CQ is normally received at the transmitting side, so that the packet is normally transmitted. However, as shown in FIG.
Although Q2 is lost, the packet Iso data packet 2 from the transmission side is sent before the timing T0 of CQ2 loss detection.
Is received. However, in the first embodiment,
When the loss of CQ2 is detected, it is processed as a data error, and therefore it cannot be used even if the packet is normally received.

Therefore, in this embodiment, when the data packet is normally received on the receiving side, the data error processing is not performed even if the synchronization packet is lost, and the data packet is processed as normal data.

The configuration of the device on the receiving side for implementing the communication system of this embodiment is the same as that of FIG. 7 except for the control method of the switch control circuit 18. The switch control circuit 18 generates a switch control signal based on the judgment result e of the CQ arrival judgment circuit 8 and the judgment result k of the packet reception judgment circuit 17, and operates as in the following (1) to (4).

(1) The result of the CQ arrival determination circuit 8 is "CQ
Is normally received ”and the result of the packet reception determination circuit 17 is“ normally received packet ”, that is, in the normal state, the switch 141 is closed to the normal time writing circuit 143. This is the same as the first embodiment.

(2) The result of the CQ arrival determination circuit 8 is "CQ
Is received normally ”and the result of the packet reception determination circuit 17 is“ the packet is not received normally ”,
The switch 141 closes the error code writing circuit 142. This is also the same as in the first embodiment.

(3) The result of the CQ arrival determination circuit 8 is "CQ
Is normally received ”and the result of the packet reception determination circuit 17 is“ normally received packet ”, that is, when the above-mentioned problems are mentioned, the switch 141 is different from the first embodiment. The writing circuit 143 is closed at the normal time.

(4) The result of the CQ arrival determination circuit 8 is "CQ
Is not normally received ”and the result of the packet reception determination circuit 17 is“ not normally received packet ”, the switch 141 determines that the error code writing circuit 142
Close to. This is also the same as in the first embodiment.

As described above, according to this embodiment, at least when a data packet cannot be received normally, it is processed as a data error. Therefore, when the data packet is received before the loss of the synchronization packet is detected, the data packet can be processed normally.

Although each of the above embodiments relates to a system for transmitting VTR data via the P1394 serial bus, the present invention can be applied to a system for transmitting digital audio data or a system for transmitting computer data.

[0083]

As described above in detail, according to the present invention, the size of the storage means such as the FIFO provided in the device on the transmission side may be the minimum size. Further, even when the receiving side cannot receive at least one of the synchronization packet and the data packet, it becomes easy to uniquely determine the number of the received data.

Further, when the receiving side device receives the data packet transmitted in the communication cycle period starting from the synchronization packet before detecting the loss of the synchronization packet, it detects the loss of the synchronization packet later. Can process data packets normally.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a state of data on a bus when CQ is lost in the first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a state of data on the receiving side in the first embodiment of the present invention.

FIG. 3 is a diagram showing conditions required for detection of CQ loss on the transmission side.

FIG. 4 is a diagram illustrating a conventional CQ loss detection timing.

FIG. 5 is a diagram showing a timing of detecting a CQ loss in the embodiment of the present invention.

FIG. 6 is a diagram showing an example of a configuration of a device on the transmission side in the first embodiment of the present invention.

FIG. 7 is a diagram showing an example of a configuration of a receiving-side device in the first embodiment of the present invention.

FIG. 8: CQ is normally received on the transmitting side, and CQ is received on the receiving side.
It is a figure which shows the example of the state of the data at the time of losing.

FIG. 9 is a diagram showing an example of a communication system to which the present invention is applied.

10 is a diagram equivalently describing the communication system of FIG.

FIG. 11 is a diagram showing an example of ideal data states on a bus in a communication system to which the present invention is applied.

FIG. 12 is a diagram showing a normal example and an abnormal example of actual data states on a bus in a communication system to which the present invention is applied.

FIG. 13 is a diagram showing a basic configuration of a digital VTR to which the present invention is applied.

14 is a diagram showing an example of a structure of data transmitted by the digital VTR of FIG.

15 is a diagram showing an example of an actual data state on a bus when the data of FIG. 14 is transmitted.

FIG. 16 is a diagram showing an example of a state of data when CQ is lost on the bus.

FIG. 17 shows a case where CQ is lost only on the transmission side,
It is a figure which shows the example of the state of the data of the conventional transmitting side and the receiving side.

FIG. 18 shows a case where CQ is lost only on the receiving side,
It is a figure which shows the example of the state of the data of the conventional transmitting side and the receiving side.

[Explanation of symbols]

CQ ... Cycle start packet, CC ... Communication cycle, SC ... Self cycle, Iso data ... Synchronous data, Async data ... Asynchronous data

─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-7-321759 (JP, A) Michael Teener, A bus on a diet-the serial bus alternate-an introducer on to the PB Higher Perfume. Compcon Spring '92. Thirty-Event h IEEE Computer Society International Conference, Digest of Papers, USA, IEEE E, February 24, 1992, P.P. 316-321 (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 12/28

Claims (5)

(57) [Claims] 1. In a communication method for performing data communication in a communication cycle including a synchronization packet indicating synchronization of communication and a data packet, when the synchronization packet is lost on the transmitting side, transmission is performed in a communication cycle period starting from the synchronization packet. A communication method characterized by not transmitting data packets that should be transmitted. 2. When the synchronization packet is lost or the data packet cannot be received normally at the receiving side,
The communication method according to claim 1, wherein data error processing is performed. 3. The communication system according to claim 1, wherein at least the data packet is not normally received at the receiving side, the data error processing is performed. 4. After detecting the one of the synchronization packet, synchronization
The communication system according to claim 1, 2 or 3, wherein the loss of the next synchronization packet is detected by not detecting the next synchronization packet within the time required for the packet cycle interval . 5. The communication system according to claim 1, wherein the data is synchronous data and asynchronous data.