JP3328211B2 - Data stream controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data stream control apparatus for handling compressed streams such as MPEG audio and AC-3, and more particularly to a data stream control apparatus capable of skipping compressed data to the head of the next frame. .

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing an example of the configuration of a conventional data stream control device for handling a compressed stream such as MPEG audio. An address generation unit 110, a buffer 120, a control unit 130, a shift register 140
, A decoding unit 150, and a parallel / serial converter (P /
S) 160.

[0003] The address generation unit 110 receives the write signal 17
Each time 0 is added, the write address 111 for the buffer 120 is incremented by one, and each time the read signal 132 is added, the read address 112 for the buffer 120 is incremented by one.
I do. However, if the write address 111 and the read address 112 indicate the end of the buffer 120 when the write signal 170 and the read signal 132 are added, the write address 111 and the read address 112 indicate the head.

The buffer 120 has a capacity to store at least one frame of compressed data. The buffer 120 stores one word of input data 180 input in synchronization with a write signal 170 in accordance with a write address 111, and reads the data. In accordance with the signal 132 and the read address 112, the stored data for one word is output.

[0005] When a request signal 151 for requesting compressed data and a request bit length 152 indicating the bit length of the requested data are added from the decoding unit 150, the control unit 130 converts the request bit length 152 into a parallel / serial converter 160. Is checked to see if it is larger than the number of bits of the unconverted (unoutput) data remaining in.

When the required bit length 152 is larger, the read signal 132 is first output to output the buffer 1
20 to output one word of compressed data,
Required bit length 15 from parallel / serial converter 160
Two-minute serial data is output, and the serial data output from the parallel / serial converter 160 is shifted to the top of the shift register 140. Then, when the requested data is arranged on shift register 140, control unit 130 outputs ready signal 131. Thereby, the decoding unit 150 takes in the data from the shift register 140 and performs the synchronization detection processing, the decoding processing, and the like.

On the other hand, if the required bit length 152 is equal to or less than the number of bits of the unconverted data remaining in the parallel / serial converter 160, the requested data is
Since the data remains in the parallel / serial converter 160, the read signal 132 is not output, and the data of the required bit length 152 is output from the parallel / serial converter 160, and the data is shifted to the top of the shift register 140. . Then, when the requested data is prepared on the shift register 140, the ready signal 131 is output.

[0008]

The above-described conventional data stream control device converts the data temporarily stored in the buffer 120 into data having the length requested by the decoding unit 150 from the parallel / serial converter 160. Since the data is simply extracted using the shift register 140 and output to the decoding unit 150, there is a problem that if an error occurs in the compressed data, noise is generated in the reproduction result.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for reproducing a reproduction result by discarding a frame containing compressed data in which an error has occurred and enabling decoding from the beginning of the next frame when an error occurs in the compressed data. To prevent noise from being generated.

Japanese Patent Application Laid-Open No. 8-18984 discloses a plurality of frame memories for storing decoded data, a switch for selecting a frame memory for writing decoded data from the plurality of frame memories, and a plurality of frame memories. A technique for providing a switch for selecting a frame memory from which decoded data is read out of the memory and performing error recovery by controlling the switching of each switch when an error occurs is described. The error recovery is performed based on the compressed data, and the error recovery is not performed by operating the compressed data. Further, in the technique described in the above publication, it is necessary to provide a plurality of frame memories for storing decoded data, and the decoded data has a larger data amount than the compressed data. More and the equipment becomes more expensive.

[0011]

To achieve the above object, the present invention provides a buffer for storing at least one frame of compressed data, and an address for generating a write address and a read address for the buffer in accordance with a write signal and a read signal. And a shift register that holds the compressed data read from the buffer and shifts the data in accordance with a shift signal.
When taking in the compressed data, a request bit length indicating the length of the compressed data to be taken is output, and if an error is detected in the compressed data corresponding to the requested bit length taken from the shift register, the bits up to the head of the next frame are detected. A decoding unit that calculates and outputs a skip bit width represented by a number, and when a required bit length is output from the decoding unit, the required bit length and the number of bits of uncompressed compressed data in the shift register. And outputs to the shift register a shift signal for performing a shift corresponding to the required bit length previously output from the decoding unit, and skips from the decoding unit. When the bit width is output, the address of the buffer in which the head of the next frame is stored is obtained and output, and the next frame is output. Determine the shift amount for shifting the head portion of the frame in position on the shift register,
A control unit that outputs a shift signal corresponding to the shift amount to the shift register; and reads one of a read address output from the address generation unit and an address output from the control unit to the buffer. And a selector for setting an address.

When detecting that there is an error in the fetched data, the decoding section outputs a skip bit width represented by the number of bits up to the head of the next frame. When the skip bit width is output, the control unit obtains and outputs the address of the buffer in which the head of the next frame is stored. As a result, an address from the control unit is added to the buffer via the selector, and the head of the next frame stored at that address is output. This data is held in the shift register. Thereafter, the control unit outputs a shift signal for shifting the head of the next frame to a predetermined position of the shift register. Accordingly, the shift register shifts the head of the next frame to a predetermined position, and the decoding unit captures the head of the next frame shifted to the predetermined position of the shift register.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which an address generator 1, a buffer 2, a controller 3,
It includes a shift register 4, a decoding unit 5, and a selector 6.

The address generator 1 increments the write address WA at the falling edge of the write signal 11 and increments the read address RA1 at the falling edge of the read signal 34. However, when the write signal 11 and the read signal 34 are input while the write address WA and the read address RA1 indicate the end of the buffer 2, the write address WA and the read address RA1 indicate the beginning of the buffer 2. To In addition, the address generation unit 1 performs the operation when the selector selection signal 35 output from the control unit 3 changes from “1” to “0” (when the selector 6 is switched from the control unit 3 to the address generation unit 1). ), And outputs the address next to the address output from the control unit 3 as a read address RA1.

The buffer 2 has a capacity for storing at least one frame of compressed data. Then, one word of input data 21 (for example, compressed data of MPEG audio or AC-3) input in synchronization with the write signal 11 is stored according to the write address WA, and output from the address generation unit 1 or the control unit 3. One word of compressed data is output according to the read address selected by the selector 6 among the read addresses RA1 and RA2 to be read.

The shift register 4 holds the compressed data output from the buffer 2 and shifts the held compressed data according to a shift signal 36. When the shift register 4 holds data in the first to i-th bits and receives j-bit data, the shift register 4 stores the data in the (i + 1) th to i-th bits. (I +
j) It has a function of holding the data in the first bit to the j-th bit when the data of the j-bit configuration is input when the data is held in the bit and when no data is held at all. .

When taking in the compressed data, the decoding unit 5 outputs a request signal 51 requesting to take in the compressed data, a request bit length 52 indicating a data length to be taken in, and a skip bit width 53. The skip bit width 53 is set to “0” when there is no error in the previously captured compressed data, and is set to the number of bits up to the head of the next frame when there is an error in the previously captured compressed data. Is done. In the present embodiment, it is assumed that the requested bit length 52 output by the decoding unit 5 is equal to or less than the bit width of the buffer 2.

The control unit 3 includes an arithmetic unit 31, a shift amount register 32, and a bit position register 33.
The shift amount register 32 stores a value indicating the shift amount of the shift register 4. The bit position register 33 stores the bit position of the tail part of the compressed data fetched by the decoding unit 5 (the bit number of the data stored at a certain address).

The control unit 3 sends a request signal 51,
When the required bit length 52 and the skip bit width 53 are added, if the skip bit width 53 is “0”, the read signal 34 is output as necessary, and then the data requested by the decoding unit 5 is shifted. The shift signal 36 which comes to the head of the register 4 is output. Then, when the requested data is arranged at the head of the shift register 4, a ready signal 37 is output to the decoding unit 5.

On the other hand, if the skip bit width 53 is not "0", first, using the arithmetic unit 31, the address of the buffer 2 where the head of the next frame is stored and the head of the next frame are stored. The shift amount for shifting the portion to the leading portion of the shift register 4 is obtained, and then the above address is output as the read address RA2, and the selector control signal 35 is set to "1" to supply the read address RA2 to the buffer 2. So that
Thereafter, a read signal 34 is output to cause the shift register 4 to hold the beginning of the next frame stored at the above address of the buffer 2, and furthermore, to supply a shift signal 36 corresponding to the shift amount to the shift register 4. Then, the head of the next frame is shifted to the head of the shift register 4. When the head of the next frame is aligned on the shift register 4, the ready signal 37 is sent to the decoding unit 5.
Is output.

The selector 6 selects and outputs the read address RA1 output from the address generator 1 when the selector control signal 35 is "0", and selects and outputs the read address RA1 when the selector control signal 35 is "1".
And selectively outputs the read address RA2 output from.

FIGS. 2 and 3 are flowcharts showing a processing example of the control unit 3, and FIG. 4 is a flowchart showing a processing example of the decoding unit 5. The operation of this embodiment will be described below with reference to the drawings.

As shown in the flowchart of FIG.
Synchronization detection processing (C1), header information extraction processing (C
2), a data fetching process (C3) is sequentially performed. At this time, in each of the processes C1 to C3, the decoding unit 5 requests a data request 51, a request bit length 52 indicating a bit length required for performing the process, and a skip bit width 53 (previous time). If there is no error in the captured data, "0" is output. Then, when the ready signal 37 is added from the control unit 3, the data of the required bit length is fetched from the shift register 4.

When the compressed data is fetched in the data fetching process C3, the decoding unit 5 detects an error using an error check code (C4), and when no error has occurred (C4 is NO), the decoding process (C4). Perform C5). If the data fetching process is not completed until the end of the frame (C6: NO), the data fetching process (C3) is performed again. If the data is fetched to the end of the frame (C6: YES), the process is repeated. The synchronization detection processing (C1) is performed.

On the other hand, if it is detected that an error has occurred in C4 (YES in C4), a skip bit width represented by the number of bits up to the head of the next frame is calculated (C7). ), And outputs a request signal 51, a request bit length 52, and a skip bit width 53 (C8). Here, the skip bit width is (the number of bits in one frame−
(The number of processed bits in the frame), and the number of bits in the frame can be obtained based on the header information. For example, MPEG
In the case of an audio compressed stream, the number of bits of the frame can be obtained based on the layer information and the bit rate index.

When the request signal 51 is output from the decoding unit 5, the control unit 3 determines whether the skip bit width 53 is "0" (A2, A3 in FIG. 2). Note that the control unit 3 has already performed processing for setting the values of the bit position register 33 and the shift amount register 32 to “N” and “0”, respectively, as initialization processing (A1). Here, N indicates the bit width of the buffer 2.

For example, if the skip bit width 53 is "0" (A3: YES), the control unit 3
Increases the value of the bit position register 33 by the required bit length 52 (A4). Thereafter, the control unit 3 checks whether or not the value of the bit position register 33 is larger than the bit width of the buffer 2 (A5). That is, it is checked whether or not the data requested by the decoding unit 5 is arranged on the shift register 4.

If the data requested by the decoding unit 5 is not aligned on the shift register 4 (A5 is Y
ES) outputs the read signal 34 (A6). Thereby, the buffer 2 outputs the data for one word stored in the address RA1 to the shift register 4, and the shift register 4 holds the data output from the buffer 2. At this time, the shift register 4 holds the data from the beginning.

When the read signal 34 is output, the control unit 3
Performs the operation of (value of bit position register 33 / bit width of buffer 2) and sets the remainder in bit position register 33 (A7).

When the process of A7 is completed, the control unit 3 outputs a shift signal 36 corresponding to the shift amount stored in the shift amount register 32, and the data stored in the shift register 4 is changed by the shift amount. Shift (A
8). The process of A8 is also performed when the result of the determination of A5 is NO.

By performing the processing of A8, the data requested by the decoding unit 5 is completed from the first bit to the m-th bit (m = required bit length) of the shift register 4, so that the control unit 3 The ready signal 37 is output (A9).
Thereby, the decoding unit 5 takes out the data from the shift register 4 and performs a predetermined process.

Thereafter, the control unit 3 sets the shift amount register 3
2, the request bit length 52 added from the decoding unit 5 this time is set (A10), and it is determined whether a skip operation (an operation of skipping to the beginning of the next frame) has been performed (A11). In this example, since the skip operation is not performed (A11 is NO), the control unit 3 waits for the input of the request signal 51 again (A2).

When the value of the skip bit width 53 from the decoding unit 5 is "0", the above processing is performed, but when the value of the skip bit width 53 is not "0" (A3 is NO).
Performs the processing shown in FIG.

If the skip bit width 53 from the decoding unit 5 is not “0”, that is, if the compressed data fetched by the decoding unit 5 has an error, the control unit 3 (The bit width of the buffer 2) (B1), and further, the operation of (the read address currently output by the address generation unit 1 + the quotient of the above operation result-1) is performed. Output as read address RA2 (B2). This read address RA2 indicates the address of the buffer 2 where the head of the next frame is stored.

Thereafter, the control unit 3 uses the arithmetic unit 31 ((the value of the bit position register 33 + the remainder of the operation performed with B1 + the number of bits of the data remaining in the shift register 4)).
Is performed, and the calculation result is set in the shift amount register 32 as a shift amount for shifting the head of the next frame to the head of the shift register 4 (B
3). Here, the number of bits of the data remaining in the shift register 4 can be obtained by performing an operation of (bit width of buffer 2-value of bit position register 33 + value of shift amount register 32).

When the process of B3 is completed, the control unit 3
Address RA2 output in step 2 and address generation unit 1
(B4). When the write address WA is more advanced (B4 is NO), the selector control signal 3
5 is set to "1" and the read signal 34 is output (B5, B6). On the other hand, when the read address RA2 is advanced (B4 is YES), the process of B5 and B6 is performed after waiting for the write address WA to catch up with the read address RA2.

When the selector control signal 35 becomes "1", the selector 6 selects the read address RA2 output from the control unit 3 instead of the read address RA1 from the address generation unit 1 which has been selected so far. In addition to the buffer 2, when the read signal 34 is added, the buffer 2 outputs data of one word stored at the address indicated by the read address RA2. The shift register 4 stores the data output from the buffer 2
It is stored in a form that connects immediately after the data already stored.

When the process of B6 is completed, the control unit 3 uses the arithmetic unit 31 to calculate (the value of the bit position register 33 + B1
(Remainder of the operation performed in (1) + required bit length 53), and the operation result is set in the bit position register 33 (B7). After that, the control unit 3 sets the bit position register 3
By comparing the value of 3 with the bit width of buffer 2,
All the data requested from the decoding unit 5 are stored in the shift register 4
It is determined whether or not they are aligned above (B8).

At B8, it is determined that the value of the bit position register 33 is larger than the bit width of the buffer 2, that is, the data requested by the decoding unit 5 is not aligned on the shift register 4. Case (B8 is YES)
Is the read signal 3 after the read address RA2 is incremented by 1.
4 is output (B9, B10). As a result, the data for one word stored in the read address RA2 is read from the buffer 2 and held in the shift register 4. Thereafter, the control unit 3 performs an operation of (value of the bit position register 33 ÷ bit width of the buffer 2) by using the arithmetic unit 31,
3 (B11).

When the process of B11 is completed, the control unit 3
A shift signal 36 corresponding to the shift amount indicated by the value of the shift amount register 32 is output to the shift register 4 so that the head of the data requested by the decoding unit 5 comes to the head of the shift register 4 ( B12). In addition, B12
Is also performed when the determination result of B8 is NO.

At a predetermined position of the shift register 4, a decoding unit 5
When the data requested by the control unit 3 is completed, the control unit 3 outputs a ready signal 37 to make the decoding unit 5 take in the data,
Further, the current required bit length 52 is stored in the shift amount register 33.
Are set (B13, B14).

Thereafter, the control section 3 determines whether or not a skip operation is being performed (FIG. 2, A11). In the case of this example, since the skip operation is performed (A11 is YE
S), the controller 3 sets the selector control signal 35 to "0", and causes the selector 6 to select the read address RA1 output from the address generator 1 (A12). Thereafter, the control unit 3 enters a waiting state for the request signal 51 (A
2).

The selector control signal 35 is also applied to the address generator 1. When the selector control signal 35 changes to "0", the address generator 1 outputs the latest read address output from the controller 3. An address obtained by adding +1 to RA2 is output as a read address RA1.

FIG. 5 is a time chart showing the operation of this embodiment. When “L” is output as the skip bit width 53 from the decoding unit 5 at time t1, the determination result of A3 in FIG. 2 becomes NO. As a result, the process of B5 in FIG. 3 is performed, and at time t2, the selector control signal 35 is set to "1". As a result, the read address “A” output from the control unit 3 is supplied to the buffer 2.
Thereafter, when the process of A12 in FIG. 2 is performed, the selector control signal 35 becomes “0” at time t3. As a result, the address generator 1 outputs an address “A + 1” obtained by adding +1 to the read address “A” output from the controller 3 as a read address RA1, and the selector 6 is output from the address generator 1. Read address "A +
1 "is supplied to the buffer 2.

[0046]

As described above, according to the present invention, when an error occurs in the compressed data, the error is skipped to the beginning of the frame next to the frame containing the compressed data in which the error has occurred. Can be made to contain no noise. In addition, the present invention realizes the above-described function using a buffer or a shift register that temporarily stores compressed data, so that error recovery can be performed using decoded data stored in a plurality of frame memories. The apparatus can be constructed more economically than in the case where it is performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a processing example of a control unit 3;

FIG. 3 is a flowchart illustrating a processing example of a control unit 3;

FIG. 4 is a flowchart showing a processing example of a decoding unit 5;

FIG. 5 is a time chart for explaining the operation of the embodiment.

FIG. 6 is a block diagram of a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Address generation part 2 ... Buffer 3 ... Control part 31 ... Calculator 32 ... Shift amount register 33 ... Bit position register 4 ... Shift register 5 ... Decoding part 6 ... Selector 110 ... Address generation part 120 ... Buffer 130 ... Control part 140 ... Shift register 150 ... Decoding unit 160 ... Parallel / serial converter

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-8-18984 (JP, A) JP-A-9-154142 (JP, A) JP-A-9-93589 (JP, A) JP-A-7- 75110 (JP, A) JP-A-7-38888 (JP, A) JP-A-6-311052 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 7/30 H04N 7 / 32

Claims (5)

(57) [Claims] 1. A data sequence control device comprising: a buffer for storing at least one frame of compressed data; and an address generator for generating a write address and a read address for the buffer in accordance with a write signal and a read signal. A shift register that holds the compressed data read from the buffer and shifts the data in accordance with a shift signal; and a request bit length that indicates the length of the compressed data to be captured when the compressed data is captured. If an error is detected in the compressed data for the bit length, a decoding unit that calculates and outputs a skip bit width represented by the number of bits up to the beginning of the next frame, and outputs the required bit length from the decoding unit In this case, the required bit length and the number of bits of the compressed data not captured by the shift register And outputs to the shift register a shift signal for performing a shift corresponding to the required bit length previously output from the decoding unit, and skips from the decoding unit. When the bit width is output, a shift for shifting the head of the next frame to a predetermined position on the shift register is performed while obtaining and outputting the address of the buffer in which the head of the next frame is stored. Find the quantity,
A control unit that outputs a shift signal corresponding to the shift amount to the shift register; and reads one of a read address output from the address generation unit and an address output from the control unit to the buffer. A data string control device, comprising: a selector serving as an address. 2. The control unit according to claim 1, wherein the control unit divides the skip bit width by a bit width of the buffer, and adds a quotient of the quotient to a read address output by the address generation unit to obtain a start of the next frame. 2. The data string control device according to claim 1, further comprising a configuration for obtaining an address of said buffer in which a part is stored. 3. The control unit determines a shift amount based on a last bit position of a part where an error is detected by the decoding unit, a remainder of the division, and a number of bits of data remaining in the shift register. 3. The data sequence control device according to claim 2, further comprising a configuration for obtaining the data sequence. 4. The selector, when an address is output from the control unit, sets the address as a read address for the buffer, and when no address is output from the buffer, the address is output from the address generation unit. 4. The data string control device according to claim 3, wherein the data string control device has a configuration in which a read address is used as a read address for the buffer. 5. The data stream control device according to claim 4, wherein the compressed data is MPEG audio or AC-3 compressed data.