JP3326015B2 - Thin film semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film integrated circuit formed on an insulating surface and a circuit element used therefor, for example,
The present invention relates to a structure of a thin film transistor (TFT). In the present invention, the insulating surface other than the insulator surface,
It also means an insulating layer provided on the surface of a semiconductor or metal.
That is, the integrated circuit and the thin film transistor manufactured by the present invention are formed over an insulating substrate such as glass or an insulator formed over a semiconductor substrate such as single crystal silicon.

[0002]

2. Description of the Related Art In a TFT, after a substantially intrinsic thin film semiconductor region (active layer) is formed in an island shape on an insulating surface, an insulating film is formed as a gate insulating film by a CVD method or a sputtering method. Obtained by forming a gate electrode thereon. The source / drain is doped with N-type or P-type impurities. That is, the TFT has a structure having an N-type or P-type source / drain and a substantially intrinsic conductivity type channel formation region. In recent years, it has been attempted to use a crystalline semiconductor instead of an amorphous semiconductor as the semiconductor of the active layer because of the need to increase the electric field mobility of the TFT.

[0003]

The biggest problem with TFTs using such a crystalline semiconductor is that the leakage current (off current) is large. That is, when no voltage is applied to the gate electrode, or when a reverse voltage is applied, no channel is formed and no current should flow. However, actually, a current higher than the leakage current normally observed in a single crystal semiconductor was observed. Such a large leak current is a problem particularly in applications requiring dynamic operation. Further, it is not preferable in applications requiring a static operation, because power consumption is increased.

In an active matrix circuit such as a liquid crystal display, which is expected as a large use of the TFT, the TFT operates as a switching transistor of a pixel provided in a matrix. In this case, a pixel electrode and an auxiliary capacitor thereof are used. It was required that the charge accumulated in the (holding capacitor) did not leak, but if the leak current was large, the charge could not be held for a sufficient time. The present invention provides a TF using a crystalline semiconductor for an active layer.
In T, an object is to reduce a leak current.

[0005]

The basic configuration and concept of the present invention will be described with reference to FIG. FIG. 1 shows the TFT viewed from above. The thin film semiconductor region 1 is a substantially intrinsic crystalline semiconductor. A feature of the present invention is that an impurity region 2 having a conductivity type opposite to that of a source / drain is provided across a portion where a channel formation region is provided later. The presence of the impurity region 2 can reduce the leak current. (FIG. 1A) The impurity region 2 may be formed either before or after the semiconductor film is etched to form the semiconductor region 1. In the case where the crystallinity is reduced by the introduction of the impurity (accelerated impurity ions). (For example, an ion implantation method or an ion doping method), it is desired to perform a process for improving crystallinity in a step before forming a gate electrode.

That is, when a crystalline semiconductor is obtained by laser light irradiation or thermal annealing, it is preferable to perform a doping step for forming an impurity region before the laser light irradiation or thermal annealing step. Further, in the case where laser light irradiation is performed after thermal annealing, even if doping is performed after thermal annealing, crystallinity can be improved by subsequent laser light irradiation. Of course, in the subsequent steps, if there is a step such as thermal annealing or laser light irradiation from the back surface, the crystallinity of the impurity region can be improved at that time.

After that, a gate insulating film and a gate electrode 3 are formed. (FIG. 1B) Then, using the gate electrode as a mask, an impurity is introduced in a self-aligned manner to form a source 4 and a drain 5. (FIG. 1C) As described above, the basic structure of the TFT of the present invention is obtained. FIG. 1 shows a state in which the gate electrode is stripped at that time.
It is shown in (D). (FIG. 1D) Cross section aa ′ perpendicular to the gate electrode of the TFT shown in FIG.
FIG. 2 shows the state of each step. The numbers correspond to those in FIG.

In the examples of FIGS. 1 and 2, only one impurity region 2 of the conductivity type opposite to the source / drain is provided in the channel forming region, but two or more impurity regions may be provided. When two or more such impurity regions are provided, variations as shown in FIGS. 3 and 4 are further possible. FIG. 3 is a top view (corresponding to FIG. 1D) of the TFT from which the gate electrode is removed, and FIG. 4 is a sectional view taken along the line aa ′ of FIG. In this example, an impurity region 16 of the same conductivity type as the source / drain is provided in a channel formation region between the source 11 and the drain 12.
Further, impurity regions 14 and 18 of the conductivity type opposite to the source / drain are provided on both sides thereof. Then, the impurity region 1
Between 4, 16 and 18, the substantially intrinsic regions 13, 1
5, 17, and 19 are provided.

[0009]

The present inventor has found that most of the leak current is generated at the edge portion of the thin film semiconductor region. In order to reduce the leakage current, it is considered effective to reduce the channel width. However, as a result of consideration by the present inventors, even if the channel width is reduced, the leakage current is reduced in proportion to the reduction. No, in particular, a channel width of 3 μm
And 8 μm (each having a channel length of 8 μm), no significant difference was found in the leakage current. This means that the entire channel is not involved in the leakage current.

The present inventor has presumed that the edge of the channel formation region is easily damaged in the etching step, and a channel may be formed unintentionally. In addition, if the step coverage of the gate insulating film is insufficient, a defect is likely to occur, and some charge may be trapped therein to generate an unintentional channel.

In the present invention, impurity regions (2 in FIG. 1 or 14 and 18 in FIG. 3) cross the channel forming region.
Is effective in making such an unstable edge portion nonconductive. In FIG. 1, if the source / drain is N-type, the impurity region 2 becomes P-type. The NIP is formed in the channel forming region including the edge region.
An IN junction is formed, which is effective in suppressing a leak current. Similarly, in the case of FIG. 3, NIPINIPI
An N junction is formed. The same is true even if the source / drain is a P-type. Here, a substantially intrinsic region (I-type region) is provided between the P-type region and the N-type region, and the PIN or N-type region is provided.
It is important that the junction is an IP junction.

[0012] In a polycrystalline or other non-single-crystal crystalline semiconductor, an ideal heterogeneous junction cannot be formed as in a single-crystal semiconductor, and many defects and levels due to the defect occur at the junction interface. In a non-single-crystal PN junction, a large current flows even in the reverse direction. The impurity region (impurity region 2 in FIG. 1 or impurity regions 14 and 1 in FIG.
It is preferable that the impurity concentration of 8) is as low as possible. Referring to FIG. 1 as an example, when the impurity region has the same impurity concentration as the source / drain, the N ⁺ IP ⁺ IN ⁺ junction or the P ^+
+ IN ⁺ IP ⁺ junction is formed. In this case, N ⁺ , P
⁺ Means that an N-type or P-type impurity having a concentration of about 10 ²⁰ atoms / cm ³ or more is contained. As a result, even if a voltage is applied to the gate electrode, the conductivity type of the impurity region 2 cannot be inverted, and
Does not work as .

Even if the impurity concentration of the impurity region 2 is low, it is not easy to invert the impurity concentration.
Is provided, the ON current decreases, and the absolute value of the threshold increases. However, since the off-state current also decreases, it is required to determine whether or not to carry out the present invention according to required characteristics. When the present invention is implemented with the impurity concentration of the impurity region 2 reduced, the N ⁺ IP ^- IN ⁺ junction (or NIP ^- IN junction) or P ⁺ IN ^- IP
⁺ Junction (or PIN ^- IP junction) is obtained. In this case, N ⁻ and P ⁻ mean that an N-type or P-type impurity having a concentration of about 10 ¹⁸ atoms / cm ² or less is contained. In the present invention, the impurity concentration is required to be 1 × 10 ¹⁷ or more in order to suppress the leak current in the edge portion. On the other hand, when the impurity is doped at a high concentration, the on-state characteristics of the TFT deteriorate as described above. Therefore, the impurity concentration is desirably 1 × 10 ¹⁹ atoms / cm ² or less.

A further effect can be obtained by applying the present invention to a TFT having a structure having a low concentration drain (LDD). A normal LDD type TFT has a junction structure of N ⁺ N ^- IN ^- N ⁺ or P ⁺ P ^- IP ^- P ⁺ , but when the present invention is applied to this, the N-channel type the N ⁺ N ^- IP ^-
IN ^- N ⁺ junction structure In the case of the P-channel type, a junction structure of P ⁺ P ^- IN ^- IP ^- P ⁺ is obtained. As described above, in the present invention, as a cause of the leak current, the channel formed unintentionally in the edge portion is removed, so that the leak current is significantly reduced. In the present invention, the main factors that determine the leak current are:
Width of channel formation region (channel width) x, impurity region 2
, And the distance z between the source or drain and the impurity region 2. These may be determined in consideration of the design rule to be used and the magnitude of the allowable leak current. Leakage current is approximately proportional to x and inversely proportional to y.

The value of z affects the breakdown voltage other than the leakage current. The value of z is a stable PIN or N as described above.
A value sufficient to form an IP junction is required, and depends on the drain voltage.
If the voltage is 10 μm or more, it is desirable that the thickness be 1.5 μm or more. In particular, on the drain side, if the distance between the drain region and the impurity region is 3 μm or less, a pinch-off point is applied to the impurity region, and the threshold voltage of the TFT increases. In the present invention, as shown in FIG. 3, when a plurality of impurity regions of the conductivity type opposite to the source / drain are formed, a plurality of PIN junctions are formed, and at least one of the junctions acts as a reverse diode with respect to the drain voltage. In addition, there is a special contribution to the reduction of off-state current.

In the present invention, it is necessary to form an impurity region before forming a gate electrode. However, it is effective to perform this step simultaneously with another impurity region forming step. For example, in an active matrix circuit, a conductive region is provided in a thin film semiconductor layer, a wiring in the same layer as a gate electrode is formed thereon, and a wiring (hereinafter, referred to as a capacitor wiring) and a conductive region therebelow. In some cases, a capacitor (capacitor) using a gate insulating film as a dielectric is formed. In this case, since the conductive region needs to be formed by doping impurities below the capacitor wiring, the formation of the conductive region needs to be performed prior to the formation of the gate electrode (capacitor wiring). In the present invention, since the impurity region is formed in the channel formation region before the formation of the gate electrode, it is effective to simultaneously form the impurity region and the conductive region.

FIG. 5 and FIG. 6 show process drawings at that time. FIG. 5 is a drawing viewed from above, and FIG. 6 is a sectional view thereof. In this case, the thin film semiconductor region is composed of two parts as shown in FIG. The left side of the figure is a region where a TFT is provided, and the right side is a region where a capacitor is provided. FIG. 5 (A)
6 (A) to 6 (F) are cross-sectional views taken along the line aa ′ of FIG. In the region where the gate electrode of the TFT is formed, an impurity region 22 is provided across the channel formation region as in FIG. In addition, the capacitor region and a part of the drain of the TFT region are simultaneously doped with impurities, so that the conductive region 23 is formed. The other regions are substantially intrinsic regions 21. (FIG. 5 (A), FIG. 6 (A))

Next, a gate insulating film, a gate electrode 24 and a capacitor wiring 25 are formed. And in the TFT area,
A mask 26 for introducing impurities for forming a source / drain is formed. This is because the conductivity type of the conductive region 23 is opposite to the conductivity type of the source / drain, so that the conductivity type of the conductive region 23 is not inverted when the source / drain is formed. (FIGS. 5B and 6B) Next, a source 27 and a drain 28 are formed by performing impurity doping. Here, the conductivity types of the source / drain and the conductive region 23 are opposite to each other. (FIG. 5 (C), FIG. 6 (C))

Next, activation of impurities (recovery of crystallinity) is performed by an appropriate method to form an interlayer insulator. Then, contact holes 2 are formed in the source / drain of the TFT.
9 and 30 are formed. At this time, in the drain 28, a contact hole 30 is provided at a boundary between the contact hole and the conductive region 23. (FIG. 5D, FIG. 6D) Next, a metal film is deposited on the entire surface. At this time, if the semiconductor active layer is made of silicon, the metal film may be a single-layer film of titanium, platinum, tungsten, molybdenum, or the like, which is easily combined with silicon to obtain silicide (silicide). It is preferable to form a multilayer film on which another metal film is stacked. After forming such a metal film, if annealing is performed at an appropriate temperature, the metal reacts with silicon to form silicide. The figure shows how a multilayer film of titanium and aluminum is deposited. Titanium generates titanium silicide at its interface by annealing at a temperature of 350 ° C. or higher. (Fig. 6 (D ')

Next, the metal film is etched to form a source electrode / wiring 22. This is connected to the source 27 by the contact hole 29, and a silicide generated by the above-described annealing is formed therebetween.
On the other hand, the silicide 32 formed in the contact hole 30 can remain even when the entire metal film is removed as shown on the drain side in the drawing. This can be easily implemented by utilizing the difference in the etching rate between the metal film and the silicide. (FIG. 5E, FIG. 6E) When forming a liquid crystal display, a second interlayer insulator is formed on a metal wiring like a source wiring / electrode 31, and a contact hole 30 (ie, , Silicide 3
A pixel electrode 33 may be formed by forming a contact hole in a region including 2). (FIG. 5 (F), FIG. 6 (F))

In FIGS. 5 and 6, since the conductivity type of the conductive region 23 and the source / drain are opposite to each other, it is necessary to pay attention to the amount of impurities to be doped. If the impurity concentration in the conductive region 23 is reduced, the resistance in the region increases, so care must be taken when designing the circuit. In the above description, the capacitance is provided on the drain 26 side for convenience, but it is needless to say that the capacitance can be provided on the source side.

[0022]

【Example】

Embodiment 1 FIG. 7 shows a cross-sectional view of a TFT of this embodiment in which the present invention is applied to an LDD type TFT. The sectional view shown in FIG. 7 corresponds to the section taken along the line aa ′ in FIG. In this embodiment, a P-channel type is used. The fabrication process is performed before the formation of the island-shaped thin-film silicon region.
The structure is the same as that of the conventional LDD type TFT except that an N ⁻ type impurity region 42 is formed across the region 1. Hereinafter, the manufacturing method will be briefly described. A substantially intrinsic amorphous silicon film was formed on a quartz substrate. The thickness of the amorphous silicon film is 300 to 1200 Å, for example, 800 Å.
And And 500-620 degreeC, for example, 600 degreeC
By heat annealing for 48 hours.
When a trace amount of an element that promotes crystallization such as nickel is added, the crystallization temperature and time can be reduced or shortened.

Thereafter, an impurity region 42 is formed. The arrangement is similar to that of impurity region 2 in FIG. , The impurity region 42 contains phosphorus at 1 × 10 ¹² to 1 × 10 ¹⁴ atoms / cm.
² , preferably 3 × 10 ^{12 to} 3 × 10 ¹³ atoms / c
It was formed by ion doping at a dose of m ² , for example, 1 × 10 ¹³ atoms / cm ² . At the time of forming the impurity region, the silicon film was patterned with a photoresist, and the substantially exposed silicon film was irradiated with ions using the photoresist as a mask. For this reason, the acceleration voltage was set to 5 to 20 kV, for example, 10 kV. Next, an island region was formed by etching the silicon film, and a gate insulating film 43 was formed of silicon oxide having a thickness of 1200 ° and a gate electrode 44 was formed of polycrystalline silicon doped with phosphorus. The doping amount of phosphorus into polycrystalline silicon is 1 × 10 ^{20 to} 5 × 10 ²¹ atoms / cm.
^{It was set to 3} .

Then, using the gate electrode 44 as a mask,
Boron is 1 × 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ² , for example,
P ⁻ -type regions 48 and 49 were formed by ion doping at a dose of 1 × 10 ¹⁴ atoms / cm ² . Next, a sidewall 45 is formed by a known technique, and using this as a mask, boron is ion-doped at a dose of 2 × 10 ^{14 to} 5 × 10 ¹⁵ atoms / cm ² , for example, 1 × 10 ¹⁵ atoms / cm ^2. By doing so, the P ⁺ type region 46,
47 were formed. In each case, the acceleration voltage was 50 to 90 kV, for example, 65 kV. By the above two-stage doping, a source / drain having an LDD structure was formed. Then, at 600 ° C, 2
By the time thermal annealing, the crystallinity of the source / drain regions reduced by the impurity doping was recovered. At this time, the crystallinity of the impurity region 42 was recovered at the same time.

[Embodiment 2] FIG. 8 is a cross-sectional view of a TFT of this embodiment in which the present invention is applied to an offset gate type TFT using anodic oxidation. The sectional view shown in FIG. 8 corresponds to the section taken along line aa ′ of FIG. In this embodiment, a P-channel type is used. The following briefly describes the manufacturing process. As a substrate, Corning 7059 formed using a silicon oxide film having a thickness of 2000 ° as a base was used. First, the thickness 50
A 0 ° amorphous silicon film was formed. Then, the N ⁻ -type impurity region 52 is later crossed over the channel formation region.
Was formed. The arrangement was the same as that of the impurity region 2 in FIG. The impurity region 52 is formed by ion doping with phosphorus at a dose of 1 × 10 ¹² to 1 × 10 ¹⁴ atoms / cm ² , for example, 2 × 10 ¹³ atoms / cm ² .

Thereafter, the silicon film was crystallized by laser light irradiation. As a laser, a KrF excimer laser (wavelength 248 nm, pulse width 20 ns)
ec) but other lasers, such as XeF
An excimer laser (wavelength 353 nm), a XeCl excimer laser (wavelength 308 nm), an ArF excimer laser (wavelength 193 nm), or the like may be used. The energy density of the laser is 250-450 mJ / cm ² ,
For example, 350 mJ / cm ² and ² to 10
A shot, for example, 10 shots was irradiated. During laser irradiation, the substrate may be heated to about 200 to 450 ° C.
It should be noted that the optimal laser energy density changes when the substrate is heated. The silicon film in this state was intrinsic except for the impurity region 52.

Next, patterning and etching of the silicon region were performed to form an island-shaped silicon region. Next, a gate insulating film 53 (silicon oxide) and a gate electrode 54 of aluminum (thickness 4000 to 8000 Å, for example, 6000 Å) were formed. When scandium (Sc) was mixed in the aluminum of the gate electrode with 0.1 to 0.5% by weight, a good quality anodic oxide film was obtained in the anodic oxidation step. Further, the surface of the aluminum wiring was anodized to form an oxide film 55 on the surface. For the anodization, a solution having a pH of about 7 by neutralizing a 1 to 5% ethylene glycol tartrate solution with ammonia was used. By gradually increasing the applied voltage and increasing the voltage to 150 V, the thickness of the obtained oxide layer becomes about 20
It was 00 $. The anodic oxide obtained by the above method is dense and is called barrier type anodic oxide.

Next, boron ions were implanted into the silicon region using the gate electrode 54 and the anodic oxide film 55 as a mask by an ion doping method. The accelerating voltage is 50
-80 kV, for example, 65 kV. Dose amount is 1 × 1
0 ^{14 to} 5 × 10 ¹⁵ atoms / cm ² , for example, 5 × 10 ¹⁵ atoms / cm ² . Thus, the P-type regions 56, 5
7 was formed.

Thereafter, the crystallinity of the P-type region (source / drain) was improved by laser light irradiation.
KrF excimer laser (wavelength 24)
8 nm and a pulse width of 20 nsec), but other lasers such as a XeF excimer laser (wavelength 3
XeCl excimer laser (wavelength 308)
nm), ArF excimer laser (wavelength 193 nm)
Etc. may be used. The energy density of the laser is 20
The irradiation was performed at 0 to 350 mJ / cm ² , for example, 250 mJ / cm ^2, and irradiation was performed for 2 to 10 shots, for example, 2 shots at one location. During laser irradiation, the substrate is kept at 200-450 ° C
It may be heated to a degree. It should be noted that the optimal laser energy density changes when the substrate is heated.

In this embodiment, unlike the first embodiment, the N-type impurity region below the gate electrode is crystallized from the beginning. In the present embodiment, the gate electrode 54
Distance x between the source 56 and the drain 57 (about 2000
Å) Offset gate type that is only separated. x is roughly the thickness of the anodic oxide coating 55. T of this embodiment
The channel forming region (including the offset region) of the FT is
1, the channel width is 3 μm, the width y of the impurity region 52 is 8 μm, and the source / drain and the impurity region 5 are formed.
The interval z of 2 was 3 μm. The channel length (the distance between the source and the drain, including the offset region) is 1
It was 4 μm.

[Embodiment 3] FIG. 9 is a sectional view of a TFT according to the present embodiment in which the present invention is applied to an offset gate type TFT using a side anodic oxidation process. The cross-sectional view shown in FIG. 9 corresponds to the cross section taken along the line aa ′ of FIG. 1 and shows main steps. In this embodiment, a P-channel type is used. The following briefly describes the manufacturing process. 200 thickness for substrate
Corning 7059 formed with 0 ° silicon oxide film as a base
Was used. First, an amorphous silicon film having a thickness of 800 ° was formed and crystallized by thermal annealing. Then, an N ⁻ -type impurity region 62 was formed so as to cross the channel formation region later. The arrangement was the same as that of the impurity region 2 in FIG. The impurity region 62 is made of phosphorous of 1 × 10 ¹² to
1 × 10 ¹⁴ atoms / cm ² , for example, 5 × 10 ¹² atoms / c
It was formed by ion doping with a dose of m ² .

Thereafter, the crystallinity of the silicon film was further improved by laser light irradiation. In this step, the phosphorus that was previously implanted by the ion doping method was also activated. As a laser, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was used.
Laser energy density is 200-400mJ / c
m ² , for example, 300 mJ / cm ^2, and 2
Irradiation was performed for 10 to 10 shots, for example, 10 shots. During laser irradiation, the substrate may be heated to about 200 to 450 ° C.

Next, the silicon region was etched to form an island-shaped silicon region 61. Next, a gate insulating film 63 (silicon oxide) and an aluminum film (thickness 400)
0 to 8000 °, for example, 6000 °). Scandium (Sc) 0.1 to aluminum
0.5% by weight was incorporated. Further, the aluminum film was subjected to anodic oxidation treatment as in Example 2, and a thin anodic oxide film was formed on the surface. In this anodic oxidation step, the applied voltage was up to 10 V, so that the obtained anodic oxide coating was 100 to 150 °. Next, the gate electrode 64 was formed by etching the aluminum film by a known photolithography process. The photoresist mask 65 used in the photolithography process was left thereafter.

Then, the side surface of the aluminum wiring was anodized to form an oxide film 66. The anodic oxidation was performed in an acidic solution different from Example 2. For example, the reaction is performed using a 3 to 20% aqueous solution of citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid, or the like.
A constant current of 30 V may be applied to the gate electrode. In this example, the voltage was set to 10 V in an oxalic acid solution (30 ° C.), and anodization was performed for 20 to 180 minutes. The thickness of the anodic oxide was proportional to the anodic oxidation time. Also, the rate of anodization was greatly affected by temperature. In this embodiment, the anodic oxide 66 having a thickness of 3000 to 3 μm, for example, 1.2 μm, is formed. The anodic oxide thus obtained was characterized by being porous. Further, it was also characterized in that a thick oxide film was obtained at a low voltage. Also,
In this embodiment, since the mask 65 is present on the upper surface of the gate electrode, the anodic oxidation selectively proceeds only on the side surface.
(FIG. 9A)

After the mask 65 was removed, boron ions were implanted into the silicon region by using the gate electrode 64 and the anodic oxide film 66 as a mask. The acceleration voltage was 50 to 80 kV, for example, 65 kV. The dose is 1 × 10 ^{14 to} 5 × 10 ¹⁵ atoms / cm ² ,
For example, it was 1 × 10 ¹⁵ atoms / cm ² . Thus, P-type regions 67 and 68 were formed.

Thereafter, the P-type region (source / drain) was activated by laser beam irradiation in the same manner as in Example 2. As a laser, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was used.
In the present embodiment, an offset gate type in which the distance between the gate electrode 64 and the source 67 and the drain 68 is x (about 1.2 μm) is provided. It was extremely large compared to the value of x in Example 1. (FIG. 9 (B))

Embodiment 4 FIG. 10 is a sectional view of a TFT of this embodiment in which the present invention is applied to an offset gate type TFT using a side anodic oxidation process. The cross-sectional view shown in FIG. 10 corresponds to the cross section taken along the line aa ′ of FIG. 1 and shows main steps. In this embodiment, a P-channel type is used. The following briefly describes the manufacturing process. As in Example 3, an island-shaped crystalline silicon region 71 was formed on the insulating surface.
In the island-shaped silicon region 71, an N ⁻ -type impurity region 72 was formed across the channel formation region. Fig. 1
Of impurity region 2. The impurity region 72 is 1 ×
10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³ , for example, 5 × 10 ¹⁷
It contains phosphorus as an impurity at a concentration of atoms / cm ³ .

Next, a gate insulating film (silicon oxide) and a gate electrode 74 (thickness 5000 mm) made of aluminum whose side surfaces were selectively anodized were formed. The width of the anodic oxide 75 on the side was 8000 °. This state is shown in FIG.
(A). Then, the gate insulating film was etched by a dry etching method. At this time, aluminum and its anodic oxide were not etched, and the gate insulating film 73 remained only under the gate electrode 74 and the anodic oxide 74. (FIG. 10A)

After the anodic oxide 75 was selectively etched, boron ions were implanted into the silicon region by ion doping using the gate electrode 74 and the gate insulating film 73 as a mask. Acceleration voltage is 50-80k
V, for example, 65 kV. Dose amount is 1 × 10 ¹³ -5
× 10 ¹⁴ atoms / cm ² , for example, 1 × 10 ¹³ atoms / cm
^{And 2} . Thus, P ⁻ type regions 76 and 77 were formed. (FIG. 10B)

Further, the accelerating voltage is continuously set to 5 to 20 k.
Boron ions were implanted at V, for example, 10 kV. In this step, since the acceleration voltage is low, boron is not implanted into the portion covered by the gate insulating film 73, and mainly,
It was implanted into the region without the gate insulating film. The dose at this time is larger than that in the previous case, that is, 1 × 10 ^{14 to} 5 × 10 ^15.
Atoms / cm ² , for example, 5 × 10 ¹⁴ atoms / cm ² . As a result, P ⁺ regions 78 and 79 were formed. Further, of the P ⁻ -type regions 76 and 77, the regions below the gate insulating film remained as LDDs 80 and 81. (FIG. 10 (C))

Thereafter, similarly to Example 2, the P ^- type region and the P ⁺ type region (source / drain) were activated by laser beam irradiation. As a laser, a KrF excimer laser (wavelength 248 nm, pulse width 20 ns)
ec) was used. As described above, an LDD type TFT was manufactured. After the porous anodic oxide film is obtained in the above steps, the anodic oxidation described in Example 2 is performed. As shown in FIG.
4 is coated with a barrier-type anodic oxide 82, which is effective in protecting the aluminum gate electrode.
(FIG. 10 (D))

Embodiment 5 FIGS. 11 and 12 show this embodiment. This embodiment includes an active matrix circuit,
The present invention is applied to a monolithic active matrix circuit in which a peripheral circuit for driving the same is formed on the same substrate. As shown in FIG. 12, a monolithic type active matrix circuit has a gate driver and a source driver attached to the active matrix circuit, and these driver circuits are called peripheral circuits, and are generally an N-channel TFT and a P-channel TFT. Are configured by a complementary circuit. for that reason,
Also in FIG. 11, the peripheral circuit is represented by a complementary inverter.

On the other hand, an active matrix circuit (pixel)
In, the TFT is either P-type or N-type. In this embodiment, a P-channel TFT is used. The unit pixel in the active matrix circuit has a TFT
And a liquid crystal element, and a storage capacitor (also referred to as an auxiliary capacitor) for supplementing the capacity of the liquid crystal element. In this embodiment, as shown in FIG. 12, one electrode of the storage capacitor is connected to the gate wiring of the next row. FIG. 11 is a cross-sectional view corresponding to the cross section taken along the line aa ′ of FIG. 5 for the TFTs of the active matrix circuit and the associated circuits. In a monolithic active matrix circuit, TFTs in pixels require lower leakage current than high-speed operation, and TFTs in peripheral circuits require higher-speed operation than low leakage current. In order to solve this contradiction, it is effective to apply the present invention only to the transistor of the pixel and not to the peripheral circuit as in the present embodiment.

Hereinafter, the manufacturing process will be described. First,
On a substrate (Corning 7059), a 2000-nm-thick silicon oxide or silicon nitride film or a base film (not shown) of a multilayer film thereof was formed by a plasma CVD method or a sputtering method. Further, an amorphous silicon film having a thickness of 300 to 1500 °, for example, 500 ° was deposited by a plasma CVD method. Then, it was crystallized by thermal annealing in a reducing atmosphere. In the crystallization step, strong light such as a laser may be used. Further, in the pixel region, N ⁻ -type regions 104 and 105 were formed by an ion doping method. N ⁻ -type region 104 corresponds to impurity region 22 in FIG. 5, and N ⁻ -type region 105 corresponds to conductive region 23 in FIG. 5, respectively. These N ^-
In the mold region, 1 × 10 ¹² to 1 × 10 ¹⁴ atoms / c of phosphorus
m ² , for example, at a dose of 3 × 10 ¹³ atoms / cm ² .

Thereafter, the crystallinity of the silicon film was further improved by laser light irradiation. In this step, the crystallinity of the N ⁻ -type regions 104 and 105 into which phosphorus was implanted earlier was also improved. As a laser, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was used. The crystalline silicon film thus obtained is etched to form island-shaped silicon regions 101 (for a peripheral circuit N-channel TFT) and 102 (a peripheral circuit P-channel TFT).
FT) and 103 (for pixel TFT). (Figure 1
1 (A))

Next, the sputtering method or plasma C
According to the VD method, the thickness is 500 to 1500 °, for example, 100
A 0 ° silicon oxide film 106 was deposited, and subsequently an aluminum film (containing 0.1 to 0.5% by weight of scandium) having a thickness of 4000 to 8000 °, for example, 6000 ° was deposited by a sputtering method. Then, the aluminum film is patterned to form the gate electrodes 107, 108,
109 and a capacitor wiring 110 were formed. Silicon oxide film 106
Functions as a gate insulating film. (FIG. 11B)

Further, in the same manner as in Examples 3 and 4, the side surfaces of the gate electrode / capacitance wiring were anodized to form porous anodic oxide layers 111, 112, 113 and 114. Further, a gate electrode is formed by the method of the second embodiment.
A barrier type anodic oxide coating 115 was formed around the capacitor wiring. (FIG. 11C) Next, only the region for forming the P-channel TFT was exposed, and the other region was covered with a photoresist mask 116, and the porous anodic oxides 112 and 113 were etched. Further, boron ions were implanted. The acceleration voltage was 50 to 80 kV, for example, 65 kV. The dose is 1 × 10 ^{14 to} 5 × 10 ¹⁵ atoms / cm ² , for example, 5
× 10 ¹⁴ atoms / cm ² . Thus, P-type regions (source / drain) 117 and 118 were formed.
(FIG. 11D)

Next, the photoresist mask 116 is removed, and the silicon oxide film 10 is removed by dry etching.
6 was etched. As a result, the silicon oxide film 106 is removed except for the gate electrode / capacitance wiring and the surrounding portion covered with the anodic oxide, and the gate insulating films 119, 120, 121, and 122 remain in the above-mentioned portions. did. (FIG. 11E) Further, the porous anodic oxides 111 and 114 were etched. Then, only the region where the N-channel TFT is to be formed is exposed, and the other regions are exposed to a photoresist mask 1.
23, and phosphorus ions were implanted. The accelerating voltage is 6
0 to 110 kV, for example, 80 kV. The dose is 1
× 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ² , for example, 5 × 10
¹³ atoms / cm ² . Subsequently, the accelerating voltage, 5-20
kV, for example, 10 kV, dose amount, 1 × 10 ^{14 to} 5 × 1
The doping was performed under the conditions of 0 ¹⁵ atoms / cm ² , for example, 1 × 10 ¹⁵ atoms / cm ² . As a result, similarly to the fourth embodiment, a region 124 into which a high concentration impurity is implanted and a region 125 into which a low concentration impurity is implanted are formed.
Type TFT was obtained. (FIG. 11 (F))

Thereafter, a silicon oxide film 126 having a thickness of 4000 to 8000 Å, for example, 5000 Å was formed on the entire surface by a plasma CVD method, and a contact hole was formed in the silicon oxide film 126. Then, a titanium film having a thickness of 500 ° and a thickness of 400
A multilayer film of a 0 ° aluminum film (containing 1% silicon) is deposited, and in this state, 300 to 450 ° C., for example, 3 ° C.
Annealed at 50 ° C. As a result, the titanium film and silicon reacted at the contact portion, and titanium silicide was formed. Then, the multilayer film is etched to form a TFT wiring 12.
8, 129, 130 and 131 were formed. However, in the pixel TFT, although the multilayer film is removed from the contact hole 127 where the pixel electrode is formed,
Silicide 132 remained. (FIG. 11 (G))

Next, the thickness 1 is formed by the plasma CVD method.
A silicon nitride film 133 of 500 to 5000 〜, for example, 3000 Å was formed. Then, first, the contact hole 12
A contact hole was formed again in the vicinity of the formation of No. 7. Thereafter, an ITO (indium tin oxide) film was formed to a thickness of 500 ° by a sputtering method, and this was etched to form a pixel electrode 134. As described above, a monolithic active matrix circuit was manufactured. (FIG. 11 (G))

[0051]

According to the present invention, it has become possible to reduce the leak current of a thin film semiconductor device, to enhance its reliability, and to obtain the maximum characteristics. The thin film semiconductor device of the present invention is particularly preferable as a transistor for controlling a pixel in an active matrix circuit of a liquid crystal display because it has a low leak current between a gate and a drain and between a gate and a source and can endure a high gate voltage. .

In the first to fourth embodiments, a description has been given mainly of a P-channel type TFT as an example.
Needless to say, the present invention can also be implemented in the case of a phase catch type circuit in which an N-channel type and a P-channel type are mixed on the same substrate. The present invention has been described centering on TFTs. However, it goes without saying that the present invention can be applied to other circuit elements, for example, a thin film integrated circuit having a plurality of gate electrodes in one island-shaped semiconductor region, a stacked gate type TFT, and a diode. As described above, the present invention is an industrially useful invention.

[Brief description of the drawings]

FIG. 1 shows a manufacturing process of a TFT of the present invention. (Top view)

FIG. 2 shows a manufacturing process of the TFT of the present invention. (Cross section)

FIG. 3 shows a configuration of a TFT of the present invention. (Top view)

FIG. 4 shows a configuration of a TFT of the present invention. (Cross section)

FIG. 5 shows a manufacturing process of the TFT of the present invention. (Top view)

FIG. 6 shows a manufacturing process of the TFT of the present invention. (Cross section)

FIG. 7 shows a configuration of a TFT according to the first embodiment.

FIG. 8 shows a configuration of a TFT according to a second embodiment.

FIG. 9 shows a configuration and a manufacturing process of a TFT of Example 3.

FIG. 10 shows a configuration and a manufacturing process of a TFT of Example 4.

11 illustrates a configuration and a manufacturing process of a TFT of Example 5. FIG.

FIG. 12 shows a configuration of a monolithic active matrix circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Island-shaped semiconductor area 2 ... Impurity area 3 ... Gate electrode 4, 5 ... Impurity area (source, drain) 6 ... Channel formation area

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 G02F 1/1368

Claims (10)

(57) [Claims] 1. An island-shaped thin film semiconductor region formed on an insulating surface, an insulating film, a gate electrode, and the same as the gate electrode.
A thin-film semiconductor device having a single- layer wiring, wherein the thin-film semiconductor region includes an N-type source and a drain, and an intrinsic channel between the source and the drain.
And forming region, wherein the source or one electrically connected to by a P-type has a first impurity region of the drain, is provided with, on the channel forming region, edge of the thin film semiconductor region And a P-type crossing the channel forming region and not joining the source and the drain .
And the second impurity region is provided, a thin film semiconductor device characterized by capacitor is formed by the first impurity region and the insulating film and the wiring. 2. An island-shaped thin film semiconductor region formed on an insulating surface, an insulating film, a gate electrode, and the same as the gate electrode.
A thin-film semiconductor device having a single- layer wiring, wherein the thin-film semiconductor region includes an N-type source and a drain, and an intrinsic channel between the source and the drain.
And forming region, and the source or the first impurity region of either the type P which are joined in the drain, is provided with, on the channel forming region comprises a edge of the thin film semiconductor region, And a P-type crossing the channel formation region and not joining the source and the drain .
And the second impurity region is provided, a thin film semiconductor device characterized by capacitor is formed by the first impurity region and the insulating film and the wiring. 3. An island-shaped thin film semiconductor region formed on an insulating surface, an insulating film, a gate electrode, and the same as the gate electrode.
In a thin-film semiconductor device having a single-layer wiring and a pixel electrode, the thin-film semiconductor region includes: an N-type source and a drain; and an intrinsic channel between the source and the drain.
And forming region, and the source or the first impurity region of either the type P which are joined in the drain, is provided with, on the channel forming region comprises a edge of the thin film semiconductor region, And a P-type crossing the channel formation region and not joining the source and the drain .
A second impurity region is provided, the first impurity region, the insulating film, and the wiring;
Are formed capacity by, in the source or the drain and the first impurity region and the pixel electrode are in contact with portions, a thin film semiconductor device characterized by silicide is formed. 4. The method according to claim 1, wherein
2. The thin-film semiconductor device according to claim 1, wherein the second impurity region is a low-concentration impurity region. 5. The method according to claim 1, wherein
The first impurity region and the second impurity region include:
A thin-film semiconductor device having substantially the same impurity concentration. 6. An island-shaped thin film semiconductor region formed on an insulating surface, an insulating film, a gate electrode, and the same as the gate electrode.
A thin-film semiconductor device having a single- layer wiring, wherein the thin-film semiconductor region includes: a P-type source and a drain; and an intrinsic channel between the source and the drain.
And forming region, wherein the source or one electrically connected to with the N-type and a first impurity region of the drain, is provided with, on the channel forming region, edge of the thin film semiconductor region And an N-type crossing the channel formation region and not joining the source and the drain
And the second impurity region is provided, a thin film semiconductor device characterized by capacitor is formed by the first impurity region and the insulating film and the wiring. 7. An island-shaped thin film semiconductor region formed on an insulating surface, an insulating film, a gate electrode, and the same as the gate electrode.
A thin-film semiconductor device having a single- layer wiring, wherein the thin-film semiconductor region includes: a P-type source and a drain; and an intrinsic channel between the source and the drain.
And forming region, and the source or one first impurity region of the N type being joined to the drain, is provided with, on the channel forming region comprises a edge of the thin film semiconductor region, And an N-type crossing the channel formation region and not joining the source and the drain .
And the second impurity region is provided, a thin film semiconductor device characterized by capacitor is formed by the first impurity region and the insulating film and the wiring. 8. An island-shaped thin film semiconductor region formed on an insulating surface, an insulating film, a gate electrode, and the same as the gate electrode.
In the thin-film semiconductor device having a single-layer wiring and a pixel electrode, the thin-film semiconductor region includes: a P-type source and a drain; and an intrinsic channel between the source and the drain.
And forming region, and the source or one first impurity region of the N type being joined to the drain, is provided with, on the channel forming region comprises a edge of the thin film semiconductor region, And an N-type crossing the channel formation region and not joining the source and the drain .
A second impurity region is provided, the first impurity region, the insulating film, and the wiring;
Are formed capacity by, in the source or the drain and the first impurity region and the pixel electrode are in contact with portions, a thin film semiconductor device characterized by silicide is formed. 9. The method according to claim 6, wherein:
2. The thin-film semiconductor device according to claim 1, wherein the second impurity region is a low-concentration impurity region. 10. The thin film according to claim 6, wherein the first impurity region and the second impurity region have substantially the same impurity concentration. Semiconductor device.