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JP3381601B2 - バンプ付電子部品の実装方法 - Google Patents

バンプ付電子部品の実装方法

Info

Publication number
JP3381601B2
JP3381601B2 JP01248298A JP1248298A JP3381601B2 JP 3381601 B2 JP3381601 B2 JP 3381601B2 JP 01248298 A JP01248298 A JP 01248298A JP 1248298 A JP1248298 A JP 1248298A JP 3381601 B2 JP3381601 B2 JP 3381601B2
Authority
JP
Japan
Prior art keywords
solder
bumps
electronic component
substrate
precoat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP01248298A
Other languages
English (en)
Other versions
JPH11214441A (ja
Inventor
満 大園
秀喜 永福
忠彦 境
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP01248298A priority Critical patent/JP3381601B2/ja
Priority to US09/234,299 priority patent/US6209196B1/en
Publication of JPH11214441A publication Critical patent/JPH11214441A/ja
Application granted granted Critical
Publication of JP3381601B2 publication Critical patent/JP3381601B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01082—Lead [Pb]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/0132—Binary Alloys
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    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0209—Inorganic, non-metallic particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0379—Stacked conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0278—Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49204—Contact or terminal manufacturing
    • Y10T29/49208—Contact or terminal manufacturing by assembling plural parts
    • Y10T29/4921—Contact or terminal manufacturing by assembling plural parts with bonding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49204—Contact or terminal manufacturing
    • Y10T29/49208—Contact or terminal manufacturing by assembling plural parts
    • Y10T29/4921—Contact or terminal manufacturing by assembling plural parts with bonding
    • Y10T29/49211—Contact or terminal manufacturing by assembling plural parts with bonding of fused material

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、バンプ付電子部品
を基板に接合するバンプ付電子部品の実装方法に関する
ものである。
【０００２】
【従来の技術】電子部品を基板の回路パターンの電極に
実装する方法として、予め電子部品や基板の電極上に半
田バンプや半田プリコートなどの半田部を形成してお
き、この半田部により電子部品を基板の電極に半田接合
する方法が知られている。半田接合に際しては、予め半
田部または基板の電極上にフラックスを塗布した後、電
子部品を電極上に搭載し、半田を加熱溶融させることに
よって半田部と電極とを接合することが行われる。そし
て半田接合後には、実装後の信頼性を確保するためフラ
ックスの残さを除去する洗浄が行われ、その後バンプ付
電子部品と基板との隙間には、接合部を補強する目的で
アンダーフィル樹脂が充填され、このアンダーフィル樹
脂を熱処理によって硬化させて実装が完了する。
【０００３】
【発明が解決しようとする課題】しかしながら、上記バ
ンプ付電子部品の実装工程では、電子部品の小型化に伴
って以下に述べるような問題点が生じてきている。ま
ず、半田接合後の洗浄工程は、従来多用されていたフロ
ンなどの溶剤による洗浄方法が規制されたことから複雑
化、高コスト化し、電子部品の小型化と相まって、技術
的にも困難なものとなっている。また、アンダーフィル
樹脂については、電子部品の小型化により電子部品と基
板の隙間が小さくなって電子部品搭載後の樹脂充填が困
難となり、実装後の品質が安定しないという品質上の問
題点とともに、同一部品の実装に半田接合と樹脂の硬化
のための熱処理の２つの加熱工程を必要とし、工程を複
雑化する要因となっていた。
【０００４】そこで本発明は、実装時の接合に際しフラ
ックスを使用せず、低コストで実装後の信頼性が高いバ
ンプ付電子部品の実装方法を提供することを目的とす
る。
【０００５】
【課題を解決するための手段】請求項１記載のバンプ付
電子部品の実装方法は、電極が形成された基板上にフィ
ラーを含有した樹脂接着材を塗布する工程と、半田バン
プが形成されたバンプ付電子部品を前記基板上に搭載す
る工程と、前記バンプ付電子部品の半田バンプを前記基
板の電極に押圧することにより、前記半田バンプの表面
の酸化膜をフィラーにより破壊する工程と、前記半田バ
ンプを加熱して前記バンプ付電子部品を前記電極に接合
する工程とを含む。
【０００６】請求項２記載のバンプ付電子部品の実装方
法は、電極が形成されこの電極上に半田プリコートが形
成された基板上にフィラーを含有した樹脂接着材を塗布
する工程と、半田バンプが形成されたバンプ付電子部品
を前記基板上に搭載する工程と、前記半田バンプを前記
基板の電極上に形成された半田プリコートに押圧するこ
とにより、前記半田バンプおよび半田プリコートの表面
の酸化膜をフィラーにより破壊する工程と、前記半田バ
ンプおよび半田プリコートを加熱して前記バンプ付電子
部品を前記電極に接合する工程とを含む。
【０００７】請求項３記載のバンプ付電子部品の実装方
法は、請求項２記載の電子部品の実装方法であって、前
記電子部品の半田バンプと前記基板の電極の半田プリコ
ートのいずれか一方の半田材料として高融点型の半田を
用い、他方の半田の半田材料には低融点型の半田を用い
るようにした。
【０００８】請求項４記載のバンプ付電子部品の実装方
法は、電極が形成されこの電極上に半田プリコートが形
成された基板上にフィラーを含有した樹脂接着材を塗布
する工程と、金属バンプが形成されたバンプ付電子部品
を前記基板上に搭載する工程と、前記金属バンプを前記
基板の電極上に形成された半田プリコートに押圧するこ
とにより、前記半田プリコート表面の酸化膜をフィラー
により破壊する工程と、前記半田プリコートを加熱して
前記バンプ付電子部品を前記電極に接合する工程とを含
む。
【０００９】請求項５記載のバンプ付電子部品の実装方
法は、電極が形成されこの電極上に金属バンプが形成さ
れた基板上にフィラーを含有した樹脂接着材を塗布する
工程と、半田バンプが形成されたバンプ付電子部品を前
記基板上に搭載する工程と、前記半田バンプを前記基板
の電極上に形成された金属バンプに押圧することによ
り、前記半田バンプ表面の酸化膜をフィラーにより破壊
する工程と、前記半田バンプを加熱して前記バンプ付電
子部品を前記電極に接合する工程とを含む。
【００１０】各請求項記載の発明によれば、バンプ付電
子部品の搭載に先立ってフィラーを含有した樹脂接着材
を基板上に塗布し、半田部をフィラーを介して電極、電
極上に形成された半田部、または金属バンプに押圧して
半田部表面の酸化膜を破壊することにより、フラックス
を使用せずに電子部品を基板の電極に半田接合すること
ができる。
【００１１】
【発明の実施の形態】（実施の形態１）図１（ａ），
（ｂ），（ｃ）、図２（ａ），（ｂ）、図３は、本発明
の実施の形態１のバンプ付電子部品の実装方法の工程説
明図である。図１（ａ）において、基板１の上面には電
極２が形成されている。電極２の表面は金などの金属に
よって表面がめっきされている。基板１上には、図１
（ｂ）に示すようにディスペンサ３により電極２を覆っ
て樹脂接着材４が塗布される。樹脂接着材４には数ミク
ロン程度の大きさの固形粒子のフィラーが重量％にして
３０〜５０％含有されている。このフィラーは基板１と
基板１上に実装される電子部品の熱膨張率の差による熱
応力を緩和する作用を有するものであり、材質としては
シリカ等の無機材料や、樹脂等の有機材料のいずれをも
用いることができる。
【００１２】この後図１（ｃ）に示すように、基板１上
には圧着ツール８に保持されたバンプ付の電子部品５が
搭載される。電子部品５の電極６には半田バンプ７が形
成されており、半田バンプ７の表面には酸化膜７ａが生
成されている。半田バンプ７を電極２に半田接合するこ
とにより、電子部品５は基板１に実装される。
【００１３】この半田接合の過程を図２（ａ），（ｂ）
を参照して説明する。図２（ａ）は電子部品５を基板１
に対して下降させ、半田バンプ７の下端部が基板１の電
極２の表面に当接する直前の状態を示したものである。
図２（ａ）において、半田バンプ７の下端部表面の酸化
膜７ａと電極２の表面の間にはフィラー粒子４ａが介在
している。フィラーの含有量は前述のように３０〜５０
重量％となっているため、実際には無数のフィラー粒子
４ａが酸化膜７ａと電極２の隙間に存在する。
【００１４】この状態で圧着ツール８を更に下降させて
半田バンプ７を電極２に押圧すると、図２（ｂ）に示す
ように、電極２の表面に押し当てられた半田バンプ７の
酸化膜７ａはフィラー粒子４ａによって破壊される。半
田バンプ７の表面に形成される酸化膜７ａの厚さは数十
から数千オングストローム程度のきわめて薄い膜である
ため、フィラー粒子４ａにより容易に破壊され、半田バ
ンプ７の下端部と電極２の当接部には酸化膜７ａが破壊
された微小な半田の露出部が無数に形成される。
【００１５】次に、図３に示すように圧着ツール８の加
熱手段により電子部品５を介して半田バンプ７を加熱す
る。これにより半田バンプ７の温度は上昇し、温度が半
田の融点に到達すると半田バンプ７は溶融する。このと
き、半田バンプ７の下端部と電極２の当接面では、酸化
膜７ａが破壊された微小な半田の露出部が無数に形成さ
れているため、溶融した半田は電極２の上面に接触し半
田ぬれ性の良い電極２の上面に沿って拡がる。このとき
半田バンプ７と電極２の接合部の周囲は樹脂接着材が充
填されて無酸素雰囲気となっているため、酸化膜７ａが
破壊されて露出した半田が再び酸化されることがなく、
良好な半田接合が行われる。
【００１６】そしてこの状態で冷却されることにより、
溶融半田は固化して電極２の上面に半田接合される。こ
の後、加熱を継続して樹脂接着材４が硬化することによ
り、電子部品５の実装が完了する。この半田接合の過程
において、従来の方法では酸化膜７ａの除去に必要であ
ったフラックスを用いる必要がなく、したがって半田接
合後の洗浄を必要とせずに実装後の信頼性を確保するこ
とができる。
【００１７】（実施の形態２）図４（ａ），（ｂ），
（ｃ）、図５は、本発明の実施の形態２のバンプ付電子
部品の実装方法の工程説明図である。実施の形態１で
は、基板に実装される電子部品に半田バンプを形成する
こととしているが、本実施の形態２では基板、電子部品
にそれぞれ半田プリコート、半田バンプを形成するもの
である。
【００１８】図４（ａ）に示すように、基板１１の電極
１２上には半田プリコート１３が形成されている。次
に、実施の形態１（図１（ｂ）参照）と同様に基板１１
上にフィラーを含有した樹脂接着材４が塗布される。次
に、基板１１上に半田バンプ７を有するバンプ付きの電
子部品５が搭載され、半田接合される。
【００１９】このときの半田接合の過程について図５を
参照して説明する。電子部品５の半田バンプ７を基板１
１の半田プリコート１３に位置合わせして電子部品５を
基板１１に対して下降させ、半田バンプ７と半田プリコ
ート１３を当接させる。このとき半田バンプ７の表面の
酸化膜７ａと半田プリコート１３の表面の酸化膜１３ａ
の間には無数の微小なフィラー粒子４ａが介在してい
る。
【００２０】この状態で半田バンプ７と半田プリコート
１３を互いに押圧すると、酸化膜７ａと酸化膜１３ａの
双方がフィラー粒子４ａによって破壊され、酸化膜７ａ
と酸化膜１３ａの表面には微小な半田の露出部が無数に
生じる。そして圧着ツール８により電子部品５を加熱
し、温度が上昇して半田の融点温度に到達すると、半田
バンプ７と半田プリコート１３が溶融を開始する。そし
て半田バンプ７と半田プリコート１３は前述の半田の露
出部を介して融合して一体となり、その後固化すること
により電子部品５は電極１２に半田接合される。このと
き実施の形態１と同様に半田バンプ７と半田プリコート
１３の周囲は樹脂接着材が充填されて無酸素雰囲気とな
っているため、酸化膜７ａ，１３ａが破壊されて露出し
た半田が再び酸化されることがなく、良好な半田接合が
行われる。
【００２１】なお、上記実施の形態２においては、半田
バンプ７および半田プリコート１３ともに同一の半田を
用いているが、半田バンプ７、半田プリコート１３のい
ずれか一方の半田材料として高融点型の半田を、他方の
半田材料として低融点型の半田を用いることにより、以
下の効果を得ることができる。圧着ツール８によって電
子部品５を加熱する過程において、まず低融点型の半田
を用いた半田バンプ７または半田プリコート１３が溶融
を開始するが、この時点では他方はまだ溶融していな
い。このため電子部品５を基板１に対して押圧する際に
半田バンプ７と半田プリコート１３が同時に溶融して押
しつぶされることがなく、電子部品５の基板１上での実
装高さを保持して良好な半田接合部を得ることができ
る。
【００２２】ここで用いられる低融点型の半田の例とし
て、Ｓｎ６７％，Ｐｂ３７％、融点温度１８３℃の一般
的なものや、Ｓｎ３７．５％、Ｐｂ３７．５％、Ｉｎ２
５％融点温度１３８℃のものがある。また高融点型の例
としては、Ｓｎ９６．５％，Ａｇ３．５％、融点温度２
２１℃のもの、Ｓｎ５％、Ｐｂ９５％、融点温度３１４
℃のものなどがある。
【００２３】（実施の形態３）図６（ａ），（ｂ），
（ｃ）、図７は、本発明の実施の形態３のバンプ付電子
部品の実装方法の工程説明図である。本実施の形態３で
は基板の電極に半田プリコートを、電子部品の電極に金
属バンプを形成するものである。
【００２４】図６（ａ）に示すように、基板２１の電極
２２上には半田プリコート２３が形成されている。次
に、実施の形態１（図１（ｂ）参照）と同様に基板２１
上にフィラーを含有した樹脂接着材４が塗布される。次
に、基板２１上に金属バンプとしての金バンプ２７を有
する電子部品２５が搭載される。金属バンプを形成する
材質としては金以外のものでもよく、材質によってワイ
ヤボンディング法や、メッキ法、転写法などの方法を用
いてバンプが形成される。
【００２５】電子部品２５が基板２１に搭載され半田接
合される過程について図７を参照して説明する。電子部
品２５の金バンプ２７を基板２１の半田プリコート２３
に位置合わせして電子部品２５を基板２１に対して下降
させ、金バンプ２７と半田プリコート２３を当接させ
る。このとき金バンプ２７の表面の酸化膜２７ａと半田
プリコート２３の表面の酸化膜２３ａの間には無数の微
小なフィラー粒子４ａが介在している。
【００２６】この状態で金バンプ２７と半田プリコート
２３を互いに押圧すると、酸化膜２３ａがフィラー粒子
４ａによって破壊され、酸化膜２３ａの表面には微小な
半田の露出部が無数に生じる。そして圧着ツール８によ
り電子部品２５を加熱し、温度が上昇して半田の融点温
度に到達すると、半田バンプ２３が溶融を開始する。そ
して溶融した半田は半田濡れ性の良い金バンプ２７の表
面を濡らし、その後固化することにより電子部品２５は
電極２２に半田接合される。このとき実施の形態１と同
様に金バンプ２７と半田プリコート２３の周囲は樹脂接
着材が充填されて無酸素雰囲気となっているため、酸化
膜２３ａが破壊されて露出した半田が再び酸化されるこ
とがなく、良好な半田接合が行われる。
【００２７】なお、上記実施の形態３では電子部品２５
に金バンプ２７を、基板２１に半田プリコート２３を設
けるようにしているが、これを入れ替えて電子部品２５
に半田プリコートを、基板２１に金バンプを設けるよう
にしても良い。
【００２８】本発明は上記実施の形態１，２、３には限
定されないのであって、例えば上記実施の形態１、２、
３ではいずれも、加熱過程において半田を溶融させて半
田接合する例を示しているが、接合の形態としては半田
を融点温度まで昇温させず融点温度以下で押圧しながら
固相拡散接合させるものであっても良い。また各実施の
形態１、２、３では電子部品５を基板１，１１に押圧し
た後に圧着ツール８により加熱する例を示しているが、
加熱した状態で電子部品５を基板１，１１に当接させて
もよい。
【００２９】
【発明の効果】本発明によれば、電子部品の搭載に先立
ってフィラーを含有した樹脂接着材を基板上に塗布し、
電子部品およびまたは基板の電極に形成された半田バン
プや半田プリコートをフィラーを介して押圧して半田バ
ンプや半田プリコートの表面の酸化膜を破壊するように
しているので、フラックスを使用せずに電子部品を基板
に半田接合することができ、したがって半田接合後の洗
浄を必要としない。また、基板と電子部品の隙間に封入
されるアンダーフィル用の樹脂接着材を予め基板上に塗
布するようにしているので、狭い隙間の小型の電子部品
であっても良好な樹脂封止が行え、半田接合部を有効に
補強し信頼性の高い実装を行うことができる。
【図面の簡単な説明】
【図１】（ａ）本発明の実施の形態１のバンプ付電子部
品の実装方法の工程説明図 （ｂ）本発明の実施の形態１のバンプ付電子部品の実装
方法の工程説明図 （ｃ）本発明の実施の形態１のバンプ付電子部品の実装
方法の工程説明図
【図２】（ａ）本発明の実施の形態１のバンプ付電子部
品の実装方法の工程説明図 （ｂ）本発明の実施の形態１のバンプ付電子部品の実装
方法の工程説明図
【図３】本発明の実施の形態１のバンプ付電子部品の実
装方法の工程説明図
【図４】（ａ）本発明の実施の形態２のバンプ付電子部
品の実装方法の工程説明図 （ｂ）本発明の実施の形態２のバンプ付電子部品の実装
方法の工程説明図 （ｃ）本発明の実施の形態２のバンプ付電子部品の実装
方法の工程説明図
【図５】本発明の実施の形態２のバンプ付電子部品の実
装方法の工程説明図
【図６】（ａ）本発明の実施の形態３のバンプ付電子部
品の実装方法の工程説明図 （ｂ）本発明の実施の形態３のバンプ付電子部品の実装
方法の工程説明図 （ｃ）本発明の実施の形態３のバンプ付電子部品の実装
方法の工程説明図
【図７】本発明の実施の形態３のバンプ付電子部品の実
装方法の工程説明図
【符号の説明】 １、１１、２１ 基板 ２、１２、２２ 電極 ３ ディスペンサ ４ 樹脂接着材 ４ａ フィラー粒子 ５、２５ 電子部品 ７ 半田バンプ ７ａ、１３ａ、２３ａ 酸化膜 １３ 半田プリコート ２７ 金バンプ
フロントページの続き (56)参考文献 特開 平２−207592（ＪＰ，Ａ) 特開 平９−167773（ＪＰ，Ａ) 特開 平９−260421（ＪＰ，Ａ) 特開 平10−294337（ＪＰ，Ａ) 特開 平10−308417（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60

Claims (5)

    (57)【特許請求の範囲】
  1. 【請求項１】電極が形成された基板上にフィラーを含有
    した樹脂接着材を塗布する工程と、半田バンプが形成さ
    れたバンプ付電子部品を前記基板上に搭載する工程と、
    前記バンプ付電子部品の半田バンプを前記基板の電極に
    押圧することにより、前記半田バンプの表面の酸化膜を
    フィラーにより破壊する工程と、前記半田バンプを加熱
    して前記バンプ付電子部品を前記電極に接合する工程と
    を含むことを特徴とするバンプ付電子部品の実装方法。
  2. 【請求項２】電極が形成されこの電極上に半田プリコー
    トが形成された基板上にフィラーを含有した樹脂接着材
    を塗布する工程と、半田バンプが形成されたバンプ付電
    子部品を前記基板上に搭載する工程と、前記半田バンプ
    を前記基板の電極上に形成された半田プリコートに押圧
    することにより、前記半田バンプおよび半田プリコート
    の表面の酸化膜をフィラーにより破壊する工程と、前記
    半田バンプおよび半田プリコートを加熱して前記バンプ
    付電子部品を前記電極に接合する工程とを含むことを特
    徴とするバンプ付電子部品の実装方法。
  3. 【請求項３】前記電子部品の半田バンプと前記基板の電
    極の半田プリコートのいずれか一方の半田材料として高
    融点型の半田を用い、他方の半田の半田材料には低融点
    型の半田を用いることを特徴とする請求項２記載のバン
    プ付電子部品の実装方法。
  4. 【請求項４】電極が形成されこの電極上に半田プリコー
    トが形成された基板上にフィラーを含有した樹脂接着材
    を塗布する工程と、金属バンプが形成されたバンプ付電
    子部品を前記基板上に搭載する工程と、前記金属バンプ
    を前記基板の電極上に形成された半田プリコートに押圧
    することにより、前記半田プリコート表面の酸化膜をフ
    ィラーにより破壊する工程と、前記半田プリコートを加
    熱して前記バンプ付電子部品を前記電極に接合する工程
    とを含むことを特徴とするバンプ付電子部品の実装方
    法。
  5. 【請求項５】電極が形成されこの電極上に金属バンプが
    形成された基板上にフィラーを含有した樹脂接着材を塗
    布する工程と、半田バンプが形成されたバンプ付電子部
    品を前記基板上に搭載する工程と、前記半田バンプを前
    記基板の電極上に形成された金属バンプに押圧すること
    により、前記半田バンプ表面の酸化膜をフィラーにより
    破壊する工程と、前記半田バンプを加熱して前記バンプ
    付電子部品を前記電極の金属バンプに接合する工程とを
    含むことを特徴とするバンプ付電子部品の実装方法。
JP01248298A 1998-01-26 1998-01-26 バンプ付電子部品の実装方法 Expired - Lifetime JP3381601B2 (ja)

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US09/234,299 US6209196B1 (en) 1998-01-26 1999-01-21 Method of mounting bumped electronic components

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