JP3374115B2 - Variable resistance circuit, operational amplifier circuit and integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable resistance circuit which changes the resistance value by turning on / off a plurality of switches connected in parallel to each of a plurality of resistors connected in series. The present invention relates to an operational amplifier circuit using the same and a semiconductor integrated circuit using the operational amplifier circuit.

[0002]

2. Description of the Related Art In recent years, CD (Compact Disc) drives,
Optical disk drive devices such as CD-ROM (Compact Disc Read Only Memory) drives have become popular, and various semiconductor integrated circuits used in these optical disk drive devices have been developed.

FIG. 6 is a block diagram showing the structure of a semiconductor integrated circuit used in a conventional CD-ROM drive.

The circuit shown in FIG. 6 is composed of a plurality of semiconductor integrated circuits, and includes a signal processing circuit 200 and an RF (Radio Freq) circuit.
uency) amplifier 220, drive circuit 230, microcomputer (microcomputer) 240, and DRAM (Dynamic)
Random Access Memory) 250.

The signal processing circuit 200 includes a DSP (Digital
Signal Processor) 201, DAC (Digital Analog C)
onverter) 202, a servo circuit 203, and an error correction circuit 204. The RF amplifier 220 is composed of a bipolar integrated circuit as a separate component, and is used as the signal processing circuit 200.
Is a CMOS (Complementary Metal Oxide Semiconduc
tor) integrated into one chip.

CD-ROM with optical pickup 210
The data recorded on the disc is converted into RF signal,
It is output to the RF amplifier 220. The RF amplifier 220 is
A reproduction signal (EFM (Eight to F
ourteen Modulation) signal), a focus error signal, a tracking error signal, etc., and outputs them to the signal processing circuit 200.

The signal processing circuit 200 creates a control signal for controlling the optical pickup 210 from the focus error signal and the tracking error signal by the DSP 201 and the servo circuit 203, and outputs it to the drive circuit 230. The drive circuit 230 drives the actuator in the optical pickup 210 according to the input control signal,
Optical pickup 210 so as to reproduce a good RF signal
Is controlled.

In addition, the signal processing circuit 200 performs error correction of reproduced data by using the DRAM 250 by the error correction circuit 204, and when reproducing a voice signal, the DAC 2 is used.
The reproduction data is converted into an analog signal by 02 and output.

The microcomputer 240 functions as a system controller for controlling the operation of the entire drive, transmits / receives data and the like to / from the signal processing circuit 200 as necessary, and a CD-
Various operations of the ROM drive are performed.

The RF amplifier 220 of the CD-ROM drive configured as described above is a CD, a CD-ROM, a CD.
In order to reproduce various optical discs such as RW (Compact Disc Rewritable), the amplification factor of the RF signal is variously changed internally in order to deal with the RF signal of various levels. Therefore, the RF amplifier 220 is provided with a PGA (programmable gain amplifier) or the like that changes the amplification factor of the RF signal, and a variable resistance circuit that can set various resistance values for gain adjustment is used.

FIG. 7 is a circuit diagram showing the structure of a conventional variable resistance circuit. The variable resistance circuit shown in FIG. 7 includes a decoding circuit 300, switches SW0 to SW255, and resistors TR0 to TR0.
Includes TR255.

The 256 resistors TR0 to TR255 are connected in series, the resistance value of all the resistors TR0 to TR255 is set to R (Ω), and the resistors TR0 to TR255 are the same resistor. The switches SW0 to SW255 are connected in parallel to the corresponding resistors TR0 to TR255, and the switches SW0 to SW255 are the same switch. When the switches SW0 to SW255 are turned on, the resistors connected to the switches are bypassed,
The resistance value of the variable resistance circuit changes.

8-bit control signals d1 to d8 are input to the decoding circuit 300. The control signal d1 is a control signal representing the least significant bit, and the control signal d8 is a control signal representing the most significant bit. , Each value of 0 to 255 can be represented by the control signals d1 to d8. Decoding circuit 3
00 decodes 8-bit control signals d1 to d8,
A control signal for setting the resistance value corresponding to the data represented by the 8-bit control signals d1 to d8 by turning on / off the switches SW0 to SW255 is set.
Output to.

The switches SW0 to SW255 are turned on / off by control signals output from the decoding circuit 300, and the turned-on switches bypass the resistors.
Therefore, it is 2 depending on the 8-bit control signals d1 to d8.
By bypassing any resistance of the 56 resistances TR0 to TR255, the resistance value of the variable resistance circuit becomes 0.
(Ω), R (Ω), 2R (Ω), ..., 255R (Ω).

FIG. 8 is a circuit diagram showing the structure of another conventional variable resistance circuit. The variable resistance circuit shown in FIG. 8 includes switches SW10 to SW17 and resistors TR10 to TR17. The eight resistors TR10 to TR17 are connected in series, the resistance value of the resistor TR10 is R (Ω), and the resistance TR
The resistance value of 11 is 2R (Ω), the resistance value of the resistor TR12 is 4R (Ω), and thereafter, the resistance value of each resistor is 2 in order.
The resistance value of the final resistance TR17 is multiplied by 128R (Ω)
Is set to.

The switches SW10 to SW17 are connected in parallel to the corresponding resistors TR10 to TR17, and when the switches SW10 to SW17 are turned on, the resistors connected to the switches are bypassed.

The above-mentioned 8-bit control signals d1 to d8 are input to the switches SW10 to SW17, and the resistance values of the variable resistance circuit are 0 (Ω), R (Ω), and 2R.
(Ω), ..., 255 R (Ω) is set to an arbitrary resistance value.

[0018]

As described above, the variable resistance circuit shown in FIG. 7 requires 256 resistors TR0 to TR255 and switches SW0 to SW255 in order to realize 8-bit resolution. Decoding circuit 300 for decoding 8-bit control signals d1 to d8
Will also be required. Therefore, the circuit area of the variable resistance circuit becomes very large, and when the variable resistance circuit having such a large circuit area is integrated with other circuits, the area of the integrated circuit increases.

In the variable resistance circuit shown in FIG. 8, the linear resistance of the variable resistance circuit deteriorates due to the parasitic resistance of the switches SW10 to SW17. That is, the resistance value of the parasitic resistance of each of the switches SW10 to SW17 is r (Ω).
Then, when all the switches SW10 to SW17 are off, the resistance value of the variable resistance circuit becomes 255 R (Ω), the switch SW10 turns on, and the switches SW11 to SW11
When SW17 is off, 254R + r × R / (r
+ R) (Ω), the switch SW11 is turned on, and the switches SW10 and SW12 to SW17 are turned off, then 253R + 2r × R / (r + 2R) (Ω),
The switches SW10 and SW11 are turned on, and the switch SW1
2 to SW17 is off, 252R + r × R /
(R + R) + 2r × R / (r + 2R) (Ω).

As described above, the amount of change in the resistance value of the variable resistance circuit is R−r × R / (r + R) (Ω), R + r × R /
(R + R) -2r × R / (r + 2R) (Ω), R−r ×
R / (r + R) (Ω) and resistances TR10 to TR17
The amount of change in the resistance value due to is constant, but the switch SW1
The amount of change in resistance value due to the parasitic resistance of 0 to SW17 is not constant. Therefore, the amount of change is not constant, and the linearity of the resistance value of the variable resistance circuit deteriorates due to the parasitic resistance of the switches SW10 to SW17.

In order to ensure the linearity of the resistance value of the variable resistance circuit, the sizes of the switches SW10 to SW17 are set so that the parasitic resistance of the switches SW10 to SW17 hardly affects the resistance value of the variable resistance circuit. It has to be big enough. Therefore, the circuit area of the variable resistance circuit becomes large, and when the variable resistance circuit having such a large circuit area is integrated with other circuits, the area of the integrated circuit increases.

As described above, in the conventional variable resistance circuit,
It is difficult to reduce the area of the circuit, or it is possible to reduce the area, but it is difficult to increase the precision of the resistance value.

An object of the present invention is to use a variable resistance circuit capable of reducing a circuit area and setting a resistance value with high accuracy, an operational amplifier circuit using the resistance circuit, and an operational amplifier circuit. Another object of the present invention is to provide a semiconductor integrated circuit.

[0024]

[Means for Solving the Problems and Effects of the Invention] (1)
1st invention The variable resistance circuit which concerns on 1st invention WHEREIN: The resistance value of at least 1 resistance differs, and each of N resistance (N is an integer greater than or equal to 2) resistance and N resistance are connected. And N switches connected in parallel to, and turning on / off the N switches.
In a variable resistance circuit that changes a resistance value by turning off, the resistance value of each parasitic resistance of N switches when turned on is proportional to the resistance value of a resistance to which the switch is connected in parallel. Or, it has a positive correlation similar to proportionality.

In the variable resistance circuit according to the present invention, N resistors are connected in series, a switch is connected in parallel to each of the N resistors, and the switch is turned on to connect to the switch that is turned on. The resistance is bypassed and the resistance value changes. At this time, since the resistance value of at least one of the N resistances is different, it is possible to set various resistance values equal to or larger than the number of resistances by changing the combination of bypassed resistances. Many resistance values can be set with. In addition, since the resistance value of the parasitic resistance of the switch when turned on has a positive correlation that is proportional to or similar to the resistance value of the resistor connected in parallel, the parasitic resistance and the resistance of the switch are The combined resistance value of is proportional to the resistance value of the resistance, and the linearity of the resistance value of the variable resistance value can be ensured. As a result, the circuit area of the variable resistance circuit can be reduced and the resistance value can be set with high accuracy.

(2) Second Invention A variable resistance circuit according to a second invention is the variable resistance circuit according to the first invention, wherein each of the N switches is
The transistor includes a transistor connected in parallel to the resistor, and the gate width of the transistor is inversely proportional to or has a negative correlation similar to the inverse proportional to the resistance value of the resistor to which the transistor is connected in parallel.

In this case, the resistance value of the parasitic resistance of the transistor can be made proportional to the resistance value of the resistor by the gate width of the transistor being inversely proportional to the resistance value of the resistor or having a negative correlation similar to the inverse proportionality. Therefore, the parasitic resistance can be adjusted only by changing the gate width, and the variable resistance circuit can be easily manufactured.

(3) Third Invention A variable resistance circuit according to a third invention is the variable resistance circuit according to the first or second invention, wherein each resistance value of N resistors is R × 2. ⁱ (i is an integer from 0 to (N-1))
The resistance value of each parasitic resistance of the N switches is set to r × 2 ⁱ (Ω).

In this case, since 2 ^N different resistance values can be set by ^N resistors, the circuit area of the variable resistance circuit can be made extremely small and 2 ^N different control signals can be obtained by the N-bit control signal. Since the resistance value can be set to any resistance value, the control of the variable resistance circuit becomes easy.

(4) Fourth Invention A variable resistance circuit according to a fourth invention is the variable resistance circuit according to the first to third inventions, wherein the switch is a CMO.
It consists of an S switch. In this case, the circuit including the variable resistance circuit can be configured by a CMOS integrated circuit.

(5) Fifth Invention In the operational amplifier circuit according to the fifth invention, the variable resistance circuit according to any one of the first to fourth inventions and the variable resistance circuit are connected, and the resistance of the variable resistance circuit is connected. And an operational amplifier that changes the amplification factor according to the value.

In the operational amplifier circuit according to the present invention, the variable resistance circuit according to any one of the first to fourth inventions is connected to the operational amplifier, and the resistance of the variable resistance circuit capable of changing the resistance value with high accuracy. Since the amplification factor is changed according to the value, it is possible to set the amplification factor with high accuracy and
Since the circuit area of the variable resistance circuit is small, the circuit area of the operational amplifier circuit can also be reduced.

(6) Sixth Invention In the operational amplifier circuit according to the sixth invention, in the configuration of the operational amplifier circuit according to the fifth invention, the variable resistance circuit is connected to the input terminal of the operational amplifier, and N variable resistance circuits are connected. The resistor having the largest resistance value is connected to the input terminal.

In this case, a parasitic capacitance is formed on the node connecting the resistors by the switch, and the parasitic capacitance and the CR time constant of the resistors affect the parasitic capacitance, but the resistance value of the resistor connected to the input terminal is the largest. Therefore, the parasitic capacitance that acts on the resistor having the largest resistance value is minimized, the CR time constant of the variable resistance circuit itself can be reduced in total, and an operational amplifier circuit with good frequency characteristics can be realized.

(7) Seventh Invention A semiconductor integrated circuit according to a seventh invention includes an operational amplifier circuit according to the fifth or sixth invention, and includes an amplifier circuit for amplifying an output signal from an optical pickup, The amplifier circuit and the other circuit are formed as a single chip by a CMOS integrated circuit.

In the semiconductor integrated circuit according to the present invention, the amplification factor for amplifying the output signal from the optical pickup can be set with high accuracy and the circuit area can be reduced. Since the operational amplifier circuit according to the sixth aspect of the present invention is used and the amplifier circuit is formed as one chip with other circuits and a CMOS integrated circuit, it is possible to provide a high precision and area-saving amplifier circuit for an optical disk drive device. A chip CMOS integrated circuit can be realized.

[0037]

1 is a circuit diagram showing the configuration of a variable resistance circuit according to an embodiment of the present invention.

In FIG. 1, the variable resistance circuit VT includes resistors T1 to T8 and switches S1 to S8. Resistance T1
Is connected between the terminal N1 and the resistor T2, and the switch S1 is connected in parallel to the resistor T1. Similarly, the resistors T2 to T8 and the switches S2 to S8, which are connected in parallel, are similarly set thereafter.
Are connected in series. 8-bit control signals d1 to d8 are input to the switches S1 to S8, and control signals d1 to d
The switches S1 to S8 are turned on / off in accordance with No.

The resistance value of the resistor T1 is R (Ω), the resistance value of the resistor T2 is 2R (Ω), and thereafter, the resistors T3 to T
Each resistance value of 8 is sequentially set to double. That is, the resistance values of the resistors T1 to T8 are R × 2 ⁱ (i = 0 to 7).
Set to (Ω). Also, the switch S when turned on
The resistance value of each parasitic resistance of 1 to S8 is r × 2 ⁱ (i = 0 to 0).
7) Set to (Ω). Therefore, the resistors T1 to T
8 and the switch S1 connected in parallel with the resistance.
The resistance values of the parasitic resistances of ~ S8 are proportional.

The control signals d1 to d8 correspond to 8-bit data, the control signal d1 corresponds to the least significant bit, the control signal d8 corresponds to the most significant bit, and the control signals d1 to d8. Can represent each value from 0 to 255. When the control signals d1 to d8 are 1, the switches S1 to S8 are off, and when the control signals d1 to d8 are 0, the switches S1 to S8.
Turns on and bypasses the resistor connected to the turned on switch.

For example, the control signals d1 to d8 are 1,
When 1, 1, 1, 1, 1, 1, 1, 1 are input to the switches S1 to S8, the switches S1 to S8 are all turned off, and the resistance value of the variable resistance circuit VT is the resistance value of the resistors T1 to T8. They are added up to become 255R (Ω).

The control signals d1 to d8 are 0, 1, 1,
When 1, 1, 1, 1, 1 is input, the switch S1 is turned on and the switches S2 to S8 are turned off. At this time, the resistors T2 to T8 are connected in series, and the resistance value of this part is 25
4R (Ω), the combined resistance value of the switch S1 and the resistor T1 is r × R / (r + R) (Ω), and the resistance value of the variable resistance circuit VT is 254R + r × R / (r + R) (Ω).
Becomes

The control signals d1 to d8 are 1, 0, 1,
When 1, 1, 1, 1, 1 is input, the variable resistance circuit VT
Has a resistance value of 253R + 2r × R / (r + R) (Ω), and thereafter, similarly, the resistance value of the variable resistance circuit VT changes according to the control signals d1 to d8, and the value of 1, 0, 0, 0, 0, 0,
When 0, 0 is input, the resistance value of the variable resistance circuit VT is R
+ 254r × R / (r + R) (Ω) becomes 0, 0,
When 0, 0, 0, 0, 0, 0 is input, the resistance value of the variable resistance circuit VT becomes 255r × R / (r + R) (Ω).

As described above, the resistance value of the variable resistance circuit VT is R-r * R / (r +) according to the control signals d1 to d8.
R) (Ω) changes in steps. In this way, the variable resistance circuit V
The resistance value of T changes at a constant rate of R−r × R / (r + R) (Ω), and linearity can be ensured.

Since ⁸ resistance values can be set by the ^eight resistors T1 to T8, the circuit area of the variable resistance circuit VT can be made very small and the 8-bit control signal d1 can be set. can be set to an arbitrary resistance value of the resistance of two ways ⁸ by d8,
The resistance value of the variable resistance circuit VT can be easily controlled.

Although eight resistors and switches have been used in the above description, the number of resistors and switches connected in series is not particularly limited to the above example, and may be varied depending on the resistance value to be changed. Other numbers of resistors and switches may be used. Further, the resistance value of each resistor is not particularly limited to the above example, and various resistance values can be used according to the resistance value to be changed, and the arrangement thereof is from the terminal N1 to the terminal N2 as described above. There is no particular limitation to the arrangement in which the resistances are sequentially increased, and the resistors may be arranged at different positions. Further, the resistance value of the parasitic resistance may not be completely proportional to the resistance value of the resistor, but may have a positive correlation similar to the resistance value of the resistor.

FIG. 2 is a circuit diagram showing an example of the switches S1 to S8 shown in FIG. The switch Si shown in FIG.
N-channel MOS field effect transistor (hereinafter referred to as NM
It includes an OS transistor Q1, a P-channel MOS field effect transistor (hereinafter referred to as a PMOS transistor) Q2, and an inverter I1.

NMOS transistor Q1 and PMOS
The transistor Q2 is connected between the terminal N11 and the terminal 12, the control signal di (i = 1 to 8) is input to the gate of the NMOS transistor Q1 via the inverter I1, and the gate of the PMOS transistor Q2 is controlled. Signal d
i is input, and a CMOS switch is configured. Therefore, when 1 is input as the control signal di, the NMOS
The transistor Q1 and the PMOS transistor Q2 turn off, and when 0 is input, they turn on.

When the CMOS switch configured as described above is used for the switches S1 to S8 shown in FIG.
The gate lengths of the S transistor Q1 and the PMOS transistor Q2 are made constant, the gate width W is changed, and the resistance value of the parasitic resistance of the switch is set as described above.

That is, when the gate width of the NMOS transistor Q1 and the PMOS transistor Q2 of the switch S1 is W, the gate width of the NMOS transistor Q1 and the PMOS transistor Q2 of the switch S2 is W /
Set to 2, NMOS transistor Q of switch S3
1 and the gate width of the PMOS transistor Q2 is W / 4
The gate width is sequentially set to ½ in the same manner. By changing the gate width in this way,
The resistance value of the parasitic resistance of each CMOS switch is r × 2 ⁱ
(I = 0 to 7) (Ω) can be set.

As described above, the switches S1 to S8
, The linearity of the variable resistance circuit VT does not depend on the resistance value of the parasitic resistance.
There is no need to increase the transistor size,
The circuit area of the variable resistance circuit can be reduced.

The switches S1 to S8 are connected to the CM described above.
The switch is not particularly limited to the OS switch, and another switch may be used as long as the resistance value of the parasitic resistance when turned on can be set according to the resistance value of the connected resistance. Also,
The gate width of the transistor may not be completely inversely proportional to the resistance value of the resistor, but may have a negative correlation similar to the inversely proportional to the resistance value of the resistor.

FIG. 3 is a diagram showing an example of an operational amplifier circuit using the variable resistance circuit shown in FIG. The operational amplifier circuit shown in FIG. 3 includes a variable resistance circuit VT, an operational amplifier 1 and a resistor T9.

In FIG. 3, a resistor T9 is connected between the inverting input terminal of the operational amplifier 1 and the terminal N1, and the non-inverting input terminal receives a predetermined reference voltage. Also, the operational amplifier 1
1 is connected between the inverting input terminal and the output terminal of the variable resistance circuit VT shown in FIG.
1 and the switch S1 are connected to the output terminal, and the resistor T8
And the switch S8 is connected to the inverting input terminal.

With the above configuration, in the operational amplifier circuit shown in FIG. 3, the resistance value of the variable resistance circuit VT is set to VR, and the resistance T
When the resistance value of 9 is Rf, the signal input to the terminal N1 is amplified by the amplification factor of VR / Rf and output from the terminal N3. At this time, the variable resistance circuit VT controls the control signal d1.
Since the resistance value VR can be changed with good linearity in 256 steps according to ~ d8, it is possible to highly accurately amplify the signal input from the terminal N1 and output it from the terminal N3.

Further, the resistance values of the resistors T1 to T8 gradually increase from the terminal N3 side, and the resistance value of the resistor T8 connected to the inverting input terminal becomes the largest. At this time, the switches S1 to S8 are connected to nodes connecting the resistors T1 to T8.
When the resistance value of the resistance is large, C
The R time constant becomes large and the frequency characteristic of the operational amplifier circuit deteriorates.

However, in the operational amplifier circuit shown in FIG. 3, since the resistors T1 to T8 are arranged as described above, the signal fed back from the output terminal of the operational amplifier is in order from the resistor 1 having the smallest resistance value. It is transmitted. At this time,
There are a plurality of nodes beyond the first resistor R1 and the parasitic capacitance is the largest, but only one node is beyond the last resistor R8, and the parasitic capacitance is the smallest. Therefore, the parasitic capacitance acting on the resistor R8 having the largest resistance value can be minimized, the CR time constant of the variable resistance circuit itself can be reduced in total, and the frequency characteristic of the operational amplifier circuit can be improved. it can.

In the above description, the arrangement of the resistors is explained when the variable resistance circuit VT is used as the resistors forming the negative feedback loop, but the variable resistance circuit VT is used as the input resistor for the same reason as above. Also in this case, it is preferable to maximize the resistance value of the resistor connected to the inverting input terminal.

FIG. 4 is a circuit diagram showing a configuration of a signal processing unit of a tracking system of an RF amplifier using the operational amplifier circuit shown in FIG.

In FIG. 4, a four-division light detection unit provided in the center for performing focus servo using the astigmatism method and a four-division light detection unit for performing tracking servo using the three-beam method. RF for a CD-ROM drive that processes each signal output from an optical pickup using a photodetector including two photodetectors provided on both sides of
The part of the amplifier that outputs the tracking error signal TE by subtracting the tracking signal F of the other photodetector from the tracking signal E from one photodetector for tracking servo to perform the tracking servo is shown. .

The RF amplifier shown in FIG. 4 has resistors T11 to T.
23, operational amplifiers 11 to 18, variable resistance circuits VT11 to VT11
It includes a VT15, capacitors C11 and C12, and a variable capacitor VC11.

One end of the resistor T11 is connected to the terminal N11 and receives the tracking signal E from one photodetector.
The inverting input terminal of the operational amplifier 11 is connected to the other end of the resistor T11, the non-inverting input terminal is connected to the terminal N13 that receives the shift voltage VREF1, and the resistor T13 is connected between the inverting input terminal and the output terminal. . As a result, the terminal N1
The tracking signal E input from 1 is applied to the shift voltage VR
The EF1 configures a level shift circuit that shifts a 5V signal to a 3V signal.

Output terminal of operational amplifier 11 and operational amplifier 1
The variable resistance circuit VT11 is connected between the inverting input terminal of the operational amplifier 13 and the non-inverting input terminal of the operational amplifier 13, and the non-inverting input terminal of the operational amplifier 13 receives a predetermined reference voltage. T15 is connected. Variable resistance circuit VT
11 is configured similarly to the variable resistance circuit shown in FIG. 1 by using a plurality of resistors, and four kinds of resistance values can be set as the resistance value of the variable resistance circuit VT11.

With this, a programmable gain amplifier is constructed, and the gain of 0 dB, 6 dB, 14 dB, or 20 dB can be set as the gain of the programmable gain amplifier. Therefore, the RF amplifier shown in FIG.
It is compatible with two types of optical pickups that output V and 600 mV signals, and has an amplification factor of 14
By switching the dB, it is possible to support an optical pickup for a CD-RW drive.

Output terminal of operational amplifier 13 and operational amplifier 1
A resistor T17 is connected between the inverting input terminal of the operational amplifier 15 and the non-inverting input terminal of the operational amplifier 15, and a variable resistance circuit is provided between the inverting input terminal and the output terminal of the operational amplifier 15. The VT 13 is connected. The variable resistance circuit VT13 is configured similarly to the variable resistance circuit shown in FIG. 1, and can switch the resistance value in 256 steps in accordance with an 8-bit control signal. Thereby, the balance circuit is configured, and the range of 0 dB to 6 dB can be switched in 256 steps in accordance with the 8-bit control signal.

One end of the resistor T12 is connected to the terminal N12 and receives the tracking signal F from the other photodetector.
The inverting input terminal of the operational amplifier 12 is connected to the other end of the resistor T12, the non-inverting input terminal is connected to the terminal N13 that receives the shift voltage VREF1, and the resistor T14 is connected between the inverting input terminal and the output terminal. . As a result, the terminal N1
The tracking signal F input from 2 is applied to the shift voltage VR
The EF1 configures a level shift circuit that shifts a 5V signal to a 3V signal.

Output terminal of operational amplifier 12 and operational amplifier 1
The variable resistance circuit VT12 is connected between the inverting input terminal of the operational amplifier 14 and the non-inverting input terminal of the operational amplifier 14, and a resistance is provided between the inverting input terminal and the output terminal of the operational amplifier 14. T16 is connected. Variable resistance circuit VT
The variable resistance circuit 12 has the same configuration as the variable resistance circuit VT11, and four kinds of resistance values can be set as the resistance value of the variable resistance circuit VT12. With this, the programmable gain amplifier is configured, and as the amplification factor of the programmable gain amplifier,
Amplification factors of 0 dB, 6 dB, 14 dB and 20 dB can be set.

Output terminal of operational amplifier 14 and operational amplifier 1
A resistor T18 is connected to the inverting input terminal of the operational amplifier 6, a non-inverting input terminal of the operational amplifier 16 is connected to a terminal N25 which receives a reference voltage VDA2 which can be set from the outside, and an inverting input terminal of the operational amplifier 16 and an output. The variable resistance circuit VT14 is connected between the terminals. Variable resistance circuit VT14
Is configured similarly to the variable resistance circuit VT13, and the resistance value can be switched in 256 steps in accordance with an 8-bit control signal. With this, a balance circuit is configured, and a range of 0 dB to 6 dB is set to 256 in accordance with an 8-bit control signal.
You can switch in stages.

Output terminal of operational amplifier 15 and operational amplifier 1
A resistor T19 is connected between the non-inverting input terminal 7 and
A capacitor C11 and a resistor T21 are connected between the inverting input terminal and the non-inverting output terminal of the operational amplifier 17, and a resistor T20 is connected between the output terminal of the operational amplifier 16 and the non-inverting input terminal of the operational amplifier 17. And operational amplifier 17
A resistor T22 is provided between the non-inverting input terminal and the inverting output terminal of
And a capacitor C12 are connected, and the inverting output terminal of the operational amplifier 17 receives a predetermined reference voltage. This allows
A subtracting circuit is configured, and a signal obtained by subtracting the output of the operational amplifier 15 from the output of the operational amplifier 16 is output from the non-inverting output terminal of the operational amplifier 17.

The variable resistance circuit VT1 is provided between the non-inverting output terminal of the operational amplifier 17 and the inverting input terminal of the operational amplifier 18.
5 is connected, the non-inverting input terminal of the operational amplifier 18 receives a predetermined reference voltage, and the variable capacitor VC11 and the resistor T are provided between the inverting input terminal and the output terminal of the operational amplifier 18.
23 is connected.

The variable resistance circuit VT15 is constructed in the same manner as the variable resistance circuit shown in FIG. 1 by using a plurality of resistors, and the resistance value can be switched in 16 steps in accordance with a 4-bit control signal. Further, the variable capacitor VC11 is configured so that two kinds of capacitance can be set as its capacitance.

With this, a programmable gain amplifier is constructed, and -6 dB to 6 dB depending on a 4-bit control signal.
The dB range can be switched in 16 steps, and two types of frequency characteristics can be set.

With the above structure, the tracking signal E of one photodetector is shifted from the 5V system signal to the 3V system signal by the shift voltage VREF1 by the operational amplifier 11 functioning as a level shift circuit, and as a programmable gain amplifier. 0d by operational amplifier 13
It is amplified by an amplification factor of any of B, 6 dB, 14 dB, and 20 dB, and is balanced-adjusted at any level of 256 levels in the range of 0 dB to 6 dB by the operational amplifier 15 functioning as a balance circuit, and the other photodetection unit The output signal F is processed in the same manner as above.

In this way, the output signals E and F whose levels and the like have been adjusted are operated by the operational amplifier 1 functioning as a subtraction circuit.
7 and finally -6 by the operational amplifier 18.
The tracking error signal TE is output after being amplified by any one of 16 amplification factors in the range of dB to 6 dB.

The signal processing unit of the focus system (not shown) is also constructed in the same manner as described above, and (A + C)-(B + D) is calculated using the output signals A, B, C, D of the four-division light detecting unit. Then, the focus error signal FE is output.

As described above, the RF amplifier shown in FIG. 4 uses many variable resistance circuits. By using the variable resistance circuit of the present invention, the area of the variable resistance circuit can be reduced and The resistance value can be set with high accuracy. Therefore, the area of the RF amplifier itself can be reduced and the accuracy can be improved.

FIG. 5 shows a CD including the RF amplifier shown in FIG.
FIG. 3 is a block diagram showing a configuration of a semiconductor integrated circuit for ROM drive.

The semiconductor integrated circuit 100 shown in FIG.
It includes an amplifier 101, a DSP 102, a DAC 103, a servo circuit 104, a microcomputer 105, an error correction circuit 106 and a DRAM 107.

The semiconductor integrated circuit 100 includes the RF amplifier 10
1, DSP102, DAC103, servo circuit 104,
Microcomputer 105, error correction circuit 106 and DRAM
This is a CMOS integrated circuit in which 107 is integrated by a CMOS process into one chip. The DRAM 107
Is a separate chip from the viewpoint of cost, and RF amplifier 1
01, DSP102, DAC103, servo circuit 10
4. CM for the microcomputer 105 and the error correction circuit 106
The OS integrated circuit may be integrated into one chip and these may be sealed in the same package.

CD-ROM with optical pickup 110
The data recorded on the disc is converted into RF signal,
It is output to the RF amplifier 101. The RF amplifier 101 is
The input R is configured similarly to the RF amplifier shown in FIG.
From the F signal, the focus error signal, the tracking error signal, and the reproduction signal (EFM (Eight
to Fourteen Modulation) signal) etc., and DSP1
Output to 02.

The DSP 102 and the servo circuit 104 are
A control signal for controlling the optical pickup 110 is created from the focus error signal, the tracking error signal, etc., and is output to the drive circuit 120. Drive circuit 120
Is the optical pickup 110 according to the input control signal.
The optical pickup 110 is controlled so as to drive the actuator therein and reproduce a good RF signal.

The error correction circuit 106 includes a DRAM 107.
Is used for error correction of the reproduced data, and when reproducing the audio signal, the DAC 103 converts the reproduced data into an analog signal and outputs the analog signal.

The microcomputer 240 functions as a system controller for controlling the operation of the entire drive, transmits / receives data and the like to / from the DSP 102 and the like as necessary, and the CD-RO.
Various operations of the M drive are performed.

As described above, in the semiconductor integrated circuit 100 shown in FIG. 5, by using the area-saving and high-accuracy RF amplifier 101, the other blocks can be integrated into one chip by the CMOS process, which is small in size. It is possible to realize a high-performance 1-chip CMOS integrated circuit for CD-ROM.

In the above description, the circuit of the CD-ROM drive is described as an example, but the circuit to which the variable resistance circuit of the present invention is applied is not particularly limited to this example, and the area is saved and the accuracy is high. Can be similarly applied to various circuits required to obtain the same effect.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a variable resistance circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a switch shown in FIG.

FIG. 3 is a diagram showing an example of an operational amplifier circuit using the variable resistance circuit shown in FIG.

4 is a circuit diagram showing a configuration of a signal processing unit of a tracking system of an RF amplifier using the operational amplifier circuit shown in FIG.

5 is a block diagram showing a configuration of a semiconductor integrated circuit for a CD-ROM drive including the RF amplifier shown in FIG.

FIG. 6 is a block diagram showing a configuration of a semiconductor integrated circuit used in a conventional CD-ROM drive.

FIG. 7 is a circuit diagram showing a configuration of a conventional variable resistance circuit.

FIG. 8 is a circuit diagram showing a configuration of another conventional variable resistance circuit.

[Explanation of symbols]

S1 to S8 switches T1 to T8 resistance VT, VT11 to VT15 variable resistance circuit Si CMOS switch 1,11-18 Operational amplifier 100 semiconductor integrated circuit 101 RF amplifier 102 DSP 103 DAC 104 Servo circuit 105 Microcomputer 106 error correction circuit 107 DRAM

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-10-215179 (JP, A) JP-A-61-242405 (JP, A) JP-A-9-326654 (JP, A) JP-A-7- 202704 (JP, A) JP-A-2-69973 (JP, A) US Patent 5736896 (US, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03H 11/24 H03H 7/25 G11B 7/005 H03F 3/08

Claims (7)

(57) [Claims] 1. A resistance value of at least one resistor is different, N (N is an integer of 2 or more) resistances connected in series, and N resistances connected in parallel to each of the N resistances. A variable resistance circuit comprising a switch and changing the resistance value by turning on / off the N switches, wherein the resistance value of each parasitic resistance of the N switches when turned on is A variable resistance circuit characterized in that a switch has a positive correlation proportional to or similar to the resistance value of resistors connected in parallel. 2. Each of the N switches includes a transistor connected in parallel to the resistor, and a gate width of the transistor is inversely proportional to or inversely proportional to a resistance value of a resistor to which the transistor is connected in parallel. The variable resistance circuit according to claim 1, wherein the variable resistance circuit has a negative correlation similar to proportionality. 3. The resistance value of each of the N resistors is R × 2 ⁱ
(Ω) (i is an integer of 0 to (N-1)), and the resistance value of each parasitic resistance of the N switches is r × 2 ^i.
It is set to (Ω).
The variable resistance circuit described. 4. The variable resistance circuit according to claim 1, wherein the switch is a CMOS switch. 5. A variable resistance circuit according to claim 1, and an operational amplifier which is connected to the variable resistance circuit and changes an amplification factor according to a resistance value of the variable resistance circuit. An operational amplifier circuit characterized by. 6. The variable resistance circuit is connected to an input terminal of the operational amplifier, and a resistance having the largest resistance value among the N resistances is connected to the input terminal. The described operational amplifier circuit. 7. An amplifier circuit including the operational amplifier circuit according to claim 5 or 6, further comprising an amplifier circuit for amplifying an output signal from an optical pickup, wherein the amplifier circuit and other circuits are formed as one chip by a CMOS integrated circuit. And a semiconductor integrated circuit.