JP3366208B2 - Semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit composed of fine MOS transistors, and more particularly to a circuit suitable for high speed / low power operation.

[0002]

[Prior Art] 1989 International Symposium OMBLS Technology, Systems and Applications, Proceedings of Technical Papers (198
May 9) pp. 188 to 192 (1989 In)
international Symposium on
VLSI Technology, Systems
and Applications, Proceed
ings of Technical Papers,
pp. As described in 188-192 (May 1989)), the breakdown voltage of a MOS transistor decreases as it is miniaturized, so the operating voltage must be lowered.

In this case, in order to maintain high-speed operation, it is necessary to reduce the threshold voltage (VT) of the MOS transistor in proportion to the decrease in operating voltage. This is because the operating speed is controlled by the effective gate voltage of the MOS transistor, that is, the value obtained by subtracting VT from the operating voltage, and the higher this value, the higher the speed. However, if VT is 0.
When the voltage is set to about 4 V or less, as described below, due to the subthreshold characteristic (tailing characteristic) of the MOS transistor, the transistor can no longer be completely turned off, and a phenomenon occurs in which a direct current flows.

The conventional CMOS inverter shown in FIG. 6 will be described. Ideally, when the input signal IN is at low level (= VSS), the N-channel MOS transistor MN
Is off and IN is at a high level (= VCC), the P-channel MOS transistor MP is off, and no current flows in any case. However, when the VT of the MOS transistor becomes low, the subthreshold characteristic cannot be ignored.

As shown in FIG. 7, the drain current IDS in the subthreshold region is proportional to the exponential function of the gate-source voltage VGS and is represented by the following equation.

[0006]

[Equation 1]

Where W is the channel width of the MOS transistor, I0 and W0 are the current value and channel width when defining VT, and S is the tailing coefficient (VGS-log ID).
It is the reciprocal of the slope of the S characteristic. Therefore, VGS = 0
But subthreshold current

[0008]

[Equation 2]

Flows. Since the transistor in the off state in the CMOS inverter of FIG. 6 has VGS = 0, the above current IL flows from the high power supply voltage VCC toward the low power supply voltage VSS, which is the ground potential, when not operating.

As shown in FIG. 7, this subthreshold current increases exponentially from IL to IL 'when the threshold voltage is lowered from VT to VT'.

As is clear from the above equation of the equation (2), in order to reduce the subthreshold current, VT should be increased or S should be decreased. However, the former causes a decrease in speed due to a decrease in effective gate voltage. In particular, from the viewpoint of breakdown voltage, if the operating voltage is lowered along with the miniaturization, the speed decrease becomes remarkable, and the advantage of miniaturization cannot be utilized, which is not preferable. In addition, the latter is difficult for the following reasons as long as it is assumed to operate at room temperature.

The tailing coefficient S is expressed as follows by the capacitance COX of the gate insulating film and the capacitance CD of the depletion layer under the gate.

[0013]

[Equation 3]

Here, k is the Boltzmann constant, T is the absolute temperature, and q is the elementary charge. As is clear from the above equation, CO
S ≧ kT ln 10 regardless of whether X or CD
/ Q, and it is difficult to set it to 60 mV or less at room temperature.

Due to the above-mentioned phenomenon, the substantial direct current of the semiconductor integrated circuit composed of a large number of MOS transistors remarkably increases. Especially at high temperature operation, V
This problem is exacerbated because T is low and S is large. In the future downsizing era of computers and the like where low power consumption is important, the increase of the subthreshold current is an essential problem.

This problem will be further described using a memory which is a typical semiconductor integrated circuit. As shown in FIG. 8, the memory has an X decoder (XDEC) and a word driver (WDE) for selecting and driving a row line (word line W) in order to select an arbitrary memory cell MC in the memory array MA.
D) and a sense amplifier (SA) that amplifies the signal on the column line (data line D), a sense amplifier drive circuit (SAD) that drives the sense amplifier, and a Y decoder (YDEC) that selects the column line. Further, a peripheral circuit (PR) for controlling these circuits is incorporated. The main part of these circuits has a circuit configuration based on the above-described CMOS logic circuit in order to reduce power consumption during operation, standby, or battery backup. However, the threshold voltage VT of the transistor (hereinafter, P for simplicity)
It is assumed that the absolute value of the MOS transistor is equal to that of the NMOS transistor and that it is VT. ) Decreases, the shoot-through current increases sharply for the above reason. This becomes particularly noticeable in the decoder and driver or the peripheral circuit section. This is because the number of circuits that make up these is overwhelmingly large and has a special function.

For example, regarding a decoder and a driver, a small number of specific circuits are selected and driven from a large number of circuits of the same type by an address signal. If VT is large enough, many non-selection circuits are completely selected and driven. Generally, as the storage capacity of the memory increases, the number of decoders and drivers increases, but unless the through current flows through the non-selection circuit, the total current does not increase even if the storage capacity increases. However, this is possible only when VT is large, and when it is low as described above, the shoot-through current increases drastically. Similarly, when the entire chip is unselected (standby state), most circuits in the chip could be turned off in the past to minimize the power supply current, but this is no longer possible. This problem is not limited to memory and is common to all semiconductor integrated circuits based on CMOS logic circuits.

Patent applications relating to shoot-through current include JP-A-60-167523 and JP-A-5-1081.
94, JP-A-5-210976, and JP-A-6-298.
34, JP-A-5-268065, and JP-A-5-291.
929, JP-A-5-347550, and JP-A-6-53.
496, JP-A-6-120439 and the like.

[0019]

The object of the present invention is to provide an MO.
To provide a high-speed and low-power semiconductor device even if the S transistor is miniaturized, and particularly to reduce a through current of a word driver, a decoder, a sense amplifier driving circuit, etc. which is a problem in a memory or a semiconductor device having a built-in memory. is there.

[0020]

In order to achieve the above object, according to the present invention, referring to FIGS. 10 and 8, a plurality of row lines (W) and a plurality of column lines intersecting the plurality of row lines are provided. (D),
A large number of memory cells arranged at desired intersections of the plurality of row lines and the plurality of column lines (the MC being completely cut, that is, the through current is substantially zero, MC); Selection circuit (XDEC, YDEC) for selecting
In a semiconductor integrated device (chip) having: a first operating voltage (VSS) is supplied to the selection circuit.
And a second node, third and fourth nodes supplied with a second operating voltage (VCC), and a first logic connected between the first node and the third node. A gate group (NAND), a second logic gate group (INV) connected between the second node and the fourth node,
A first current limiting means connected between the first logic gate group and the first node, and a second current limiting means connected between the second logic gate group and the fourth node. Current limiting means, each output of the first logic gate group is connected to each input of the second logic gate group, and in a first state, at least the first logic gate group One logic gate forms a first current path between its output and the first node via the first current limiting means, and at least one logic gate of the second logic gate group. Forms a second current path between its output and the fourth node via the second current limiting means, and in the second state, each logic gate of the first logic gate group is Form a third current path between its output and the third node Both first between each logic gate of said second logic gate group and the output and the second node 4
Current path of the first current limiting means and the first current limiting means is connected to the first node and the first current limiting means more than in the first state.
And the second current limiting means limits the current allowable amount of the current flowing between the first and second logic gate groups.
The allowable current amount of the current flowing between the fourth node and the second logic gate group is limited to be smaller than that in the state of (4).

[0021]

Even if the threshold voltage of the transistor is low, it is possible to minimize the shoot-through current flowing in the circuit when it is not selected.

[0022]

1 shows an example in which the present invention is applied to a word driver (WD in FIG. 8) of a dynamic random access memory (DRAM). Taking the state after the word line is selected as an example, in the conventional circuit (a), VT
Is high enough that all CMOS drivers have no shoot-through current. However, when VT becomes low,
Through current flows through the word driver, and this size cannot be ignored as the capacity increases (m · n large).
The total IA of this through current is

[0023]

[Equation 4]

Can be expressed as Here, VT is a threshold voltage defined by the current value I0 as shown in FIG. 2, and S is a tailing coefficient. Since the word driver power supply VCH is supplied by boosting the external power supply inside the chip, it has a limited current drive capability and cannot be processed when IA increases.

On the other hand, the features of the hierarchical feed line system (b) of the present invention are the following two points. (1) Hierarchical power supply line in which drivers are divided into blocks: m blocks each including n word drivers are provided, and the power supply lines P1 to Pm of each block are connected to the power supply line P via block selection transistors Q1 to Qm. Connect to. Furthermore, P
Is connected to the power supply line of the word voltage VCH via the transistor Q which selects the operation mode and the standby mode. (2)
Hierarchical gate width setting: The gate width (a · W) of the block selection transistor is selected sufficiently smaller than the total gate width (n · W) of the word driver transistors in the block (a << n). Also, the gate width of Q (b
W) is the sum of gate widths of all block transistors (m
・ Select sufficiently smaller than a ・ W) (b << m ・
a).

During operation, Q and Q1 are turned on to supply VCH to the power supply line (P1) corresponding to the block (B1) including the selected word driver (# 1). Here, assuming that the VT of all transistors is the same low value,
With this configuration, the through current of each of the unselected blocks (B2 to Bm) becomes equal to the subthreshold current of one corresponding block selection transistor (Q2 to Qm). Because the subthreshold current is proportional to the gate width of the transistor, even if a current of n.multidot.i tries to flow, the entire through current eventually becomes the subthreshold current (a.i) of the block selection transistor.
Because it is limited to. At that time, the voltage of the power supply lines P2 to Pm of the non-selected block is lowered by ΔV almost in the standby state. Because, Q2-Q which charges P2-Pm
This is because the subthreshold current of m is relatively small. Therefore, the total through current IA is almost (n + m · a) i as shown in Table 1. In order to reduce IA, n and (m · a) should be set to the same value.
Here, if a is set to about 4, the influence on the speed of the series transistor (Q, Q1) and the chip area can be reduced.

During standby, all of Q and Q1 to Qm are turned off. The total through current IS becomes equal to the Q subthreshold current, which is a / m
It can be reduced by n. The voltage of the power supply line of the block is m
Δ determined by the ratio of n · W and a · W and the tailing coefficient
Only V drops from VCH.

[0028]

[Table 1]

FIG. 3 is a schematic diagram of operation waveforms. During standby (Φ, Φ1 to Φm: VCH), Q and Q1 to Qm are almost off, so P is a voltage VCH-ΔV ′ lower than VCH, and P1 to Pm are Is even lower voltage. All word lines are fixed to VSS regardless of the voltages of P1 to Pm. When the external clock signal / RAS (here "/" indicates a bar signal) is turned on, first, Q is turned on by Φ,
The parasitic capacitance C of P is charged to VCH for t1 hour. next,
At Φ1, Q1 is turned on, and the parasitic capacitance C1 of P1 is charged to VCH for t2 hours. At this time, Q2 to Qm remain almost off. After that, the X decoder output signal X1
Thus, the word driver # 1 is selected and the word line is driven. When / RAS turns off, Q and Q1 turn off. P and P1 become VCH-ΔV 'and VCH-ΔV, respectively, after a long time elapses due to the mechanism described above.
Here, the power supply line (P,
P1) can be charged to VCH. This is because even if C is large, ΔV ′ is as small as several hundred mV, and moreover, the charging time (t1) of P can be sufficient immediately after / RAS is turned on. In addition, since C1 is relatively small because it is divided into blocks, the charging time (t2) of P1 can be shortened.

By applying the hierarchical feed line to the decoder as well, the through current can be greatly reduced.

FIGS. 4 and 5 show a hierarchical feed line system applied to a sense amplifier drive circuit (SAD in FIG. 8) and 1
The essential part of the memory array by the memory cell which consists of one transistor and one capacitor is shown. Well-known VC
Since the C / 2 precharge system is used, this sense amplifier drive circuit operates mainly at VCC / 2. Therefore, the feature is that the hierarchical feeders are used for both VCC and VSS. Here, the PMOS transistor QP
And the conductance of the NMOS transistor QN are equal. CMOS sense amplifier (SA) in sub-array
The group is selectively driven by the corresponding sense amplifier drive circuit, but at this time, the current IA ′ flowing through the power supply lines VCC and VSS.
Are dominated by the shoot-through currents of many non-selected drive circuits. For example, even if the gates of the transistors QP and QN in the figure are set to VCC and 0, respectively, to bring them into a non-selected state, since the sense amplifier drive lines CP and CN are VCC / 2, the subthreshold currents change from P′1 to P ″ 1. Flows to. To prevent this, application on both sides is essential. If the hierarchical feed line is applied only to VCC as described above, a subthreshold current of QN will newly flow from VCC / 2 to P ″ 1, which will cause a decrease in the level of VCC / 2. Because the VCC / built in the chip
This is because the current driving capability of the second supply circuit is small.

FIG. 9 shows the effect of applying the present invention to the word driver, the decoder and the sense amplifier drive circuit, assuming that the above-mentioned through current does not flow in the peripheral circuit (PR in FIG. 8) portion. 16 Gigabit DRAM is taken as an example. The parameter used there is a gate width of 5μ.
The threshold voltage VT defined by the voltage at which a current of 10 nA flows at m is -0.12 V and the tailing coefficient S is 97 mV / d.
ec. , Junction temperature T is 75 ° C., effective gate length Leff is 0.15 μm, gate oxide film thickness TOX is 4 nm, word voltage VCH is 1.75 V, power supply voltage VCC is 1 V, cycle time is 180 ns, and refresh cycle number is 12
8 k, chip size 23 mm × 45 mm, total capacity of data line charged / discharged in 1 cycle is 17 nF. According to the present invention, the operating current can be reduced from about 1.05 A of the related art to about 109 times, ie, 109 mA. This is because the shoot-through current can be significantly reduced from the conventional value of about 0.97 A to about 1/30 of 34 mA.

Although the present invention has been described with reference to the embodiments applied to the word driver and the sense amplifier driving circuit, the present invention is not limited to the embodiments described so far without departing from the gist of the present invention. Absent. A modified example of the present invention will be shown below.

FIG. 10 shows an example of a hierarchical power supply line system applied to a decoder. CM of NAND circuit and inverter
In an example in which the AND circuit is configured by two stages of the OS logic circuit, even if the circuit is not a circuit that operates around VCC / 2 like a sense amplifier drive circuit, a hierarchical feed line is provided on both sides of VCC and VSS. The feature is that it is used. The NAND circuits all output VCC during standby, and a small number output 0V during operation. Since the shoot-through current is determined by the NMOS transistor on the VSS side, a hierarchical feed line is used on the VSS side. On the contrary, the inverter outputs all 0V in the standby state, and a small number of outputs the VCC in operation. Through current is P
Since it is determined by the MOS transistor, a hierarchical feed line is used on the VCC side.

The present invention can be applied to any circuit group that outputs the same voltage during standby and operates a small number during operation. At that time, it is not necessary that all the circuits have the same transistor size, and the configurations may be different.

FIG. 11 shows another embodiment in which the present invention is applied to a word driver, and 16 of 2 mega word drivers are used.
An example is shown in which individual pieces operate simultaneously. This is an example in which the power supply line in the embodiment shown in FIG. 1 is received even if it is divided into a plurality of lines. A block is composed of 512 word drivers, and
12 blocks (B1,1 to B1,256, B2,1
~ B2,256) 8 sectors (S1 to S8)
Is provided. Within each sector, two blocks (eg B1,1 and B2,1) share a feed line (eg P1). The power feed lines P1 to P256 are fed through the block selection transistors Q1 to Q256 by 128 power feed lines P each.
Connect to L and PR. The power supply lines PL and PR are common to eight sectors. In addition, PL and PR are connected to transistor Q
It is connected to the feed line of VCH via L and QR. Q1
The gate width of Q256 is selected to be sufficiently smaller than the total gate width of the transistors of the word drivers in the two blocks, that is, 1 kilo word driver. Further, the gate widths of QL and QR are selected to be sufficiently smaller than the total gate width of the block selection transistors connected to the power supply lines PL and PR, that is, (8 × 128) block selection transistors. In operation,
Eight sectors perform the same operation. For example, QL, QR and Q1 in each sector are turned on, and two blocks (B1,1 and B2,1) including the selected word driver (# 1) are turned on.
Supply VCH to. The through current is the same as that when m is 256 and n is 4 km in the embodiment shown in FIG. In this way, when a plurality of circuits operate simultaneously, a plurality of blocks may be selected at the same time. Further, by dividing and arranging a plurality of transistors that operate as switches, the feeding line can be shortened to reduce the influence of wiring resistance, and the feeding line (P1) of the selected block can be charged in a short time.

FIG. 12 shows an embodiment in which the present invention is applied to an NMOS driver. The feature is that a hierarchical feed line is used on the drain side of the transistor. Each driver is a push-pull circuit composed of two NMOS transistors. The unselected driver outputs 0V, and the selected driver outputs VCC-VT. By using the hierarchical feed line on the drain side of the transistor, that is, on the VCC side, the shoot-through current can be reduced as in the embodiment shown in FIG. 1 without changing the output of the non-selected driver. For example, as shown in FIG. 12, when the block selection transistors Q2 to Qm are off, even if the influence of the drain voltage on the subthreshold current is small, P2 to Pm
The voltage on the word driver drops significantly, and no current flows through the word driver transistor. Thus, the present invention is a CMOS
It can also be applied to other logic circuits.

In the above description, the connection of the transistor substrate was not mentioned, but in any of the embodiments,
It is desirable to connect to a power supply. In that case, the charge required for charging the power supply line is smaller and the charging time is shorter than when the substrate is also connected to the power supply line connecting the drain. For example, in the embodiment shown in FIG. 1, by connecting all substrates of PMOS transistors to VCH,
As described above, the power supply line of the non-selected block is ΔV from VCH.
The threshold voltage of the PMOS transistor in the non-selected block becomes high due to the substrate bias effect. Since the source has a lower voltage than the gate and the threshold voltage is higher, the same current reduction effect can be obtained with a smaller ΔV as compared with the case where the substrate has the same voltage as the drain.

Although the threshold voltages of the transistors are all the same, the through current can be further reduced by making the threshold voltage of the transistor used as the switch higher than that of the other transistors. For example, Q in FIG.
By setting the threshold voltage of Q1 to Qm higher than that of the transistors in the word driver and selecting a and b large, it is possible to further reduce the through current while preventing the deterioration of the operating speed due to the on resistance of the switch. This is because the off-threshold current is affected exponentially, while the on-resistance is affected only by a linear function. Even if the gate capacitance increases with the gate width,
If the charging times t1 and t2 can be ensured, there is no problem in terms of operating speed. Also, in terms of layout area, there is no problem because the number is relatively small. In some cases, using a transistor having a high threshold voltage only for Q is effective in reducing the standby current.

In the timing diagram shown in FIG. 3, / RAS
During the active period when 0V is 0V, Φ and Φ1 are kept low and Q and Q1 are kept on. this is,
This is realized by controlling Φ by a signal generated by / RAS that designates an active mode and a standby operation mode, and by controlling Φ1 by a combined signal of the signal and the address signal. Further, it is possible to turn off Q and Q1 by setting Φ and Φ1 to VCH after driving the word line by using a signal that specifies the period from the fall of / RAS to the end of driving the word line. . As a result, the through current after driving the word line is
It can be reduced to the same level as. This effect is greater as the active period in which / RAS is 0V is longer. However, in this case, in order to rewrite the memory cell, it is necessary to lower Φ and Φ1 and turn on Q and Q1 for a certain period from the rise of / RAS. For example, also in the embodiment applied to the decoder shown in FIG. 10, it is possible to further reduce the shoot-through current after the output is determined.

The present invention can be applied not only to DRAMs but also to memories such as static random access memories (SRAMs) and read only memories (ROMs) and logic LSIs with built-in memories. According to the present invention, the smaller the threshold voltage is, the greater the effect is, and the threshold voltage is 0.2 V in which the through current becomes dominant in the operating current.
The effect is remarkable in the LSIs of the order of magnitude or less. When the operating voltage is about 2 V or less, a threshold voltage of such a degree is required from the viewpoint of operating speed, or when the gate length is about 0.2 μm or less, such a threshold voltage is obtained according to the scaling rule, so that the effect is particularly large.

[0042]

As is apparent from the embodiments described above,
According to the present invention, a through current can be reduced without impairing the operation speed, and a semiconductor device that operates at high speed with low power consumption can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment applied to a word driver.

FIG. 2 is a diagram showing operating points of PMOS transistors of a word driver.

3 is an operation timing chart of the embodiment shown in FIG.

FIG. 4 is a diagram showing an embodiment applied to a sense amplifier drive circuit.

FIG. 5 is a diagram showing a configuration example of a main part of a memory array.

FIG. 6 is a circuit diagram of a conventional CMOS inverter.

FIG. 7 is a diagram showing a subthreshold characteristic of a transistor.

FIG. 8 is a block diagram of a memory.

FIG. 9 is a diagram showing an effect of the present invention.

FIG. 10 shows an embodiment applied to a decoder.

FIG. 11 is another embodiment applied to a word driver.

FIG. 12 is a diagram showing an embodiment applied to an NMOS driver.

[Explanation of symbols]

WD ... Word driver, W ... Word line, XDEC ... X decoder, D ... Data line, SA ... Sense amplifier, YDEC
... Y decoder, SAD ... Sense amplifier drive circuit, CN,
CP ... Sense amplifier drive line, MC ... Memory cell, MA ...
Memory array, PR ... Peripheral circuit, VCH ... Word voltage,
VCC ... Power supply voltage, VSS ... Ground voltage (0V), m,
m '... number of blocks, n ... number of circuits in block, B1 to B
m, B'1 'to B'm' ... Block, P1 to Pm, P '
1'-P'm ', P "1'-P"m' ... Block feed lines, Q1-Qm, Q'1'-Q'm ', Q "1'-Q"
m '... block selection transistor, P, P', P "... second feed line, Q, Q ', Q" ... Transistor for selecting operation mode and atmospheric mode.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-6-29834 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 11/40-11/4197

Claims (11)

(57) [Claims] 1. A plurality of row lines, a plurality of column lines intersecting the plurality of row lines, and a plurality of memory cells arranged at desired intersections of the plurality of row lines and the plurality of column lines. In a semiconductor integrated device having a selection circuit for selecting the memory cell, the selection circuit is supplied with first and second nodes to which a first operating voltage is supplied and a second operating voltage. Third and fourth nodes, a first logic gate group connected between the first node and the third node, and between the second node and the fourth node A second group of logic gates connected to each other and between the first node and the third node.
And a third logic gate group connected between the second node and the fourth node.
A fourth logic gate group, first current limiting means connected between the first logic gate group and the first node, the second logic gate group and the fourth node Second current limiting means connected between the third logic gate group and the first node.
The connected third current limiting means is connected between the fourth logic gate group and the fourth node.
A fourth current limiting means connected to each other, each output of the first logic gate group is connected to each input of the second logic gate group, and each output of the third logic gate group. Is the fourth logic game
In the first state, at least one logic gate of the first logic gate group includes the first current limiting means between its output and the first node. To form a first current path via the second current limiting means, and at least one logic gate of the second logic gate group forms a second current limiting means between its output and the fourth node. In the second state, each logic gate of the first logic gate group forms a third current path between its output and the third node, and at the same time, in the second state. Each logic gate of the logic gate group forms a fourth current path between its output and the second node, and the first current limiting means sets the fourth current path more than that in the first state. Current flowing between the first node and the first logic gate group And the second current limiting means limits the current allowance of the current flowing between the fourth node and the second logic gate group more than in the first state. It is limited to a small value, and in the third state, at least the third logic gate group
One logic gate is between its output and the first node
To form a fifth current path through the third current limiting means.
And at least the fourth logic gate group
One logic gate is between its output and the fourth node
To form a sixth current path through the fourth current limiting means.
In the fourth state, each logic gate of the third logic gate group is
Has a seventh current path between its output and the third node.
Forming a path and forming each logic of the fourth logic gate group
The gate has an eighth electric current between its output and the second node.
Forming a flow path, and the third current limiting means is
The above-mentioned first node and the above-mentioned third theory than in the case of the third state
Control the current allowance of the current flowing between
And the fourth current limiting means is the same as the third state.
The fourth node and the fourth logic gate as compared with the state
The current permissible amount of the current flowing to and from the group is limited to a small value, and when the first and second logic gate groups are in the first state, the third and fourth logic gate groups are in the fourth state. in <br/> Ah is, the third and fourth logic gate group is the third state of
At this time, the first and second logic gate groups are set to the second
The semiconductor integrated circuit is characterized in that 2. The semiconductor integrated circuit according to claim 1, wherein the first operating voltage is supplied to the first node.
A power supply line, and a second line for supplying the second operating voltage to the fourth node
A power supply line; a first main current limiting means provided between the first power supply line and the first node; a second main power supply line provided between the second power supply line and the fourth node; 2 main current limiting means, and in the first state or the third state, the first operating voltage is supplied to the first node through the first main current limiting means. The semiconductor integrated circuit is characterized in that the second operating voltage is supplied to the fourth node through the second main current limiting means. 3. The semiconductor integrated circuit according to claim 1, wherein the first current limiting means has a source connected to the first node and a drain connected to the first logic gate group. A second MOS transistor having a source connected to the fourth node and a drain connected to the second logic gate group. Integrated semiconductor circuit. 4. The semiconductor integrated circuit according to claim 3, wherein the absolute value of the threshold voltage of the first MOS transistor and the absolute value of the threshold voltage of the second MOS transistor are the same as those of the first integrated circuit. And greater than the absolute value of the threshold voltage of the MOS transistor included in each of the second logic gate group, where the threshold voltage is the ratio of the gate width to the effective gate length (effective gate width / effective gate width). A semiconductor integrated circuit characterized by a constant current threshold voltage defined by a gate-source voltage at which a drain current of 10 nA flows when the gate length) is 5 / 0.15. 5. The semiconductor integrated circuit according to claim 3, wherein the first MOS transistor and the second MOS transistor have complementary polarities. 6. The semiconductor integrated circuit according to claim 1, wherein each of the first and second logic gates is composed of a CMOS logic gate. 7. The semiconductor integrated circuit according to claim 6, the semiconductor integrated circuit, wherein said first logic gate is a multi-input first output. 8. The semiconductor integrated circuit according to claim 7, wherein the first logic gate is a NAND gate. 9. The semiconductor integrated circuit according to claim 6, wherein the second logic gate is an inverter. 10. The semiconductor integrated circuit according to claim 1, wherein each of the first logic gate and the second logic gate has a gate voltage from a first voltage to a second voltage. , The drain current becomes larger when the gate voltage is the second voltage than when the gate voltage is the first voltage, and the gate voltage is the first voltage. A semiconductor integrated circuit including a MOS transistor in which a subthreshold current flows between a drain and a source at any time. 11. The semiconductor integrated circuit according to claim 3, wherein in the third current limiting means, a source is connected to the first node and a drain is connected to the third logic gate group. The fourth current limiting means has a fourth MOS transistor having a source connected to the fourth node and a drain connected to the fourth logic gate group; In the state, the first MOS transistor and the second MOS transistor are on, and the third MOS transistor and the fourth MOS transistor are off. In the third state, the first MOS transistor and the first MOS transistor are off. The MOS transistor and the second MOS transistor are off, and the third MOS transistor and the fourth MOS transistor are on. Semiconductor integrated circuit.