JP3252826B2 - Circuit pattern defect inspection method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern to be inspected (circuit pattern) such as an LSI wafer and the like.
The present invention relates to a circuit pattern defect detection method for automatically detecting a defect such as a foreign matter or a discoloration defect, and an apparatus therefor.

[0002]

2. Description of the Related Art Integrated circuits such as LSIs tend to be highly integrated and miniaturized. In the formation of such a fine wiring pattern, the detection of a defect is important in determining the quality of the formation.

[0003] Since the detection of defects is no longer visually observable, there is an urgent need for automation of defect detection, rather than the stage of visual inspection with a large number of personnel.

Therefore, after converting image information on the surface of a semiconductor element obtained from an optical microscope or an electron microscope into an electric signal by an image pickup tube or an image pickup device, a predetermined signal processing is performed to detect a defect. Devices are known.
For example, Semiconductor World (June 1984)
Pages 112 to 119 (Semiconductor World (198
4) pp112-119) or JP-A-59-192943.

The components common to these technologies are shown in FIG.
4 will be briefly described. In FIG. 14, lamp 2
The circuit pattern on the wafer 1 illuminated by the above is enlarged and detected by the image sensor 4 via the objective lens 3, and an image of the previous chip 7 a (adjacent chip) stored in the image memory 5 with a grayscale image of the circuit pattern And a defect determination is performed.
The detected image is simultaneously stored in the image memory 5 (stored image) and used for the comparative inspection of the next chip 7b.

FIG. 15 shows an example of defect determination. In the alignment circuit 6a, the detected image and the stored image are aligned,
The difference image between the detected image and the stored image aligned by the difference image detection circuit 6b is detected. This is binarized by the binarization circuit 6c to detect a defect. With the above configuration, the chip 8a existing in the detected image is detected.

[0007]

However, as the miniaturization of LSIs has advanced and the era of submicron LSIs has entered, it is becoming difficult to detect minute defects with these conventional techniques.

[0008] In the future, further miniaturization and multi-layering will be advanced, and it is expected that conventional techniques alone cannot cope with detecting a defect of 0.1 to 0.3 μm in a complicated and fine multi-layer pattern with high reliability. You.

It is an object of the present invention to detect a three-dimensional shape difference, such as the thickness of a pattern to be inspected (circuit pattern) and the degree of edge droop, a shift between layers, or a sampling error at the time of detection as a defect. Without detecting, only true defects can be detected with high reliability and high accuracy, and it is possible to sufficiently cope with miniaturization and multi-layering of LSI.
It is an object of the present invention to provide a circuit pattern defect detection method and apparatus capable of detecting minute defects of up to 0.3 μm.

Another object of the present invention is to provide a circuit pattern defect detection method and apparatus which can automatically set the defect detection sensitivity according to the state of the shape of the pattern to be inspected. .

It is another object of the present invention to provide a circuit pattern defect detection method and apparatus capable of accurately detecting a defect size.

[0012]

In order to achieve the above-mentioned object, according to the present invention, a plurality of circuit patterns to be inspected, which are originally formed to be identical, are sequentially imaged. In the method of inspecting a defect of a circuit pattern to be inspected using an image, a filtering process is performed on at least one of two images obtained by sequentially capturing the circuit pattern to be inspected, thereby performing a filtering process on the two images. The state of the positional shift is changed, and the filtering process is performed to detect a defect of the pattern to-be-inspected using two images in which the state of the positional shift is changed.

Further, according to the present invention, a plurality of circuit patterns to be inspected which are originally formed to be identical are sequentially imaged,
In the method of changing the state of the positional shift between the two images obtained by sequentially capturing images and comparing the two images with the changed state of the positional shift to inspect the defect of the circuit pattern to be inspected, When a defect is detected by comparing the two images having the changed patterns, the detection sensitivity is changed between the edge part of the circuit pattern to be inspected and the other part to detect the defect, or the defect of the circuit pattern to be inspected is detected. It is characterized in that the detection sensitivity of the defect is changed according to the state.

Further, according to the present invention, a defect of a pattern to be inspected is inspected by using an image of the circuit pattern to be inspected obtained by sequentially imaging a plurality of circuit patterns to be inspected which are originally formed to be the same. Image capturing means for capturing an image of a circuit pattern to be inspected to obtain an image of the circuit pattern to be inspected, storage means for storing images sequentially captured by the image capturing means, and an image obtained by the image capturing means Filtering means for performing a filtering process on at least one of the image stored in the storage means and the image, and changing the state of the positional shift between the two images. Defect detecting means for detecting a defect in the pattern to-be-inspected using the image.

[0015]

With the above arrangement, even if the shape of the grayscale waveform of the detected image is considerably different in the normal part, it is possible to detect a fine defect, thereby obtaining a change in the grayscale fluctuation of the circuit pattern and a difference in edge droop. In addition, no misalignment between layers or a sampling error upon detection is detected. Further, since the alignment accuracy can be improved, it is possible to detect even finer defects. Further, not only the shape defect of the circuit pattern but also the discoloration can be detected without overlooking. Furthermore, not only the presence / absence of a defect but also its size can be accurately detected.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the embodiments shown in the drawings. First, the principle of the present invention will be described with reference to FIG. That is, the detected grayscale image signal f obtained by detecting the circuit pattern at the position 7d inside the chip 7 on the wafer by the photoelectric converter 4, and the circuit pattern at the position 7c corresponding to the adjacent chip on the wafer, for example, The defect is detected by comparing the gray scale image signal g stored in the image memory 5 detected in the above with the following as follows.

(1) The grayscale image signals f and g are first-order differentiated by the first-order differentiating circuits 10a and 10b, respectively, and the polarity of the first-order differentiation obtained from the subtractors 22a to 22h, that is, positive or negative. Circuits 12a and 12b and polarity comparison circuits 14a to 14a
In step 14y, the images are compared for each image, and the mismatch is detected as a defect.

(2) Primary differentiating circuits 10a and 10b (FIG. 6)
The details are shown below. ) At the time of the first differentiation, the binarization circuit 23a
The absolute value of the first derivative obtained from the subtractors 22a to 22h is different from that of the two image signals, or only the pixels of which the absolute value is larger than the set value Eth. Is detected as a defect.

(3) The grayscale image signals f and g are secondarily differentiated by the second-order differentiating circuits 11a and 11b, and are binarized by the threshold value Dth.
Based on the output signals a, 12b, 13a, and 13b, the above-mentioned (2) is performed only in one area to detect the polarity mismatch as a defect.

(4) As shown in FIG. 12, the grayscale image signals f and g are secondarily differentiated by the second differentiating circuits 11a and 11b and binarized by a threshold value Dth. 2) is performed, the polarity mismatch is detected as a defect from the AND circuit 19, and the values of the grayscale signals f and g are compared in the other area (non-edge area) or all areas, and the difference is minimized by binarizing the difference image signal. The value detection circuit 44 detects the mismatch as a defect.

(5) A low threshold value is set in the non-coincidence area obtained by any of the above (2) and (3), and a high threshold value is set in other areas, and the difference image signal between the grayscale image signals f and g is set. Detects defects by binarization.

(6) The two grayscale images f and g are aligned so that the number of mismatched pixels obtained by any of (2) and (3) is minimized.

(7) The grayscale image signal is aligned at a plurality of positions where the number of mismatched pixels obtained by any of the above (2) and (3) is equal to or less than a set value.

(8) The images are aligned at a plurality of positions obtained by the above (7), and the common inconsistency obtained by the comparison of any of the above (2) to (5) is detected as a defect.

(9) The number of mismatched pixels obtained by any of the above (2) and (3) is symmetrical with respect to misalignment around the minimum number of polarity mismatched pixels.
Alternatively, the grayscale image is filtered such that the numbers of the plurality of mismatched pixels are substantially equal.

Next, how the above technical means (1) to (9) operate will be described with reference to signal waveforms. That is,
The signal waveforms f ₁ and g ₁ shown in FIG. 18A for the two circuit patterns having shading differences as shown in FIGS. 16 (a), (b), (c) and (d) are converted to the above-mentioned means (1). ), That is, first-order differentiation is performed by the first-order differentiating circuits 10a and 10b, and f ₁ ′,
When g ₁ ′ is obtained and its polarity is plotted, the waveform shown in FIG. One bit (1,0) of 1, -1 is assigned from the subtracters 22a to 22h of the primary differentiating circuits 10a, 10b according to whether the polarity of the primary differentiation is positive or negative, and two polarity waveforms. FIG. 2C is obtained by comparing 1 and -1 as mismatch. Defect 8b can be detected as a mismatch, and the detected dimensions exactly match the actual dimensions of the defect. However, in the normal part, erroneous detection occurs due to a difference in the degree of droop of the circuit pattern edge or the like. Therefore, the means (2), that is, the primary differentiation f ₁ ', _{g 1'} absolute value of _{| f 1 '|, | g} 1' | for the, for the threshold _{Eth, | f 1 '| <} Eth or | g 1' | < when Eth is established, first-order differential When the polarities of f ₁ ′ and g ₁ ′ are forcibly set to 0, a polarity waveform shown in FIG. 19B is obtained. When these are compared, the same figure (c) is obtained, and the defect 8b
Only can be detected correctly. The above is min ｛| f ₁ ′ |, |
This is equivalent to performing a defect determination on an area where g ₁ ′ |｝ ≧ Eth holds, but max ｛| f ₁ ′ |, | g ₁ ′ |｝ ≧
Similar results are obtained with Eth. As described above, the defect can be detected by the means (2). However, depending on the inspection target, the signal waveforms f ₃ and g ₃ as shown in FIG. , (C), since the waveform shape of the bright portion is different, erroneous detection of the normal portion occurs. In normal bright-field illumination as shown in FIG. 14, the edge of the circuit pattern is observed to be dark. Therefore, by performing the above-described means (2) on the dark edge, the erroneous detection can be prevented. That is, as shown in FIGS. 21A to 21D, the means (3), that is, the second-order differentiating circuits 11a and 11d are used.
b, the second derivative of the signal waveforms f ₃ and g ₃ is calculated by using the threshold value Dth as 2
Digitizing (realizing an edge operator of 1, -2, 1 by the adder 26, the multiplier 27 and the adder 28, and binarizing the edge operator with a threshold value Dth set by the binarizing circuit 29)
f _3b and g _3b are obtained, and the logical sums f _3b and Ug _3b are obtained. This region R corresponds to the edge of the circuit pattern, and when the polarities of the first derivative are compared in this region, erroneous detection does not occur as shown in FIG.

According to the above (3), even if the shape of the signal waveform is considerably different, it is possible to accurately detect not only the presence / absence but also the size of the shape defect generated at the edge of the circuit pattern. As shown in a) and (b), when the film thicknesses of the circuit pattern F ₄ and the circuit pattern G ₄ are different from each other by more than an allowable limit, this can be detected as a defect.
In the region other than the edge region R by the means (4), the difference signal waveform | f ₄ − in FIG.
g ₄ | (the difference image detection circuit 43a shown in FIGS. 12 and 13)
(Obtained by .about.43y) with a threshold value Vth, it becomes possible to detect a defect as shown in FIG.

According to the means (5), a low threshold value is set in the mismatch area obtained by the means (3).
By setting a high threshold value in other areas and binarizing, circuit pattern edge defects can be detected to be strictly small as shape defects, and other than that, erroneous detection can be suppressed and some rough inspection can be performed. it can.

The number of inconsistent pixels obtained by the means (2) and (3) is the amount of displacement ΔX between the two images.
With respect to (図 Y), the shape is as shown in FIG. Therefore, according to the means (6), if the two images f and g are aligned by the cutout circuits 12a and 12b so that the number of mismatched pixels is minimized, a state where the circuit pattern edge positions in the images are correctly aligned can be obtained. realizable. The two images can be correctly aligned. If the comparison is performed by means (2) to (5) in a state where the two images are correctly aligned, highly accurate defect detection can be performed.

Here, as shown in FIGS. 24 (a) and 24 (b), when there is an interlayer shift, the number of unmatched pixels does not decrease at only one point, but at each pattern edge of the multilayer pattern. Are correctly aligned, the number of mismatched pixels is reduced at a plurality of points. Therefore, for example, FIG.
In, the two images f ₂ and g ₂ are aligned by the cut-out circuits 12a and 12b at ΔX = 0 that minimizes the number of mismatched pixels. 24A and 24B, the signal waveforms f ₂ and g ₂ of the AA ′ and BB ′ portions are as shown in FIG. 24C, and when the above-mentioned means (3) is applied, FIG. ), And an erroneous detection occurs in the interlayer displacement part. Next, if the number of unmatched pixels is the second smallest, two images f ₂ ,
the g ₂ to align. Applying means (3) to the signal waveform _{g 2} by one pixel shifted to the signal waveform _{f 2} and the left, FIG. (G), the (h). Then, as shown in FIG. 2I, AND of the determination result of △ X = 0 and the determination result of △ X = −1 is taken by the AND circuit 19, and when a common output mismatch is detected, the interlayer Only the defect can be correctly detected without being affected by the displacement.

The number of mismatched pixels is affected not only by the presence / absence of interlayer misalignment but also by minute irregularities of the circuit pattern, and the value varies depending on the object to be inspected. If the number of power points is determined, the sensitivity of defect detection can be automatically set according to the state of the circuit pattern.

According to the means (9), it is possible to arbitrarily change the state of the positional deviation by filtering the detected grayscale image. That is, the number of mismatched pixels is
If the shape shown in FIG.
FIG. 4B shows that two images can be registered.
If the shape is as shown in Figure 1, one image is exactly 1
/ 2 pixels. Therefore, in the case of (a), at the position where the number of mismatched pixels is minimized, here, △ X =
If the image is aligned with 0, defect determination with extremely high accuracy can be performed, and even a very small defect can be detected. In the case of (b), two points ΔX = 0, ΔX = −
If the image is aligned with 1, it is possible to realize a defect determination that allows a difference in the shape of the pattern of 1/2 pixel. Here, the above image filtering is

[0033]

(Equation 1)

The filter can be realized by convolving a filter having such coefficients with the image, and the coefficient aij (i, j = 1 to 3) is determined from the value of the number of mismatched pixels.

Next, an embodiment of the present invention will be described with reference to FIG. As the photoelectric converter 4 for converting an optical image of a pattern to be inspected (circuit pattern) into an electric signal, any device such as a linear image sensor or a TV camera can be used. In this embodiment, a linear image sensor is used.
The two-dimensional circuit pattern of the wafer 1 on which the pattern to be inspected is formed is detected by the self-scanning of the linear image sensor and the XY table 1A which moves in a direction perpendicular to the self-scanning. An analog signal (video signal) detected by the linear image sensor 4 is converted by the A / D converter 9 into, for example, 8
It is converted to a digital signal 8 of bits and the detected image signal f
Is compared with the signal (stored image signal) g of the immediately preceding chip stored in the image memory 5 to determine a defect.
That is, as shown in FIG. 2, the circuit pattern at the position 7d inside the chip 7 on the wafer is detected (detected image signal f), and this is stored in the image memory 5 and the circuit pattern at the position 7c corresponding to the adjacent chip is stored. The defect is detected by comparing with (stored image signal g).

First, in FIG. 1, for example, an 8-bit detected image signal f and a stored image signal g are sequentially subjected to primary differentiation and secondary differentiation by primary differentiation circuits 10a and 10b and secondary differentiation circuits 11a and 11b for each pixel. Differentiate. As shown in FIG. 3, the primary differentiating circuits 10a and 10b
× 3 pixels are sequentially cut out, and the first derivative o, p,.
... V and o ′, p ′,... V ′ are obtained, and their polarities (1, 0) and the values (1, 0) obtained by binarizing the absolute value of the first derivative are obtained. ), For example, 16bi
The signals 100a and 100b of t are output. Here, the polarity “1” represents positive, and “0” represents negative. Second derivative circuit 1
1a and 11b, as shown in FIG. 4, apply the operators 1, -2 and 1 to each picture element of the image, binarize them with a threshold value Dth, and set the dark area of the pattern edge to "1". The others are set to “0”, for example, 1-bit signals 101a, 1
Output as 01b. Next, the cutout circuits 12a, 1
2b, 13a, 13b, the primary differentiating circuit 10a, 1
0b and the outputs of the second-order differentiating circuits 11a and 11b are cut out. The cutout circuits 12a and 13a are, for example, 5 ×
A region of 5 pixels is cut out to create a state shifted by ± 2 pixels. The cutout circuits 12b and 13b synchronize with the central position of the 5 × 5 pixels. Next, the polarity comparison circuits 14a to 14a
4y, the cutout circuits 12a, 12b, 13a, 1
Using the output of 3b, the primary differential and secondary differential results of the detected image signal and the stored image signal shifted by ± 2 pixels are compared respectively. That is, in the dark region of the pattern edge extracted by the secondary differentiation, the polarity of the primary differentiation in eight directions (number) of the detected image signal and the stored image signal and the magnitude of its absolute value are compared for each direction. In any of the regions where the absolute value is large, a pixel whose polarity does not match is determined as a mismatch and a value “1” is output. Since the cutout circuits 12a and 12b have 25 outputs of, for example, 5 × 5 pixels, in this case, there are also 25 polarity comparison circuits 14a to 14y.

Next, the counter circuits 15a to 15y count the number of mismatched pixels obtained by the polarity comparison circuits 14a to 14y, for example, every 1024 pixels × 256 pixels. The displacement detection circuit 16 includes counter circuits 15a to 15a.
15y, the number of mismatched pixels obtained is analyzed, and the amount of misalignment (ΔX
₁ , △ Y ₁ ),... (△ Xm, △ Ym). This displacement amount is, for example, as shown in FIG.

Next, the outputs of the polarity comparison circuits 14a to 14y are delayed by the delay circuits 17a to 17y until the above-mentioned positional deviation amount is obtained. Then, the area selection circuit 18a
１８18y, the displacement amount (△ X ₁ , △ Y ₁ ),
····································· (Only active) the output of the polarity comparison circuit 16 at the position corresponding to (△ Xm, △ Ym), and mask the other. Then, the AND circuit 19 calculates the logical product of the outputs of the area selection circuits 18a to 18y to obtain the value "1".
Is output as a defect.

As will be described later, 19 is not necessarily
There is no need to use an AND circuit. Area selection circuits 18a-1
Similarly, 8y need not necessarily be an AND circuit.

Next, the components of each section will be described in more detail. FIG. 6 is a diagram illustrating a configuration example of the primary differentiating circuits 10a and 10b. From the 8-bit digital signal 8, shift registers 20a and 20b and latch 21a
To 21i, 3 × 3 pixel areas are cut out in the latches 21a to 21i. From the 3 × 3 pixels, the first derivative in the eight directions shown in FIG. 3 is calculated using the subtractors 22a to 22h. Here, the subtracter 22a corresponds to the first derivative o in FIG. 3, and the subtractor 22h corresponds to the first derivative u in FIG.
22h performs the first derivative ov shown in FIG.
Outputs a to 22h are 1-bit code bits, that is, positive,
The negative polarity (1, 0) and the absolute value of the remaining first derivative (|
f ′ | or | g ′ |) is 8 bits. As shown in FIG. 19B, the binarization circuits 23a to 23h calculate the absolute value of the first derivative by a predetermined threshold value Eth.
In a circuit for obtaining a binarized signal by binarizing, if the absolute value of the first derivative (| f '| or | g' |) is equal to or larger than the threshold value Eth, "1" is set, and if smaller than the threshold value Eth, "0" is set. That is, the 1-bit value (1, 1) obtained by binarizing the absolute value of the first derivative
0) is output. Note that this threshold Eth is (| f '| and |
g ′ |).
That is, the subtracters 22a to 22h and the binarization circuits 23a to 232
From 3h, eight signals indicating directions (directions) adjacent to each other and signals indicating absolute values of eight adjacent directions (directions) are combined and output as signals 100a and 100b in a 16-bit configuration.

FIG. 7 is a diagram showing a configuration example of the secondary differentiating circuits 11a and 11b. 8 bit digital signal 8
Shift registers 24a and 24b and latch 25
A region of 3 × 3 pixels is cut out to the latches 25a to 25i by using a to 25i. A binary edge pattern is extracted from the 3 × 3 pixels using the edge operator shown in FIG. That is, the adder 26, the multiplier 27 and the adder 28
To realize an edge operator of 1-2, 1 and binarize it with the threshold value Dth set by the binarization circuit 29.
As shown in FIGS. 21 (b) and 21 (c), the dark area of the pattern edge is set to "1", and the other areas are set to "0" and output as 1-bit signals 101a and 101b. The other three types of edge operators shown in FIG. 4 can be realized by the adder 26, the multiplier 27, and the adder 28 in the same manner. (The adder 26, the multiplier 27, and the adder 28 that perform the other three types of edge operators are omitted in FIG. 7.) FIG. 8 is a diagram illustrating a configuration example of the cutout circuits 12a and 12b. 16 bits output from the primary differentiating circuit 10a
Digital signal (combined signal of eight polarities (1, 0) and the absolute values (1, 0) of the eight primary derivatives) 100a
Shift registers 30a to 30d and latch 31
Using 5a to 31y, an area of 5 × 5 pixels is cut out in the latches 31a to 31y. Also, the 16-bit digital signal 100b (eight polarities (1, 0) and the absolute values of the eight primary differentials (1,
0), the shift registers 30e, 30
f, and outputs a pixel corresponding to the center pixel of the 5 × 5 pixels to the latch 32c using the latches 32a, 32b, and 32c. The cutout circuits 13a and 13b shown in FIG. 1 can be realized by a similar configuration. FIG. 9 shows an example. That is, 1 bit output from the secondary differentiating circuit 11a
From the binary signals (the signal (1, 0) indicating the edge area and the other area) 101a of the shift registers 33a to 33a
3d and the latch 34a using the latches 34a to 34y.
A region of 5 × 5 pixels is cut out to 34y. Also, a 1-bit binary signal 101 output from the secondary differentiating circuit 11b
b (the edge region, the signal (1,
0)), the shift registers 33e and 33f and the latches 35a, 35b and 35c
A pixel corresponding to the center pixel of the × 5 pixels is output.

FIG. 10 is a diagram showing a configuration example of the polarity comparison circuits 14a to 14y. In the figure, the comparison circuit 37a which validates the mismatch by the polarity comparison only in a region where the absolute value of the primary differential signal is large is a 16-bit signal 102, 104.
(Positive: 1, negative: 0)
1, negative: 0) is detected.
EXOR circuit 36 that outputs a signal that becomes "0" when they match.
a, the signals representing the magnitudes of the absolute values of the primary differential signals included in the 16-bit signals 102 and 104 are both (both)
The NAND circuit 36b and the NAND circuit 3 which output a "0" signal when the signal is small "0" and output a "1" signal otherwise.
When the output of 6b is "0", it comprises an AND circuit 36c which does not output the inconsistency of the polarity output as a signal of "1" from the EXOR circuit 36a. The OR circuit 38
The logical sum of the outputs of the individual (direction) comparison circuits 37a to 37h is calculated, and the absolute value of the primary differential signal is large from at least one of the eight comparison circuits 37a to 37h. When a mismatch is detected only in the region by the polarity comparison, this polarity mismatch signal is output. OR
The circuit 39 calculates the logical sum of the binarized edge pattern signals 103 and 105 output from the extraction circuits 13a and 13b, and outputs either the detected image signal f or the stored image signal g, that is, the extraction circuit 13a and the extraction circuit 13b. Signal "1" indicating that the edge pattern "1" signal has been detected
Is output. AND circuit 40 is OR circuit 3
The logical AND of the output of the OR circuit 39 and the output of the OR circuit 39 is obtained, and the polarity mismatch signal obtained in a region where the absolute value of the primary differential signal is large is output as a signal of "1" in the edge pattern.

[0043] With this configuration, as shown in FIG. 19, for the detection image signal f ₁ shown in the diagram (a) and the stored image signal g _1, the absolute value is large in the region (first derivative of the first order differential signal Value | f ₁ ′ | or | g ₁ ′ | <Eth, and the threshold value Eth is
Obviously, it is possible to vary between | f ₁ ′ | and | g ₁ ′ |. )), It is set to “0”, and the polarities (positive (1), negative (−1)) of the first derivative (f ₁ ′ org ₁ ′) in other regions (regions where the absolute value of the first derivative signal is small). )
FIG. 19B shows the polarity waveform of the first derivative converted into a signal. Then, comparison is made in a region where the absolute value of the primary differential signal is large (primary differential value | f ₁ ′ | or | g ₁ ′ | <Eth), and the polarity of the primary differential (f ₁ ′) (positive (1 ), Negative (-
1)) Compare the signal with the first derivative (g ₁ ') polarity (positive (1), negative (-1)) signal and find a mismatched (1 / -1) signal as shown in FIG. OR of circuits 14a to 14y
From the circuit 38, the determination result is obtained as shown in FIG. That is, in absolute value is larger region of the primary differential signal as a polarity mismatch for the detected image signal f ₁ and the stored image signal g _1, the polarity comparing circuit 14a~ shown in FIG. 10
The defect 8b is detected from the OR circuit 38 of 14y. However, as shown in FIG. 18, for the detection image signal f ₁ and the stored image signal g _1, simply by detecting defects 8b only polarity mismatch, as shown in FIG. 18, in the normal portion, the detected image signal polarity mismatch is detected in relation f ₁ and the stored image signal g ₁ by significant differences in the output image signal, erroneously detected as a defect. Therefore, in a region where the absolute value of the primary differential signal is large, the detected image signal f ₁
By detecting the polarity of the mismatch between the stored image signals g ₁ and, as shown in FIG. 19, there is no possible erroneous detection for the normal portion. Further, as shown in FIG. 20, with the miniaturization of the circuit pattern, at the center of the circuit pattern,
Detected image polarity mismatch relative to the signal f ₃ and the stored image signal g ₃ is detected, so that the normal portion is erroneously detected as a defect. Therefore, the detected image signal f ₃ and the stored image signal g ₃ shown in FIG.
The secondary differential signals f ₃ ″, g ₃ ″ (shown as secondary differentials in FIG. 21 (b)) are obtained by 1 a and 11 b, and the secondary differential signals f ₃ ″, g ₃ ″ are binary-coded with a threshold value Dth. (F _3b = f
₃ ″> Dth, g _3b = g ₃ ″> Dth) Edge signal 1
01a and 101b (shown in FIG. 21C as binarization of the second derivative), and the polarity comparison circuits 14a to 14b shown in FIG.
The OR circuit 39 of 14y detects OR (f _3b Ug _3b ) as to whether or not there is an edge signal in any direction (O in FIG. 21D).
Shown as R detection. ), An edge signal of a circuit pattern "1" is obtained. Then, the polarity comparison circuit 14a shown in FIG.
The signal "1" OR-detected by the OR circuits 39 to 14y and the defect signal due to the polarity mismatch detected from the OR circuits 38 of the polarity comparison circuits 14a to 14y are converted to an AND circuit 40.
In FIG. 2
As shown in FIG. 1 (e), it is possible to eliminate erroneous detection in a normal portion due to a polarity mismatch generated near a central portion (non-edge region) of a fine circuit pattern.

FIG. 11 shows the area selection circuits 18a to 18y,
FIG. 2 is a diagram illustrating a configuration example of an AND circuit 19; Delay circuit 17
The polarity comparison results output from a to 17y indicate the detected image signal f and the stored image signal g at positions shifted by ± 2 pixels by the cutout circuits 12a, 12b, 13a, and 13b.
, And a positional deviation amount (X ₁ , ΔY ₁ ) obtained by the positional deviation amount detection circuit 16,... (ΔXm, ΔYm), the binarized signal input to the area selection circuits (AND circuits) 18a to 18y is selected as a signal “1”,
In the area selection circuits (AND circuits) 18a to 18y, a logical product of the non-coincidence binarized signals output from the polarity comparison circuits 14a to 14y and the binarized signal selected from the position shift amount detection circuit 16 is obtained. That is, as shown in FIG.
The ND circuit 19 calculates the logical product of them in a range of ± 2 pixels, and the determination shown in FIG. 24 can be realized.

In particular, as shown in FIG. 24, in the case of a multilayer circuit pattern, the position shift amount detection circuit 16 and the area selection circuit (A
ND circuits) 18a to 18y and an OR circuit 19 are required for defect detection. That is, the detection multilayer pattern _{F 2} in FIG. 24 (a), FIG criteria multilayer pattern _{G 2} 24 (b)
Shown in The detection multilayer pattern F ₂ detected image signal f
For the ₂ and the reference multi-layer pattern stored image signal _{g 2} of _{G 2} shows the signal waveforms in FIG. 24 (c). As can be seen from these signal waveforms, there is a portion having no displacement and a portion having a displacement between them. In the case of a multilayer pattern, the upper layers do not have a positional shift, but the lower layers have a positional shift. Therefore, the differentiated polarity waveform signals 100a and 100b shown in FIG. 24D are obtained from the primary differentiating circuits 11a and 11b. These polarity waveform signals 100a and 100b are compared with polarity comparison circuits 14a to 14
If the comparison is made only in y, the determination result I (incorrect detection and mismatch due to a defect as shown in FIG. 24E are detected as polarity mismatch in the edge region) occurs. Therefore in FIG. 24 (e), showed a detection multilayer pattern relationship shifted by circuit 12b cut the detected image signal f ₂ of F ₂ the stored image signal g ₂ of the reference multilayer pattern G ₂ to the left. These derivative polar waveform signals 100a,
100b is shown in FIG. And this polarity waveform signal 1
Determination results II obtained by comparing 00a and 100b in the polarity comparison circuits 14a to 14y (two erroneous detections and a mismatch due to a defect are detected as the polarity mismatch in the edge region as shown in FIG. 24H). Is obtained. The AND result of the determination result I and the determination result II is obtained by the AND circuit 19 to obtain a final determination result as shown in FIG. 24 (i).

The configuration example of the alignment using the polarity of the first derivative and the defect judgment method has been described above. According to the above configuration, a circuit pattern of an LSI wafer or the like to be inspected has a three-dimensional shape difference such as film thickness or edge drooping, a difference between layers, or a shape difference due to a sampling error at the time of detection, and shading. , It is possible to detect only true defects with high accuracy.

Further, the position shift of the darkest point of the pattern edge can be detected as a defect, and the dimensional accuracy is extremely high.

In the above-mentioned configuration example, both the first differentiation and the second differentiation are performed by cutting out 3 × 3 pixels. However, the present invention can be realized by enlarging it to 5 × 5 pixels or the like. In addition, since the second derivative targets an image obtained under bright-field illumination, the configuration is such that a dark pattern edge is detected. , -1 or the like.

Further, in the position shift detecting circuit 16 of FIG.
The number of mismatched pixels S (△ X, △ Y), △ X, △ Y = −2, −1,0,
The positional deviation amounts △ X and な る Y satisfying S (△ X, △ Y) ≦ Sth (Fth) were obtained for 1 and 2, but the threshold value Sth (Fth)
Besides setting a constant,

[0050]

(Equation 2)

For example, automatic setting may be performed. here,
C ₁ and C ₂ are constants. As a result, the number of points to be aligned can be increased or decreased according to the state of the circuit pattern (wiring pattern), and the defect detection sensitivity can be automatically set.

Further, in order to more positively allow a shift between layers, a plurality of alignment points may be obtained by the method described below. The number of mismatched pixels S (△ Xmin, △ Ymin) (where △ Xmi
n, △ Ymin: S (△ X, △ Y) at which S (△ X, △ Y) is the minimum is the number of mismatched pixels when the detected image signal f and the stored image signal g are aligned, and Consists of inconsistencies and defects. The mismatch between the normal portions is mainly caused by interlayer displacement, and in addition, there are minute irregularities in the circuit pattern.

In the interlayer misalignment pattern, when one image (for example, a recorded image) is shifted in the xy plane, there are positions (可能 な Xr, △ Yr) that can be aligned as shown in FIG.
Therefore, the value of S (△ X, △ Y) is small in a region where the interlayer shift occurs. On the other hand, the defect is located at the position (△ Xr, △ Yr)
Is not always adjusted, and S (ＳX
r, △ Yr) does not change. However, for a pattern with no interlayer displacement, shifting one image will result in (△ Xm
The normal part that matched at (in, △ Ymin) is detected as a mismatch, and as a result, the value of S (△ Xr, △ Yr) does not decrease. Therefore, from the magnitude of S (△ X, △ Y),
It is not possible to directly find the positions ΔXr and ΔYr where the interlayer slip is allowed.

Therefore, S (△ X, △) given by equation (1)
Y, △ Xof, △ Yof) are introduced.

ΔS (△ X, △ Y, △ Xof, △ Yof) = △ S (△ Xmin + △ Xof- △ X, △ Ymin + △ Yof- △ Y) -2S (△ Xmin + △ Xof, △ Ymin + △ Yof ) −S (minXmin + △ Xof + △ X, minYmin + △ Yof + △ Y) (1) This 、 S is one image of △ X and △ Y at the position of (△ Xmin + △ Xof, △ Ymin + △ Yof). Represents a mismatch that cannot be erased by shifting. This is shown in FIG.
7 will be described. FIG. 27 shows an example of an experiment (three-layer pattern) for compensating an interlayer alignment error due to image shift, that is, an example of a three-layer simulation pattern. A slight interlayer shift exists between the detected image and the recorded image. . In FIG. 27, the recorded image is xy only ± △ X, △ Y (both are 1) pixels.
A non-coincidence image obtained by shifting in the plane and comparing polarities is shown. In the figure, (△ Xmin, △ Ymin) =
(0,0) and (△ Xr, △ Yr) = (1,1),
At the position (0, -1), interlayer displacement is allowed.

Here, assuming that (△ Xof, △ Yof) = (0,0), △ S (△ X, △ Y, 0,0) is minimized (△ Xs, △ Y
The position s) is the position (1, 1) where the layer B is aligned.
△ S (△ Xs, △ Ys, 0,0) / 4;
Mismatch for C layer at (0,0).

S (0,0)-△ S (△ Xs, △ Ys, 0,0)
/ 4; mismatch for layer B at (0,0).

Is as follows. Moreover, S (0,0)-△
The quantity S (△ Xs, △ Ys, 0,0) becomes zero at (1,1). This is because, in the number of mismatched pixels obtained by aligning the pattern at a plurality of positions, if the number of mismatched pixels with a certain number of mismatched pixels is selected to be a position having a value close to a linear sum, optimum alignment can be achieved. It represents what you can do.

Therefore, min △ S (△ X, △ Y, 0,0) / 4:
At (△ Xmin, △ Ymin) and positions shifted by (△ X, △ Y) from this, there is a discrepancy between layers that cannot be aligned.

S (△ Xmin, △ Ymin) −min △ S △ S (△ X, △
Y, 0,0) / 4: alignment is not possible with (△ Xmin, △ Ymin), but discrepancies in layers that can be aligned when shifted by (△ X, △ Y).

Can be expressed as Also, more generally, min
△ S (△ X, △ Y, △ Xof, △ Yof) / 4: (△ Xmin + △ Xof, △ Ymi
n + △ Yof) and discrepancies for layers that cannot be aligned by (し て も X, △ Y) shift.

S (△ Xmin + △ Xof, △ Ymin + △ Yof) −min △ S
(△ X, △ Y, △ Xof, △ Yof) / 4: (△ Xmin + △ Xof, △ Ymin + △
Disagreement on layers that cannot be aligned with (Yof), but can be aligned by shifting (△ X, △ Y).

Is obtained. Therefore, min △ S (△ X, △ Y, △ Xof,
△ Yof) / 4 is small and S (ＳXmin + △ Xof, △ Ymin + △ Yof)
−min △ S (△ X, △ Y, △ Xof, △ Yof) / 4 is large (△ X
At the image shift position of (min + △ Xof, △ Ymin + △ Yof), and (△ X, △ Y), many normal parts that did not match with (△ Xmin + △ Xof, △ Ymin + △ Yof) are replaced by (△ X, △ Y ), The alignment is correct, so that it can be erased, and the mismatch that does not match even if the image is shifted is small.

In the example shown in FIG. 27, the positions where min △ S (△ X, △ Y, 0,0) / 4 <Sth (2) (Sth: threshold) hold are (0,0), (1,
1), and the position where min △ S (△ X, △ Y, △ Xof, △ Yof) ≦ min △ S (△ X, △ Y, 0,0) (3) holds is (0, −1) , (0,0), (1,
0), (0, 1), and (1, 1). These positions can correctly align all the layers A, B, and C, and it is understood that this concept is appropriate.

In the case of a two-layer pattern, the above concept leads to an optimal solution. FIG. 28 is a diagram showing an example of an experiment (two-layer pattern) for compensating an interlayer alignment error due to an image shift, that is, an example of a simulated pattern of two layers. A slight interlayer shift exists between the detected image and the stored image. I do. In the figure, min △ S (△ X, △ Y, △ Xof, △ Yof) ≦ min △ S (△ X, △ Y, 0,0) <Sth (4) holds (△ Xmin + △ Xof, △ Ymin + △ Yof) and (△ X, △
The positions shifted by Y) are (0,0) and (1,1)
And the positions where the layer A and the layer B are correctly aligned.

Next, specific detection means of (△ Xs, △ Ys) will be described.

[0067]

(Equation 3)

[0068]

(Equation 4)

At the position of (△ Xmin, △ Ymin), of the number of mismatched pixels S (△ Xmin, △ Ymin), registration is not possible at this position. Number of mismatched pixels for possible patterns. This value is large (considered as interlayer shift) (erasing maximum ... interlayer shift)

[0070]

(Equation 5)

At the position of (△ Xmin, △ Ymin), of the number of mismatched pixels S (△ Xmin, △ Ymin), (△ X,
When the image is shifted by ΔY), the number of mismatched pixels that cannot be aligned even if shifted. This value is small (the mismatch itself is small). (Unmatched small ... can be deleted)

[0072]

(Equation 6)

Selection of image matching position.

[0074]

(Equation 7)

At the position of (△ Xmin, △ Ymin), of the number of mismatched pixels S (△ Xmin, △ Ymin), registration is not possible at this position. Number of mismatched pixels for possible patterns. This value is large (considered as interlayer shift) (erasing maximum ... interlayer shift)

[0076]

(Equation 8)

The offset (△ Xof, △ Y) is added to (△ Xmin, △ Ymin).
of) (位置 Xmin + △ Xof, △ Ymin + △ Yof)
The number of unmatched pixels is small even at a position shifted by (△ X, △ Y). (Erase max)

[0078]

(Equation 9)

Selection of image matching position.

[0080] Positioning is performed at any two points, a mismatch that can be eliminated at these positions is obtained, and a position where the remaining mismatch is small is detected as a position where interlayer displacement is allowed.

FIG. 12 is a diagram showing another embodiment.
The configuration from the image sensor 4 to the AND circuit 19 is the same as that in FIG. The detected image signal f and the stored image signal g are delayed by the delay circuits 41a and 41b, and the 5 × 5 pixel area of the delayed detected image signal f is cut out by the cutout circuit 42a having the same configuration as the cutout circuits 12a and 13a. Create a state shifted by ± 2 pixels. In addition, the cut-out circuit 42b having the same configuration as the cut-out circuits 12b and 13b synchronizes the delayed stored image signal g with the center position of the 5 × 5 pixels. Next, the difference image detection circuit 43a
43y, the difference image between the detected image signal f shifted by ± 2 pixels and the stored image signal g is detected using the outputs of the cutout circuits 42a and 42b. The minimum value detection circuit 44 determines whether the binarized edge patterns, which are the outputs of the corresponding cutout circuits 13a and 13b, are both at the position "0" (the OR of the outputs of the cutout circuits 13a and 13b shown in FIG. 10).
In the area other than the edge detected as “0” in FIG. 21D, which is detected by the circuit 39), among the difference image outputs of the difference image detection circuits 43a to 43y, the position shift amount detection circuit 16 outputs The minimum value at the set position is detected. If any of the binarized edge patterns detected by the OR circuit 39 is “1”, the minimum value is set to 0, for example, and the difference image output is set to 0. The binarization circuit 45
The minimum value difference image output of the minimum value detection circuit 44 is set to a predetermined threshold V
This circuit binarizes at th (for example, as shown in FIG. 22), detects a defect such as discoloration, and takes the logical product of this and the output of the AND circuit 19.

[0082] With this configuration, as shown in FIG. 22, the difference image detection circuit 43a~43y the detection image signal (signal waveform) of the pattern _{F 4} shown in FIG. 22 (c) detecting the image of _{f 4} and the pattern _{G 4} signal difference (signal waveform) _{g 4} image (FIG. 2
2 (d) shows a difference signal waveform. ), And the minimum value detection circuit 44 detects the difference image detection circuits 43a to 43a in the non-edge area where the OR circuit 39 which takes the logical sum of the outputs of the extraction circuits 13a and 13b detects "0".
The minimum value in the range of the position output by the positional deviation amount detection circuit 16 (without positional deviation) is obtained from the differential image signal output from 43y, and the minimum value of the differential image signal is equal to or greater than a predetermined threshold Vth. In this case, the binarization circuit 45 outputs a signal of "1", and this is ORed with the output of the AND circuit 19, so that it is possible to detect a defect such as discoloration as shown in FIG. Becomes

As another embodiment, in FIG. 12, the above-described binarization circuit 45 is eliminated, and the binarization edge pattern signal detected by the OR circuit 39 is not used.
Among the difference image signals output from the difference image detection circuits 43a to 43y, the minimum value in the range of the position output from the position error detection circuit 16 (without any position error) is obtained and output from the AND circuit 19. The threshold value is changed based on the signal in the area where the polarities do not match, that is, the AND circuit 19
For the regions where the output polarities are mismatched,
Various defects (shapes) are obtained by a binarized signal obtained by binarizing the minimum value of the difference image signal by the minimum value detection circuit 44 at a low threshold value and otherwise at a high threshold value (for an area where the polarity does not become inconsistent). Defects and discoloration defects) can be detected.

As another embodiment, in FIG. 12, the detected image signal f and the stored image signal g are respectively set to f (x, y) and g (x, y) as the threshold value Vth used in the binarization circuit 45. When, Vth (x, y) = C 1 min {f (x, y), g (x, y)} + C 2 may be. Here, C ₁ and C ₂ are constants. If the output of the minimum value detection circuit 44 is binarized with the threshold value Vth (x, y), the binarization can be optimally performed according to the brightness of the circuit pattern, and various defects can be detected. In this case, based on the detected image signal input to the minimum value detection circuit 44, the grayscale value of the pixel corresponding to the positional deviation of the minimum mismatching pixel number obtained by the positional deviation amount detection circuit 16 and the corresponding stored image signal From the gray value of a pixel, the threshold V
Decide th.

FIG. 13 is a diagram showing another embodiment for performing an image filtering operation. The configuration from the image sensor 4 to the displacement detection circuit 16 is the same as that in FIG. The coefficient detection circuit 46 is provided with the displacement detection circuit 1
6 is a circuit for inputting the value of the number of unmatched pixels, thereby obtaining coefficients aij and bij of filter circuits 47a and 47b described later. The filter circuits 47a and 47b convolve filters having coefficients aij and bij with respect to the image signals delayed by the delay circuits 41a and 41b. The cutout circuit 42a cuts out a region of 5 × 5 pixels of the filtered detection image signal and creates a state shifted by ± 2 pixels. Further, the cutout circuit 42b synchronizes the filtered stored image signal g with the center position of the 5 × 5 pixels. Next, the difference image detection circuits 43a to 43a
43y, the difference image signal between the detected image signal f shifted by ± 2 pixels and the stored image signal g is detected using the outputs of the cutout circuits 42a and 42b. Minimum value detection circuit 44
Detects the minimum value of the difference image at the position output by the displacement amount detection circuit 16 among the difference image detection circuits 43a to 43y. The binarization circuit 45 is a circuit that binarizes the output of the minimum value detection circuit 44.

Here, in the coefficient detection, FIG.
By applying the following function and the like, a virtual position where the number of mismatched pixels is minimized by a least square method or the like is determined with an accuracy of a pixel unit or less,
The difference between this position and the position in pixel units where the number of mismatched pixels is minimized is detected. Then, filter coefficients aij and bij for respectively shifting the detected image signal and the stored image signal in the reverse direction by an amount equal to 1/2 of the difference are obtained.

For example, if the detected image is 0.2 pixels in the x direction,
If the stored image is shifted by the same amount in the y direction by 0.3 pixels and the stored image is shifted by the same amount in the opposite direction, the coefficient becomes:

[0088]

(Equation 10)

## EQU11 ##

Although the above description has shown an example in which the two images are accurately matched, for example, the two images are shifted so as to be shifted by 画素 pixel, and as shown in FIG.
If the minimum value is detected at a plurality of positions such as 0, △ X = -1, a shape difference of 1/2 pixel can be positively allowed.

According to the above configuration, the image can be aligned with an arbitrary accuracy based on the relationship between the number of unmatched pixels and the amount of misalignment. For example, as shown in FIG. 26, a sampling error at the time of image detection is compensated. It becomes possible. here,
(A) shows a detection pattern, (b) shows a memory pattern,
(C) shows the detection pattern and the storage pattern after filtering.

FIG. 13 shows an example in which a defect is determined by detecting a difference image of a grayscale image. This may be determined by comparing polarities, as shown in FIG. 1, or as shown in FIG. A combination of polarity comparison and difference image detection is also possible.

According to the above configuration, the alignment accuracy can be drastically improved from a conventional pixel unit to a unit smaller than a pixel, so that even a minute defect can be detected.

[0094]

According to the present invention, even if the shape of the grayscale waveform of the detected image is considerably different in the normal part, fine defects can be detected. There is no erroneous detection of a difference in condition, a displacement between layers, or a sampling error at the time of detection.
Further, since the alignment accuracy can be improved, it is possible to detect even finer defects. further,
Not only pattern defects but also discoloration can be detected without overlooking. Further, not only the presence or absence of a defect but also its size can be accurately detected.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment of a circuit pattern defect detection method and apparatus according to the present invention.

FIG. 2 is an explanatory diagram for comparing two chips.

FIG. 3 is a diagram showing an example of a primary differentiation in which a primary differentiation is performed in the primary differentiation circuit shown in FIG. 1;

FIG. 4 is a diagram showing an example of a second differentiation in which a second differentiation is performed in the second differentiation circuit shown in FIG. 1;

FIG. 5 is a diagram showing positional deviation amounts (△ X, △ Y).

FIG. 6 is a configuration diagram showing an example of a specific configuration of a primary differentiating circuit.

FIG. 7 is a configuration diagram showing an example of a specific configuration of a secondary differentiating circuit.

FIG. 8 is a configuration diagram showing an example of a specific configuration of a cutout circuit that cuts out a primary differential signal output from the primary differential circuit.

FIG. 9 is a configuration diagram showing an example of a specific configuration of a cutout circuit that cuts out a secondary differential signal output from a secondary differential circuit.

FIG. 10 illustrates a configuration example of a polarity comparison circuit.

FIG. 11 is a configuration diagram showing an area selection circuit, an AND circuit, and the like.

FIG. 12 is a diagram showing another embodiment of the circuit pattern defect detection method and the device of the present invention which are different from FIG. 1;

FIG. 13 is a diagram showing still another embodiment of a circuit pattern defect detection method and apparatus according to the present invention, which is different from FIG.

FIG. 14 is a diagram for explaining a conventional technique.

FIG. 15 is a diagram for explaining a conventional technique.

FIG. 16 is a diagram showing an example of each gray-scale waveform.

FIG. 17 is a diagram showing an example of each gray-scale waveform.

FIG. 18 is a view for explaining the principle of polarity comparison according to the present invention.

FIG. 19 is a view for explaining improved contents in the polarity comparison according to the present invention.

FIG. 20 is a diagram illustrating a case where an erroneous detection occurs in the polarity comparison according to the present invention.

FIG. 21 is a diagram for explaining polarity comparison using second-order differentiation.

FIG. 22 is a view for explaining discoloration defect detection.

FIG. 23 is a diagram showing a relationship between a positional shift and the number of mismatched pixels.

FIG. 24 is a diagram for explaining a polarity comparison corresponding to interlayer displacement.

FIG. 25 is a diagram showing the relationship between the displacement and the number of mismatched pixels.

FIG. 26 is a diagram showing that a detected image signal (pattern) and a stored image signal (pattern) are in a state where there is no displacement.

FIG. 27 is a diagram showing an example (three-layer pattern) of an experiment for compensating an interlayer alignment error by image shift.

FIG. 28 is a diagram showing an example (two-layer pattern) of an experiment for compensating an interlayer alignment error by image shift.

[Explanation of symbols]

10 ... primary differentiator circuit, 11 ... secondary differentiator circuit, 12,
13 ... Cutout circuit, 14 ... Polarity comparison circuit, 15 ... Counter circuit, 16 ... Position shift amount detection circuit, 18 ... Area selection circuit, 44 ... Minimum value detection circuit, 43 ... Difference image detection circuit, 45 ... Binarization circuit , 47 ... Filter circuit.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor, Tan Makinohira 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Pref. JP-A-61-65444 (JP, A) JP-A-63-32666 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/66 G01B 11/30 G01N 21/88 G01N 21 / 956

Claims (6)

(57) [Claims] [Claim 1 wherein said original using an image of a plurality of the inspection target circuit pattern obtained by sequentially imaging an object to be inspected circuit pattern formed to have the same object to be inspected circuit pattern <br/> over a method for inspecting a defect of the down position of <br/> the two images by performing a filtering process on at least one image of the two images the obtained by sequentially imaging an object to be inspected circuit pattern It changes the state of the deviation, the filter
A circuit pattern defect inspection method, wherein a defect of the circuit pattern to be inspected is detected using two images in which a state of a positional shift is changed by performing a ring process . 2. A method according to claim 1, wherein a plurality of circuit patterns to be inspected, which are originally formed to be the same, are sequentially imaged, and the state of the positional shift between the two images obtained by the sequential imaging is changed. A method for inspecting a defect of the circuit pattern to be inspected by comparing two images having different positions, the method comprising: A circuit pattern defect inspection method, wherein a defect is detected by changing detection sensitivity between an edge portion of a circuit pattern to be inspected and other portions. 3. A plurality of circuit patterns to be inspected, which are originally formed to be identical, are sequentially imaged, and the state of the positional shift between the two images obtained by the sequential imaging is changed. A method for inspecting a defect of the circuit pattern to be inspected by comparing two images having different positions, the method comprising: A circuit pattern defect inspection method, wherein the defect detection sensitivity is changed according to the state of a circuit pattern to be inspected. 4. A plurality of circuit patterns to be inspected, which are originally formed to be the same, are sequentially imaged, and the state of the positional shift between the two images obtained by the sequential imaging is changed. A method for inspecting a defect of the circuit pattern to be inspected by comparing two images obtained by changing the position of the two images, the method comprising: The two images are compared to detect a mismatch, and then the misalignment is detected by changing the positional shift between the two images obtained by sequentially capturing the images to a second state, and then comparing the two images to detect a mismatch. A circuit pattern defect inspection method characterized by detecting a mismatch that appears in common between the mismatch detected by comparison in the first position shift state and the mismatch detected by comparison in the second position shift state as a defect. . 5. A defect of the pattern to be inspected to be detected may be caused by a difference in three-dimensional shape such as a thickness of the pattern to be inspected or a drooping state of an edge, a displacement between layers, or a sampling error at the time of detection. 2. The method according to claim 1, wherein
5. The circuit pattern defect inspection method according to any one of claims 1 to 4. 6. An apparatus for inspecting a defect of a pattern to be inspected using an image of the circuit pattern to be inspected obtained by sequentially imaging a plurality of circuit patterns to be inspected formed so as to be originally identical. An imaging unit that captures the circuit pattern to be inspected to obtain an image of the circuit pattern to be inspected, a storage unit that stores images sequentially captured by the imaging unit, The two images are obtained by performing a filtering process on at least one of the obtained image and the image stored in the storage unit.
Filtering means for changing the state of the position shift, and said filtering means for changing the state of the position shift
And a defect detecting means for detecting a defect of the pattern to be inspected using the two images.