[go: up one dir, main page]

JP3119385B2 - Surface treatment method, surface treatment device and surface treatment liquid for electronic components and their electrode terminals - Google Patents

Surface treatment method, surface treatment device and surface treatment liquid for electronic components and their electrode terminals

Info

Publication number
JP3119385B2
JP3119385B2 JP04037465A JP3746592A JP3119385B2 JP 3119385 B2 JP3119385 B2 JP 3119385B2 JP 04037465 A JP04037465 A JP 04037465A JP 3746592 A JP3746592 A JP 3746592A JP 3119385 B2 JP3119385 B2 JP 3119385B2
Authority
JP
Japan
Prior art keywords
solder
surface treatment
electrode terminal
adsorbed
tin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP04037465A
Other languages
Japanese (ja)
Other versions
JPH05235232A (en
Inventor
一 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP04037465A priority Critical patent/JP3119385B2/en
Publication of JPH05235232A publication Critical patent/JPH05235232A/en
Application granted granted Critical
Publication of JP3119385B2 publication Critical patent/JP3119385B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Manufacturing Of Electrical Connectors (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】この発明は、例えばLSIチップ
等、基板上に半田付け実装される電子部品およびその電
極端子の表面処理方法、表面処理装置および表面処理液
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface treatment method, a surface treatment apparatus, and a surface treatment liquid for an electronic component, such as an LSI chip, which is soldered and mounted on a substrate, and its electrode terminals.

【0002】[0002]

【従来の技術】プリント基板にLSIチップ等の電子部
品を半田付け実装するには、半田付けする金属表面の清
浄および濡れ性向上の役割をするフラックス(一般的に
はロジン系フラックス)と、半田とが必要である。例え
ば図7に示すようにプリント基板の端子表面7にクリー
ム半田8(半田粒子とフラックスを混ぜてクリーム状に
したもの)を印刷し、この上に電子部品1の電極端子2
を置き、リフロー炉にて加熱する工程をとっていた。
2. Description of the Related Art In order to mount an electronic component such as an LSI chip on a printed circuit board by soldering, a flux (generally, a rosin-based flux) which plays a role of cleaning and improving wettability of a metal surface to be soldered, and a solder. Is necessary. For example, as shown in FIG. 7, cream solder 8 (which is made by mixing solder particles and flux to form a cream) is printed on the terminal surface 7 of the printed circuit board, and the electrode terminals 2 of the electronic component 1 are printed thereon.
And a step of heating in a reflow furnace.

【0003】図8にこの電子部品実装機を示す。即ち、
クリーム半田印刷機10にてプリント基板の端子表面7
にクリーム半田8を印刷し、チップマウンタ11にてプ
リント基板上に電子部品1を置き、リフロー炉12にて
上記クリーム半田8を加熱溶解させることにより半田付
け実装するという工程をとっていた。
FIG. 8 shows this electronic component mounting machine. That is,
Terminal surface 7 of printed circuit board by cream solder printing machine 10
Then, the cream solder 8 is printed on the printed circuit board, the electronic component 1 is placed on the printed board by the chip mounter 11, and the cream solder 8 is heated and melted in the reflow furnace 12 to be soldered and mounted.

【0004】この場合、電子部品の電極端子は半田濡れ
性を良くするために半田またはスズメッキ(3〜5μ
m)が施されている。このメッキは、あくまで濡れ性を
向上させるためなので、5μm以上の厚みでメッキが施
されることはない。
In this case, the electrode terminals of the electronic component are soldered or tin-plated (3 to 5 μm) in order to improve the solder wettability.
m). Since this plating is for the purpose of improving the wettability, plating is not performed with a thickness of 5 μm or more.

【0005】[0005]

【発明が解決しようとする課題】ところが、最近の電子
機器の小型化に伴い電子部品の小型化も急速に進んでい
る。電子部品を小型化すると、これらの電子部品を実装
するプリント基板の電極端子ピッチもまた微細になるた
め、微細パターンへの半田付けが必要とされる。しかし
ながら、微細パターンの半田付けには図7に示したよう
に、半田ボール9の発生や半田による電極間ショートな
どの発生により、半田付け工程の歩留まり低下という問
題があった。
However, with the recent miniaturization of electronic equipment, miniaturization of electronic components has been rapidly progressing. When electronic components are miniaturized, the electrode terminal pitch of a printed circuit board on which these electronic components are mounted also becomes fine, so that soldering to a fine pattern is required. However, as shown in FIG. 7, the soldering of the fine pattern has a problem in that the yield of the soldering process is reduced due to the occurrence of solder balls 9 and the occurrence of short-circuit between electrodes due to soldering.

【0006】この発明の課題は、半田ボールの発生およ
び電極間ショートを防止して微細ピッチへの電子部品実
装を可能にすると共に、クリーム半田印刷工程を削減で
きる電子部品、およびその電極端子の表面処理方法、表
面処理装置および表面処理液を提供することである。
SUMMARY OF THE INVENTION An object of the present invention is to prevent the generation of solder balls and short-circuiting between electrodes, thereby enabling electronic components to be mounted on a fine pitch and to reduce the cream solder printing process, and the surface of electrode terminals thereof. An object of the present invention is to provide a treatment method, a surface treatment device and a surface treatment liquid.

【0007】[0007]

【課題を解決するための手段】第1の発明は、電子部品
における電極端子の表面処理方法であって、カチオン
界面活性剤を吸着させたロジン系フラックスを分散させ
た半田またはスズ電解液中に電子部品の電極端子を浸漬
させる工程と、上記電極端子の表面に上記半田またはス
ズと共にカチオン系界面活性剤を吸着させたロジン系フ
ラックスを析出させる工程とを有することを特徴とす
る。◇第2の発明は、電子部品における電極端子の表面
処理装置であって、電子部品の電極端子を表面処理する
電子部品の電極端子表面処理方法において、カチオン
界面活性剤を吸着させたロジン系フラックスを分散させ
た半田またはスズ電解液中に、電子部品の電極端子を浸
漬させる第1の手段と、上記電極端子の表面に上記半田
またはスズと共にカチオン系界面活性剤を吸着させたロ
ジン系フラックスを析出させる第2の手段とを具備した
ことを特徴とする。◇第3の発明は、電子部品であっ
て、この電子部品の電極端子と、この電極端子をカチオ
系界面活性剤を吸着させたロジン系フラックスを分散
させた半田またはスズ電解液中に浸漬させることにより
上記電極端子の表面に上記半田またはスズと共に析出さ
れるカチオン系界面活性剤を吸着させたロジン系フラッ
クスとを有することを特徴とする。◇第4の発明は、電
子部品における電極端子の表面処理液であって、カチオ
系界面活性剤と、このカチオン系界面活性剤を吸着さ
せたロジン系フラックスと、このロジン系フラックスを
分散させた半田またはスズ電解液とを有し、被処理材表
面に上記半田またはスズと共にカチオン系界面活性剤を
吸着させたロジン系フラックスを析出させることを特徴
とする。
A first aspect of the present invention is a method for treating a surface of an electrode terminal in an electronic component, the method comprising the steps of: dissolving a rosin flux adsorbed with a cationic surfactant in a solder or tin electrolyte; A step of immersing the electrode terminal of the electronic component in the substrate, and a step of depositing a rosin-based flux in which a cationic surfactant is adsorbed together with the solder or tin on the surface of the electrode terminal. ◇ A second invention is a surface treatment device for an electrode terminal of an electronic component, wherein the rosin-based surface treatment method for an electrode terminal of an electronic component has a cation- based surfactant adsorbed thereon. First means for immersing an electrode terminal of an electronic component in a solder or tin electrolyte in which a flux is dispersed; and a rosin flux in which a cationic surfactant is adsorbed on the surface of the electrode terminal together with the solder or tin. And second means for depositing ◇ third invention, Kachio an electronic component, and the electrode terminals of the electronic component, the electrode terminal
By immersing the emissions-based surfactant in the solder or tin electrolyte solution is dispersed rosin flux was adsorbed to adsorb the cationic surfactant deposited with the solder or tin to the surface of the electrode terminal Rosin flux. ◇ fourth invention is a surface treatment solution of the electrode terminals in the electronic component, Kachio
And a rosin flux in which the cationic surfactant is adsorbed, and a solder or tin electrolyte in which the rosin flux is dispersed. It is characterized in that a rosin flux onto which a cationic surfactant is adsorbed is deposited.

【0008】[0008]

【作用】この発明は、上述したような手段を有すること
により、半田またはスズと共にカチオン系界面活性剤を
吸着させたロジン系フラックスを電極端子表面に析出さ
せ、基板への実装の際、上記電極端子表面に析出された
半田またはスズおよびカチオン系界面活性剤を吸着させ
たロジン系フラックスによって、微細ピッチへの実装で
あっても半田ボールの発生や電極間ショートなどを発生
させることなく半田付けを行なうことができる電子部品
を得ることができる。
According to the present invention, a rosin flux in which a cationic surfactant is adsorbed together with solder or tin is deposited on the surface of an electrode terminal by having the means described above, and the above electrode is mounted on a substrate when mounted on a substrate. Rosin flux that adsorbs solder or tin and cationic surfactant deposited on the surface of the terminal allows soldering without generating solder balls or shorting between electrodes, even when mounted on a fine pitch. An electronic component that can be performed can be obtained.

【0009】[0009]

【実施例】以下、この発明の実施例を図1ないし図6を
参照して説明する。図1は、LSIチップ1の外観構成
を示す斜視図である。LSIチップ1は複数の電極端子
2を有する。電極端子2はフープ材をプレス加工して形
成されるものである。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a perspective view showing an external configuration of the LSI chip 1. The LSI chip 1 has a plurality of electrode terminals 2. The electrode terminal 2 is formed by pressing a hoop material.

【0010】図2は、電極端子の材料となるフープ材か
らLSIチップ1の電極端子2を形成するまでの工程を
説明するフローチャートである。フープ材は、まずプレ
ス工程によって電極端子の形状に打抜かれて、電極端子
が形成される。図3はプレス加工後のフープ材3を示す
平面図である。フープ材3にはプレス加工によって電極
端子となるための複数の帯状部分3aが形成される。プ
レス工程が終了すると、フープ材3はメッキ工程に進
む。
FIG. 2 is a flow chart for explaining steps from the step of forming the electrode terminals 2 of the LSI chip 1 from the hoop material as the material of the electrode terminals. The hoop material is first stamped into a shape of an electrode terminal by a pressing process to form an electrode terminal. FIG. 3 is a plan view showing the hoop material 3 after the press working. The hoop material 3 is formed with a plurality of strip-shaped portions 3a to become electrode terminals by press working. When the pressing step is completed, the hoop material 3 proceeds to a plating step.

【0011】図4はメッキ工程の詳細を示す図である。
リール4にはプレス加工後のフープ材3が巻かれてい
る。リール4から繰り出されたフープ材3はメッキ装置
5に搬送される。メッキ装置5では、フープ材3に付着
したプレス油等の汚れを落とす前処理工程を経た後に、
メッキ工程(電解メッキ)に進む。メッキ工程において
はフラックス粒子を分散させたメッキ液を使用する。
FIG. 4 is a diagram showing details of the plating step.
The hoop material 3 after the press working is wound around the reel 4. The hoop material 3 unreeled from the reel 4 is transported to the plating device 5. In the plating apparatus 5, after passing through a pretreatment step of removing dirt such as press oil adhered to the hoop material 3,
Proceed to plating step (electrolytic plating). In the plating step, a plating solution in which flux particles are dispersed is used.

【0012】図5はフラックス粒子をメッキ液中に分散
させる概念を示す図である。ここで、ロジン系フラック
スは主成分であるロジン(アビエチン酸80〜90重量
%含有)をIPA(イソプロピルアルコール)等の溶剤
に20〜50重量%/体積%溶解させたものである。ロ
ジン系フラックスのフラックス粒子は直径3μm以下の
微粒子である。このフラックス粒子をカチオン系界面活
性剤中に分散させると、フラックス粒子の周囲にカチオ
系界面活性剤粒子が吸着してフラックス粒子自体が
「+」の電荷を帯びる。そして、半田(スズと鉛の合
金)を電解液中に溶解させSn2+,Pb2+イオンが存在
するメッキ液に、カチオン系界面活性剤粒子が吸着され
たフラックス粒子を10〜15重量%の割合で添加して
分散させる。
FIG. 5 is a view showing the concept of dispersing flux particles in a plating solution. Here, the rosin-based flux is obtained by dissolving rosin (containing 80 to 90% by weight of abietic acid) as a main component in a solvent such as IPA (isopropyl alcohol) at 20 to 50% by weight / volume%. The flux particles of the rosin-based flux are fine particles having a diameter of 3 μm or less. When dispersing the flux particles in the cationic surfactant, Kachio around the flux particles
The flux-type surfactant particles are adsorbed and the flux particles themselves are charged with “+”. Then, solder (an alloy of tin and lead) is dissolved in an electrolytic solution, and flux particles in which cationic surfactant particles are adsorbed are added at a ratio of 10 to 15% by weight to a plating solution containing Sn2 + and Pb2 + ions. And disperse.

【0013】図4に戻り、メッキ工程では上述のような
メッキ液を用いて電解メッキを行なう。即ち、上記メッ
キ液中に電極端子となるフープ材3と半田電極(板状の
半田)とを浸漬する。次に、フープ材3を「−」電極と
し、半田板を「+」電極として電流を流す。この場合、
メッキ厚は電流量と時間とにより決まる。そして、この
実施例ではメッキ厚を通常のメッキ厚(3〜5μm)よ
りも厚く、10〜20μmのメッキ厚までフープ材3の
表面に半田を析出させる。この時、メッキ液にはカチオ
系界面活性剤粒子が吸着されたフラックス粒子が分散
しているので、フープ材3の表面には半田とフラックス
粒子とが共に析出(共析)する。
Returning to FIG. 4, in the plating step, electrolytic plating is performed using the above-mentioned plating solution. That is, the hoop material 3 serving as an electrode terminal and the solder electrode (plate-like solder) are immersed in the plating solution. Next, an electric current is passed using the hoop material 3 as a “−” electrode and the solder plate as a “+” electrode. in this case,
The plating thickness is determined by the amount of current and time. In this embodiment, the plating thickness is larger than the normal plating thickness (3 to 5 μm), and solder is deposited on the surface of the hoop material 3 to a plating thickness of 10 to 20 μm. At this time, the plating solution Kachio
Since the flux particles having the adsorbed surfactant particles dispersed therein, the solder and the flux particles are both precipitated (eutectoid) on the surface of the hoop material 3.

【0014】そして、メッキ工程が終了すると洗浄工程
に進んでフープ材3が洗浄され、乾燥工程に進んで乾燥
される。そして、メッキ装置5を出たフープ材3は巻取
リール6に巻取られる。
When the plating process is completed, the process proceeds to a cleaning process, in which the hoop material 3 is cleaned, and then proceeds to a drying process to be dried. Then, the hoop material 3 that has exited the plating device 5 is taken up on a take-up reel 6.

【0015】図2に戻って、メッキ工程が終了すると、
次にボンディング工程に進む。このボンディング工程で
は、半田およびフラックス粒子がメッキされたフープ材
3にLSIチップが載せられ、電極端子2となるフープ
材3の帯状部分3aとLSIチップとがボンディングさ
れる。このボンディング工程を終了すると、モールド工
程に進む。モールド工程ではボンディングしたLSIチ
ップの部分を樹脂によりモールドする。モールド工程が
終了すると、フープ材3の不要部分をカットして複数の
電極端子2(帯状部分3a)を夫々独立させ、図1に示
す形状のLSIチップ1が完成する。
Returning to FIG. 2, when the plating step is completed,
Next, the process proceeds to the bonding step. In this bonding step, the LSI chip is mounted on the hoop material 3 on which the solder and flux particles are plated, and the band-shaped portion 3a of the hoop material 3 that becomes the electrode terminal 2 and the LSI chip are bonded. When this bonding process is completed, the process proceeds to a molding process. In the molding step, the bonded LSI chip is molded with resin. When the molding process is completed, unnecessary portions of the hoop material 3 are cut to separate the plurality of electrode terminals 2 (band-like portions 3a) from each other, and the LSI chip 1 having the shape shown in FIG. 1 is completed.

【0016】上述した工程により、LSIチップ1にお
ける電極端子2の表面には半田と共にフラックスが析出
されているので、クリーム半田と異なり均一に少量の半
田とフラックスとが供給でき、クリーム半田を使用する
必要がない。即ち、図6に示すように、プリント基板の
端子表面7にLSIチップ1の電極端子2を図8で示し
たチップマウンタ11で位置決めし、リフロー炉12を
通すことにより電極端子2表面のフラックスと半田とが
この順に熱溶解して電極端子2がプリント基板の端子表
面3に半田付けされる。
Since the flux is deposited together with the solder on the surface of the electrode terminal 2 of the LSI chip 1 by the above-described process, unlike the cream solder, a small amount of the solder and the flux can be supplied uniformly, and the cream solder is used. No need. That is, as shown in FIG. 6, the electrode terminals 2 of the LSI chip 1 are positioned on the terminal surfaces 7 of the printed circuit board by the chip mounter 11 shown in FIG. The solder is thermally melted in this order, and the electrode terminals 2 are soldered to the terminal surfaces 3 of the printed circuit board.

【0017】[0017]

【発明の効果】この発明によれば、半田またはスズと共
カチオン系界面活性剤を吸着させたロジン系フラック
スを電極端子表面に析出させ、基板への実装の際、上記
電極端子表面に析出された半田またはスズおよびカチオ
系界面活性剤を吸着させたロジン系フラックスによっ
て基板への半田付けを行なうことができる電子部品を得
ることができ、半田ボールの発生および電極間ショート
を防止して微細ピッチへの電子部品実装を可能にすると
共に、クリーム半田印刷工程を削減できる電子部品、お
よびその電極端子の表面処理方法、表面処理装置および
表面処理液を提供することができる。
According to the present invention, a rosin flux in which a cationic surfactant is adsorbed together with solder or tin is deposited on the surface of an electrode terminal, and is deposited on the surface of the electrode terminal when mounted on a substrate. Solder or tin and katio
Emissions-based surfactant can be obtained an electronic component capable of performing soldering to the substrate by rosin flux was adsorbed, the electronic component mounting to a fine pitch by preventing the occurrence and a short circuit between electrodes of the solder balls And a surface treatment method, a surface treatment apparatus, and a surface treatment liquid for an electrode component capable of reducing the cream solder printing step, and the electrode terminal thereof.

【図面の簡単な説明】[Brief description of the drawings]

【図1】LSIチップの外観構成を示す斜視図である。FIG. 1 is a perspective view showing an external configuration of an LSI chip.

【図2】フープ材をLSI電極に加工するまでの動作を
示すフローチャートである。
FIG. 2 is a flowchart showing an operation until a hoop material is processed into an LSI electrode.

【図3】プレス後のフープ材を示す図である。FIG. 3 is a view showing a hoop material after pressing.

【図4】フープ材のメッキ工程を示す図である。FIG. 4 is a diagram showing a plating step of a hoop material.

【図5】フラックス粒子をメッキ液中に分散させる状態
を示す概念図である。
FIG. 5 is a conceptual diagram showing a state in which flux particles are dispersed in a plating solution.

【図6】クリーム半田を使用しない実装構造を示す図で
ある。
FIG. 6 is a diagram showing a mounting structure that does not use cream solder.

【図7】クリーム半田を使用する従来の実装状態を示す
図である。
FIG. 7 is a diagram showing a conventional mounting state using cream solder.

【図8】クリーム半田の印刷機からリフロー炉までの一
連の装置を示す図である。
FIG. 8 is a diagram showing a series of devices from a cream solder printing machine to a reflow furnace.

【符号の説明】[Explanation of symbols]

1…LSIチップ 2…電極端子 3…フープ材 4…リール 5…メッキ装置 6…巻取リール 7…端子表面 8…クリーム半田 9…半田ボール 10…クリーム半田印刷機 11…チップマウンタ 12…リフロー炉 DESCRIPTION OF SYMBOLS 1 ... LSI chip 2 ... Electrode terminal 3 ... Hoop material 4 ... Reel 5 ... Plating device 6 ... Take-up reel 7 ... Terminal surface 8 ... Cream solder 9 ... Solder ball 10 ... Cream solder printer 11 ... Chip mounter 12 ... Reflow furnace

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 カチオン系界面活性剤を吸着させたロジ
ン系フラックスを分散させた半田またはスズ電解液中に
電子部品の電極端子を浸漬させる工程と、上記電極端子
の表面に上記半田またはスズと共にカチオン系界面活性
剤を吸着させたロジン系フラックスを析出させる工程と
を有することを特徴とする電子部品における電極端子の
表面処理方法。
1. A step of immersing an electrode terminal of an electronic component in a solder or tin electrolyte solution in which a rosin flux in which a cationic surfactant is adsorbed is dispersed, and the surface of the electrode terminal together with the solder or tin. Depositing a rosin flux onto which a cationic surfactant has been adsorbed.
【請求項2】 電子部品の電極端子を表面処理する電子
部品の電極端子表面処理方法において、カチオン系界面
活性剤を吸着させたロジン系フラックスを分散させた半
田またはスズ電解液中に、電子部品の電極端子を浸漬さ
せる第1の手段と、上記電極端子の表面に上記半田また
はスズと共にカチオン系界面活性剤を吸着させたロジン
系フラックスを析出させる第2の手段とを具備したこと
を特徴とする電子部品における電極端子の表面処理装
置。
2. A method for treating an electrode terminal of an electronic component, the method comprising: treating a surface of an electrode terminal of the electronic component with a solder or tin electrolyte in which a rosin flux to which a cationic surfactant is adsorbed is dispersed. A first means for immersing the electrode terminal of the present invention; and a second means for depositing a rosin flux in which a cationic surfactant is adsorbed together with the solder or tin on the surface of the electrode terminal. Surface treatment device for electrode terminals in electronic components.
【請求項3】 電極端子と、この電極端子をカチオン
界面活性剤を吸着させたロジン系フラックスを分散させ
た半田またはスズ電解液中に浸漬させることにより上記
電極端子の表面に上記半田またはスズと共に析出される
カチオン系界面活性剤を吸着させたロジン系フラックス
とを有することを特徴とする電子部品。
3. An electrode terminal, and the electrode terminal is immersed in a solder or tin electrolyte in which a rosin flux in which a cationic surfactant is adsorbed is dispersed, so that the solder or tin is applied to the surface of the electrode terminal. Deposited with
An electronic component comprising: a rosin flux to which a cationic surfactant is adsorbed.
【請求項4】 カチオン系界面活性剤と、このカチオン
系界面活性剤を吸着させたロジン系フラックスと、この
ロジン系フラックスを分散させた半田またはスズ電解液
とを有し、被処理材表面に上記半田またはスズと共に
チオン系界面活性剤を吸着させたロジン系フラックスを
析出させることを特徴とする表面処理液。
4. A coating composition comprising a cationic surfactant, a rosin flux to which the cationic surfactant is adsorbed, and a solder or tin electrolyte in which the rosin flux is dispersed. Ca with the solder or tin to the processing material surface
A surface treatment liquid characterized by depositing a rosin flux onto which a thione surfactant is adsorbed.
JP04037465A 1992-02-25 1992-02-25 Surface treatment method, surface treatment device and surface treatment liquid for electronic components and their electrode terminals Expired - Fee Related JP3119385B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP04037465A JP3119385B2 (en) 1992-02-25 1992-02-25 Surface treatment method, surface treatment device and surface treatment liquid for electronic components and their electrode terminals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP04037465A JP3119385B2 (en) 1992-02-25 1992-02-25 Surface treatment method, surface treatment device and surface treatment liquid for electronic components and their electrode terminals

Publications (2)

Publication Number Publication Date
JPH05235232A JPH05235232A (en) 1993-09-10
JP3119385B2 true JP3119385B2 (en) 2000-12-18

Family

ID=12498276

Family Applications (1)

Application Number Title Priority Date Filing Date
JP04037465A Expired - Fee Related JP3119385B2 (en) 1992-02-25 1992-02-25 Surface treatment method, surface treatment device and surface treatment liquid for electronic components and their electrode terminals

Country Status (1)

Country Link
JP (1) JP3119385B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0560491U (en) * 1992-01-29 1993-08-10 株式会社日本省力産業研究所 Simple dry clothes dryer
US6181313B1 (en) 1997-01-30 2001-01-30 Hitachi, Ltd. Liquid crystal display controller and liquid crystal display device
US6731264B2 (en) 1994-09-30 2004-05-04 Semiconductor Energy Laboratory Co., Ltd. Driver circuit for display device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0560491U (en) * 1992-01-29 1993-08-10 株式会社日本省力産業研究所 Simple dry clothes dryer
US6731264B2 (en) 1994-09-30 2004-05-04 Semiconductor Energy Laboratory Co., Ltd. Driver circuit for display device
US6181313B1 (en) 1997-01-30 2001-01-30 Hitachi, Ltd. Liquid crystal display controller and liquid crystal display device
US6633274B1 (en) 1997-01-30 2003-10-14 Hitachi, Ltd. Liquid crystal display controller and liquid crystal display device
US7688303B2 (en) 1997-01-30 2010-03-30 Renesas Technology Corp. Liquid crystal display controller and liquid crystal display device
US8212763B2 (en) 1997-01-30 2012-07-03 Renesas Electronics Corporation Liquid crystal display controller and liquid crystal display device
US8547320B2 (en) 1997-01-30 2013-10-01 Renesas Electronics Corporation Liquid crystal display controller and liquid crystal display device

Also Published As

Publication number Publication date
JPH05235232A (en) 1993-09-10

Similar Documents

Publication Publication Date Title
US6217671B1 (en) Composition for increasing activity of a no-clean flux
US5615827A (en) Flux composition and corresponding soldering method
US6695200B2 (en) Method of producing electronic part with bumps and method of producing electronic part
US7604152B2 (en) Method for manufacturing a printed circuit board for electronic devices and an electronic device using the same
US20140212678A1 (en) Soldering device, soldering method, and substrate and electronic component produced by the soldering device or the soldering method
KR100279861B1 (en) Molded electronic component having pre-plated lead terminals and manufacturing process thereof
US6494361B1 (en) Semiconductor module package substrate fabrication method
US9149883B2 (en) Soldering device, soldering method, and substrate and electronic component produced by the soldering device or the soldering method
JP3119385B2 (en) Surface treatment method, surface treatment device and surface treatment liquid for electronic components and their electrode terminals
US6445075B1 (en) Semiconductor module package substrate
JP3400408B2 (en) Flip chip mounting method
US7159758B1 (en) Circuit board processing techniques using solder fusing
JP3124224B2 (en) Solder bump formation method
JP3872318B2 (en) Solder bump forming method and solder bump bonding structure
JPWO2006134891A1 (en) Module board soldering method
US6924440B2 (en) Printed wiring board, apparatus for electrically connecting an electronic element and a substrate, and method for manufacturing a printed wiring board
JP3980473B2 (en) Manufacturing method of electronic parts
JP3334728B2 (en) Electrode terminal of electronic component and surface treatment method of electrode terminal
JPH04297091A (en) Solder coated printed circuit board and its manufacturing method
JPH09191174A (en) Printed wiring board, method of manufacturing the same, and mounting structure of electronic component on printed wiring board
JPH0385750A (en) Semiconductor device and its mounting method
JP2594075B2 (en) Manufacturing method of square electronic components
JP2025077156A (en) Manufacturing method of circuit member having solder bumps and circuit member having solder bumps
JP2811112B2 (en) Solder supply plate
TWI328415B (en) Method for attachment of solder powder to electronic circuit board and solder-attached electronic circuit board

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees