JP3111725B2 - Dual gate semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a dual gate (double or multiple gate) structure suitable for an insulated gate bipolar transistor, a MOS controlled thyristor, and the like.

[0002]

2. Description of the Related Art A power semiconductor device which mainly performs switching operation and is used for power conversion and power control circuits is required to have a high withstand voltage and a small on-time voltage drop in order to minimize power loss. Therefore, thyristors and insulated gate bipolar transistors (IGBTs) with a conductivity modulation effect are suitable. . FIG. 7 shows a horizontal structure suitable for incorporating an IGBT into an output side of an integrated circuit as a conventional example of a semiconductor device suitable for the use according to the application.

An integrated circuit chip 10 shown in cross section in FIG.
The wafer is formed, for example, by growing an epitaxial layer to a predetermined thickness as an n-type semiconductor region 2 on which a circuit element including an IGBT is to be formed on a p-type semiconductor substrate 1.
The IGBT is usually formed by repeating its unit structure a plurality of times in the semiconductor region 2 and then connecting them in parallel. The figure shows this by a half-unit structure Uh. In an actual IGBT, the structure Uh is alternately and symmetrically repeated in the left-right direction of the figure.

In the left part of the figure, a p-type base layer 21, its p-type connection layer 22 and an n-type source layer 23 are diffused from the surface of the n-type semiconductor region 2 as shown in FIG. A gate 25 is provided on the surface of the base layer 21 between the semiconductor layer 2 and the semiconductor layer 2 via a thin gate oxide film 25a. twenty five
From the gate terminals G. On the right side of the figure, an n-type buffer layer 32 and a p-type drain layer 33 are diffused from the surface of the semiconductor region 2 as shown in the figure, and another main terminal T2 is formed from an electrode film 42 connected to the drain layer 33. Derived. p
The n-type base layer 21, the n-type semiconductor region 2 and the p-type drain layer 33 constitute one pnp transistor.
Is controlled by the potential applied to the gate 25 to perform an on / off operation.

That is, when a positive voltage is applied to the gate 25 from the gate terminal G, majority carriers e, which are electrons in this example, flow into the semiconductor region 2 from the source layer 23 through the n-type channel below the gate terminal G. The bipolar transistor is turned on by the base current, so that conduction between the main terminals T1 and T2 of the IGBT is conducted. Further, after such conduction, minority carriers h, which are holes, are injected into the semiconductor region 2 from the drain layer 33 through the buffer layer 32, so that the on-voltage between the main terminals T1 and T2 is reduced due to the conductivity modulation effect. It is much lower than in the case of MOSFET. Of course, in order to turn off the IGBT, the voltage of the gate 25 may be stopped to stop the majority carrier e from flowing into the semiconductor region 2. After the OFF operation, the depletion layer spreads in the semiconductor region 2 and a high breakdown voltage state is set.

[0006]

As described above, in the IGBT, on / off of the IGBT can be easily controlled by the insulated gate 25 having a high input impedance. Although there is an advantage that the on-voltage can be reduced, on the other hand, at the time of turn-off, it is necessary to sweep out a large number of minority carriers that have contributed to the conductivity modulation from the semiconductor region 2 to expand the depletion layer. And the turn-off time becomes considerably long, and the turn-off loss tends to increase accordingly.

The increase in the turn-off time is a major obstacle in applying the IGBT to a high-frequency circuit that requires high-speed on-off, and the increase in the turn-off loss drives an inductive load that generates a back electromotive force when the IGBT is off. This is particularly noticeable in the case where the IGBT for high frequency is used. To improve such turn-off characteristics, the impurity concentration of the buffer layer 32 may be increased to reduce the minority carriers injected from the drain layer 33 into the semiconductor region 2 during the OFF operation. This has its limitations as it has a negative effect. Also,
Platinum or the like can be introduced into the semiconductor region 2 as a so-called lifetime killer to promote the disappearance of carriers at the time of turn-off, but this also has a negative effect of increasing the on-voltage. The problems described above for IGBTs are substantially the same for thyristors having self-turn-off capability such as GTO.

An object of the present invention is to solve such a problem,
An object of the present invention is to improve the turn-off characteristics of a semiconductor device without diminishing the effect of improving the forward characteristics at the time of on using the conductivity modulation action.

[0009]

According to the present invention, there is provided a semiconductor device comprising, for example, an n-type semiconductor region, a p-type base layer diffused from a surface thereof, and a substrate layer.
An n-type source layer selectively diffused into the surface layer of the semiconductor layer, a main gate disposed above the base layer between the source layer and the semiconductor region, and a p-type diffused adjacent from the surface of the semiconductor region. It has a dual gate structure including a drain layer and an injection layer, and a sub gate disposed above the drain layer and the injection layer. The first main terminal is derived from the source layer and the second main terminal is derived from the drain layer. The control terminals are led out from the gates, and when turned on, the majority of carriers flow from the source layer into the semiconductor region while the channels under the main and sub gates are both conductive, and the minority carriers are injected from the injection layer and conducted there. At the time of off-operation, the channel under the sub-gate is turned off to stop injection of minority carriers from the injection layer into the semiconductor region, and then the channel under the main gate is turned off. It is accomplished by turning off the semiconductor device to the panel in a non-conducting state. In addition,
Of course, the n-type and the p-type in the above may be interchanged, and in some cases, the majority carrier and the minority carrier may be interchanged.

When the semiconductor device is of a horizontal type, the above-mentioned main gate and sub-gate are preferably provided on the same surface as the semiconductor region, and in this case, the injection layer is preferably provided on the main gate side with respect to the drain layer. . When the semiconductor device is of a vertical type, a base layer, a source layer, and a main gate are provided on one surface side of the semiconductor region, and a drain layer, an injection layer, and a sub-gate are provided on the other surface side. In any case, a connection layer of a conductivity type opposite to that of the drain layer is provided on the sub-gate or the second main terminal side so as to cover the drain layer from the outside except for the end portion on the side of the injection layer, and the second connection layer is formed from the drain layer and the connection layer. Deriving the main terminal is advantageous for shortening the turn-off time, and forming a Schottky junction between the electrode film for deriving the second main terminal from the drain layer and the surface of the semiconductor region in contact with the drain layer improves the withstand voltage. It is advantageous. Further, in the case of a horizontal structure, it is advantageous to improve the breakdown voltage by diffusing the buffer layer to have the same conductivity type as the semiconductor region and to cover the injection layer and the drain layer, particularly the former, from the outside or below.

The present invention can be applied not only to IGBTs but also to thyristors. In the case of application to MOS control thyristors, another source layer is diffused into the surface portion of the source layer in a conductivity type opposite to that of the source layer. The main gate is preferably disposed so as to cover the source layer and the base layer between them from above. When the present invention is applied to an electrostatic induction thyristor,
The first main terminal layer of the same conductivity type is diffused from the surface of the semiconductor region on the main gate side, and the main gate layer of the opposite conductivity type to the semiconductor region is diffused deeper than the first main terminal layer so as to sandwich it from both sides; When the channel under the sub-gate is turned on during conduction, majority carriers flow into the semiconductor region from the first main terminal layer and minority carriers are injected from the injection layer. At turn-off, the channel under the sub-gate is turned off. Then, a voltage is applied to the main gate layer to spread a depletion layer from both sides to the semiconductor region below the first main terminal layer so as to pinch off the current.

[0012]

The present invention focuses on the fact that the cause of the prolonged turn-off is that the injection of minority carriers from the drain layer into the semiconductor region does not stop after the start of the off operation.
The injection layer is provided so as to be able to be separated from the drain layer by the sub-gate, and minority carriers are injected from the injection layer connected to the drain layer when on, but before the turn-off starts, the injection layer is separated from the drain layer and minority carrier injection is performed. Stop it.

That is, the base gate and the source layer diffused from the surface of the semiconductor region and the main gate disposed on the base layer are provided on the side of the conventional gate, which is the main gate referred to in the structure of the preceding paragraph. Same as the conventional case, but in the present invention, the injection layer is diffused with the same conductivity type adjacent to the conventional drain, a sub-gate is provided between them, and the channel below the sub-gate is made conductive when on. Injects minority carriers from the injection layer into the semiconductor region in a state where the conductivity modulation occurs, and shuts off the channel below the main gate at turn-off
Prior to this, the channel under the sub-gate is rendered non-conductive to cut off the injection of minority carriers, thereby reducing the number of carriers to be swept out when expanding the depletion layer in the semiconductor region. In the semiconductor device having the dual gate structure of the present invention, the off operation is promoted, the turn-off time can be reduced to half, and the turn-off loss can be reduced to a fraction of the conventional value.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention shown in FIGS. 1 to 6 will be described below. 1 to 4 show an IGBT according to the present invention, and FIG.
FIG. 6 is a partial cross-sectional view showing an embodiment applied to a control thyristor (hereinafter referred to as MCT). Each of the semiconductor devices is constructed by repeating a unit structure a plurality of times. In the figure, the unit structure is indicated by U, and the half-unit structure is indicated by Uh.

In the embodiment of FIG.
In this example of 10 or wafer, on a p-type semiconductor substrate 1
The n-type semiconductor region 2 is, for example, 10¹⁵Atom / cm^ThreeImpurity concentration
Epitaxial growth. The structure in the left half of the figure is the front
7 is the same as the conventional structure of FIG.
From p-type substrate layer 21¹⁷Atom / cm^ThreeOf degree
The impurity concentration is diffused to a depth of 2 to 5 μm, and the example shown in FIG.
Then, a p-type connection layer 22 is¹⁹Atom / cm^ThreeOf degree
After diffusion to a depth of, for example, 1 μm with a high impurity concentration,
N-type source layer 23 so as to straddle source layer 21 and connection layer 22.
To 10¹⁹Atom / cm ^ThreeWith the above high impurity concentration, for example, 0.3-0.
Diffuses shallowly to a depth of 5 μm. Main gate 25 to source layer 23
To cover the surface of the base layer 21 between the semiconductor region 2 and
Disposed via the gate oxide film 25a and the source layer 23.
An aluminum electrode film 41 connected to the connection layer 22 is provided to form a first main end.
Let it be a child T1. Note that this left part is
May omit the connection layer 22.

In the right half of the figure, the n-type connection layer 32 is first formed from 10 ¹⁸ to 10 ¹⁹ atoms / cm 2 from the surface of the semiconductor region 2 in this embodiment.
After it diffused to a depth of 2~3μm an impurity concentration of ^3, the present invention diffuses by adjacent implanted layer 34 and the drain layer 33 of p-type. Both layers 33 and 34 may be diffused simultaneously with the above-mentioned connection layer 22 and with the same impurity concentration and depth. The injection layer 34 is disposed closer to the main gate 25 than the drain layer 33 in the horizontal structure of this embodiment. Set up. Further, a sub-gate 35 is provided on the surface of the semiconductor region 2 between the drain layer 33 and the injection layer 34 via a gate oxide film 35a, and the connection layer 32 is formed.
And an electrode film 42 connected to the drain layer 33 and the second main terminal
T2. Although the connection layer 32 is not always necessary on the second main terminal T2 side, it is desirable to provide the drain layer 33 so as to cover the drain layer 33 from below except for the end portion on the injection layer 34 side as shown in the figure.

The semiconductor device according to the present invention configured as described above has a dual-gate structure including a main gate 25 and a sub-gate 35 controlled by control terminals G1 and G2, respectively. The potential is applied to make the n-type channel below the main gate 25 conductive, and the control terminal G2
Is applied with a negative potential to make the p-type channel below the sub-gate 35 conductive. As a result, majority carriers e or electrons flow from the source layer 23 connected to the first main terminal T1 to the semiconductor region 2 through the channel below the main gate 25, and this is used as a base current to make the base layer 21 and the semiconductor region 2 And a bipolar transistor comprising an injection layer 34 conducts first, and further a second transistor through the drain layer 33 and the channel below the sub-gate 35.
Since minority carriers h or holes are injected into the semiconductor region 2 from the injection layer 34 connected to the main terminal T2, conduction between the main terminals T1 and T2 is conducted at a low on-voltage by the conductivity modulation action.

In order to turn off the dual gate type IGBT, immediately before that, the control terminal G2 is set to the same potential or the positive potential with respect to the second main terminal T2, and the channel below the sub-gate 35 is turned off. Above, the control terminal G1 is set at the same potential as the first main terminal T1, and the channel below the main gate 25 is turned off. During this turn-off operation, it is necessary to sweep out the carriers in order to spread the depletion layer in the semiconductor region 2, but before that, the injection of the minority carriers h from the injection layer 34 is cut off, and the conductivity modulation action is weakened. Therefore, in the present invention, the number of carriers to be swept out at this time can be reduced much more than in the prior art, and the turn-off operation can be promoted.

The dual-gate semiconductor device of the embodiment shown in FIG. 1 has a lateral structure, and the measured turn-off time varies depending on the current capacity, but it is as short as about 20 to 100 ns compared to the conventional 0.1 to 1 μS. Reduces the turn-off loss for inductive loads by a factor of or less. To obtain this effect, the timing at which the channel below the sub-gate 35 is turned off prior to turn-off depends on the current capacity, but is preferably set to 0.1 to several μS , usually about 1 μS . After the injection layer 34 is separated from the drain layer 33, minority carriers h may be injected into the semiconductor region 2 from the latter, but the degree is much smaller than in the past. Furthermore, by covering the p-type drain layer 33 from below with the n-type connection layer 32 having a high impurity concentration as in this embodiment, the possibility of injection of the minority carrier h can be substantially eliminated.

In the embodiment shown in FIG. 2, the n-type semiconductor substrate of the chip 10 is used as the semiconductor region 2 and the main gate 25 is provided on one surface and the sub-gate 35 is provided on the other surface. The dual gate semiconductor device has a vertical structure. The structure on the upper side of the figure is the same as that of FIG. 1 except that the main gate 25 is formed wide so as to cover the surface of the adjacent base layer 21 and each other. The lower side of the sub-gate 35 is shown in FIG.
Of course, the same structure as that of FIG. 1 may be used. However, in the embodiment of FIG.
33 and a contact surface side of an electrode film 42 connected to the surface of the semiconductor region 2 between them is made of a Schottky barrier film such as molybdenum.
The electrode film 42 is connected to the semiconductor region 2 via a Schottky junction as 42a. Arranging the sub-gate 35 on the space between the drain layer 33 and the injection layer 34 is the same.

In the embodiment shown in FIG.
, The minority carriers are injected into the semiconductor region 2 to reduce the on-voltage between the main terminals T1 and T2 by the conductivity modulation, and the channel below the sub-gate 35 is turned off immediately before the turn-off to promote the turn-off operation. The points are the same as the embodiment of FIG. Although this embodiment is not very suitable for an integrated circuit, it has the advantage that the unit structure U can be made smaller than the horizontal structure when applied to vertical individual elements. Since the Schottky junction of this embodiment has a problem of reverse leakage current at the time of off, the mutual interval between the pair of drain layers 33 is set to be narrow, and after the semiconductor region 2 near the junction is turned off, the depletion layer is expanded. It is better to put it in a pinch-off state.

The embodiment shown in FIG. 3 has a horizontal structure as in FIG. 1, but an n-type buffer layer 31 is provided on the sub-gate 35 side. This buffer layer 31 is diffused at an impurity concentration of about 10 ¹⁶ atoms / cm ³ to a depth of about 5 μm, for example, and a connection layer 32, a drain layer 33 and an injection layer 34 are diffused inside as shown in the figure. In this embodiment, when the impurity concentration of the semiconductor region 2 is reduced to increase the breakdown voltage, or when the distance between the base layer 21 and the injection layer 34 is reduced to reduce the size, a depletion layer is formed in the entire region of the semiconductor region 2 when off. Spread through and occurrence of punch-through can be stopped by the buffer layer 31 to increase the breakdown voltage.

However, the buffer layer 31 in the embodiment of FIG. 3 is slightly disadvantageous in injecting minority carriers from the injection layer 34 into the semiconductor region 2 when turned on. If it does not flow, the injection of minority carriers is unlikely to occur, and negative resistance characteristics may be exhibited immediately after the start of conductivity modulation. For this reason, in the next embodiment of FIG. 4, the buffer layer 31 is used for the drain layer 33 and the injection layer as shown in FIG.
Separately for 34. In the structure of this embodiment, since the high-resistance semiconductor region 2 exists between the drain layer 33 and the injection layer 34, when the majority carriers in the semiconductor region 2 flow toward the second main terminal T2, the high-resistance range The injection of minority carriers from the injection layer 34 can be promoted by the potential drop generated therein, the conductivity modulation is caused by the influx of the minority carriers, the on-voltage is reduced, and undesirable negative resistance characteristics can be prevented. In this embodiment, the buffer layer on the drain layer 33 side is used.
It is also possible to omit 31 as appropriate, or to have the connection layer 32 act for it.

In the embodiment shown in FIG. 5, the present invention is applied to an MCT. As is well known, this thyristor is a MOS
The gate can be controlled to be turned off by itself. Therefore, the n-type source layer 23 in the p-type base layer 21 on the side of the main gate 25 is more deeply diffused than in the embodiment of FIG. After another source layer 24 is diffused shallowly with a high impurity concentration, a main gate 25 is provided so as to cover the surface of the source layer 23 and the base layer 21 between the another source layer 24 and the semiconductor region 2.
The electrode film 41 for the first main terminal T1 is connected to both the source layers 23 and 24. The sub-gate 35 side may be, for example, the same as that of the embodiment of FIG. 4, but in the example of FIG.
In order to not cover the channel forming portion under the sub-gate 35, the pattern 31 is diffused in a smaller pattern than in the case of FIG. 4, and has a simple structure in which the connection layer 32 of FIG. 4 is omitted.

In order to turn on the MCT shown in FIG. 5, a positive potential is applied to the main gate 25 to make the channel on the surface of the base layer 21 therebelow conductive so that majority carriers flow from the source layer 23 into the semiconductor region 2. . At the same time, the channel under the sub-gate 35 is made conductive, and minority carriers are injected from the injection layer 34 to cause conductivity modulation in the semiconductor region 2 as before. At the time of turn-off, the channel below the sub-gate 35 is turned off immediately before that, and then a negative potential is applied to the main gate 25 to cut off the channel on the surface of the base layer 21 and cut off the supply of majority carriers to the semiconductor region 2. At the same time, the channel on the surface of the source layer 23 is made conductive, and the excess carriers remaining in the base layer 21 are pulled out to the first main terminal T1 via another source layer 24, thereby turning off the MCT. The point that the turn-off time can be reduced and the turn-off loss can be reduced by the present invention is the same in this embodiment.

In the embodiment shown in FIG. 6, the present invention is applied to a thyristor of an electrostatic induction type. This embodiment preferably has a vertical structure, and the sub-gate 35 having the same structure as that of FIG. 1 is disposed on the back side of the semiconductor substrate or the semiconductor region 2 of the chip 10 in the illustrated example. The surface side of the semiconductor region 2 is the main gate side, and the same n-type first main terminal layer 26 is diffused from the surface to a depth of about 0.5 μm with a high impurity concentration of 10 ¹⁹ atoms / cm ³ or more and a depth of about 0.5 μm. As shown in the figure, the p-type main gate layer 27 is diffused as deep as several to 10 μm with an impurity concentration of about 10 ¹⁸ atoms / cm ³ so as to sandwich it from both sides as shown in FIG.
A first main terminal T1 and a control terminal G1 are derived from 43, respectively.
On the back side, a second main terminal T2 and a control terminal G2 are respectively derived from an electrode film 42 and a sub-gate 35 connected to the connection layer 32 and the second main terminal layer 33 corresponding to the drain layer in FIG.

In this electrostatic induction type thyristor, majority carriers flow from the first main terminal layer 26 into the semiconductor region 2 and minority carriers from the injection layer 34 in a state where the channel below the sub-gate 35 is turned on when turned on. Carriers are injected to lower the on-voltage by conductivity modulation.
After the lower channel is turned off to stop the injection of minority carriers from the injection layer 34, the main gate layer 27 is placed at a negative potential and the semiconductor region 2 below the first main terminal layer 26 is placed from both sides. The depletion layer is spread to pinch off the majority carrier flow path. Thus, the stop of the injection of minority carriers and the promotion of the turn-off according to the present invention are the same in the embodiment of FIG.

As can be seen from the above-described embodiments, the present invention can be applied to a semiconductor device utilizing conductivity modulation in various modes. The embodiment is merely an example, and the present invention can be implemented by combining various modified embodiments and embodiments. In the embodiment, the semiconductor region 2 is of the n-type, but may be of the p-type, and the present invention can be carried out even when the majority carrier and the minority carrier are exchanged.

[0029]

According to the present invention, attention is paid to the fact that it takes a long time for the turn-off operation of the semiconductor device because the injection of minority carriers from the drain layer into the semiconductor region does not stop even after the start of the off-operation. Is a dual gate type with a main gate and a sub gate, and an injection layer for minority carriers is provided so that the connection to the drain layer can be separated by the sub gate, and minority carriers are injected from the injection layer connected to the drain layer when on. Then, the injection layer is separated from the drain layer and the turn-off operation is started in a state in which the injection of minority carriers is stopped, so that in the on state, the advantage of reducing the on-voltage by the conductivity modulation action in the semiconductor region is maintained. However, at the time of turn-off, the number of carriers to be swept out to expand the depletion layer in the semiconductor region is reduced, and the Futaimu below half, thereby reducing the respective turn-off loss to a fraction less.

The present invention can be applied to semiconductor devices using conductivity modulation such as the above-mentioned insulated gate bipolar transistor, MOS control thyristor, electrostatic induction thyristor and the like in a wide variety of forms. The present invention can be applied to a semiconductor device having a current capacity to reduce switching loss, increase power conversion efficiency, shorten turn-off time, and contribute to expansion of an applicable frequency range.

[Brief description of the drawings]

FIG. 1 is a sectional view of an embodiment in which a dual gate semiconductor device according to the present invention is applied to a horizontal insulated gate bipolar transistor.

FIG. 2 is a sectional view of an embodiment in which the present invention is applied to a vertical insulated gate bipolar transistor.

FIG. 3 is a sectional view of another embodiment in which the present invention is applied to a horizontal insulated gate bipolar transistor.

FIG. 4 is a sectional view of still another embodiment in which the present invention is applied to a horizontal insulated gate bipolar transistor.

FIG. 5 is a sectional view of an embodiment in which the present invention is applied to a MOS control thyristor.

FIG. 6 is a sectional view of an embodiment in which the present invention is applied to an electrostatic induction thyristor.

FIG. 7 is a cross-sectional view of a conventional horizontal insulated gate bipolar transistor.

[Explanation of symbols]

 2 Semiconductor region 10 Semiconductor device chip 21 Base layer 23 Source layer 24 Another source layer 25 Main gate 26 First main terminal layer 27 Main gate layer 31 Buffer layer 32 Connection layer 33 Drain layer or second main terminal layer 34 Injection layer 35 Sub-gate 42a Schottky barrier film e majority carrier or electron h minority carrier or hole G1 control terminal for main gate G2 control terminal for sub-gate T1 first main terminal T2 second main terminal U Unit structure of semiconductor device Uh semiconductor Device half-unit structure

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 29/749

Claims (6)

(57) [Claims] 1. A semiconductor region of one conductivity type, a substrate layer of the other conductivity type diffused from a surface of the semiconductor region ,
A source layer of one conductivity type selectively diffused into the surface layer of the substrate layer; a main gate disposed above the substrate layer between the source layer and the semiconductor region; A drain layer and an injection layer of the other conductivity type, which are diffused adjacent to each other, and a sub-gate disposed on the upper side between the drain layer and the injection layer; A second main terminal is led out from the drain layer, and a control terminal is led out from the main gate and the sub-gate, respectively. Dual gate, characterized in that carriers are injected, minority carriers are injected from the injection layer, the channel below the sub-gate is turned off, and the channel is turned off. Conductor device. 2. The device according to claim 1, wherein a substrate, a source layer, and a main gate are provided on one surface side of the semiconductor region, and a drain layer, an injection layer, and a sub gate are provided on the other surface side. A dual-gate semiconductor device, characterized in that: 3. The device according to claim 1, further comprising: a connection layer of one conductivity type covering the drain layer from the outside except for the injection layer side end, and leading the second main terminal from the drain layer and the connection layer. A dual-gate semiconductor device. 4. The dual gate semiconductor device according to claim 1, wherein one conductivity type buffer layer which covers the injection layer from the outside is diffused. 5. The dual gate semiconductor device according to claim 1, wherein an electrode film for leading the second main terminal from the drain layer is Schottky-bonded to the surface of the semiconductor region. 6. The device according to claim 1, wherein another source layer of the other conductivity type is diffused in a surface portion of the source layer,
A dual gate semiconductor device, wherein a main gate is disposed above a source layer and a substrate layer between another source layer and a semiconductor region.