JP3184363B2 - Microprocessor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor unit (MPU) having a look-ahead mechanism for fetching an instruction at the next address without waiting for the end of execution of the instruction.

[0002]

2. Description of the Related Art With the development of LSI technology, a computer system is mounted on one LSI, and a central processing unit (CPU) is mounted on a so-called custom LSI according to customer specifications. Microprocessor unit (MPU) is used. Also, in recent years, the amount of information to be processed by the MPU is increasing, and therefore, the MPU is required to have a higher speed.

[0003] A so-called look-ahead is considered as one method for increasing the speed. Prefetching refers to fetching an instruction stored at an address subsequent to the address at which the instruction being executed is stored without waiting for the end of the execution of the instruction in the MPU, and immediately following the end of the execution of the instruction being executed, This is a method that is prepared so that execution of an instruction can be started.

Here, the address at which the instruction to be read is stored is managed by a program counter. When one instruction is read using the program counter as an address, the program counter is incremented to indicate the next address. That is, as shown in FIG. 3, the value PC of the program counter is sequentially incremented by one in synchronization with the clock CLK.

[0005]

Incidentally, the MPU is usually provided with an interrupt mechanism. This interrupt mechanism is a function of interrupting the execution of the routine currently being processed upon receiving a predetermined interrupt, and branching to the address where the interrupt routine is stored. If there is an interrupt in the MPU having the look-ahead function, the instruction read by the look-ahead is discarded without being executed at the stage when the currently executing instruction is completed, and the process branches to the interrupt routine. However, since the value of the program counter is already incremented and indicates the address next to the address where the prefetched instruction is stored, after the execution of the interrupt routine is completed, the discarded instruction is read again. It is necessary to decrement the value of the program counter when branching to the interrupt routine.

That is, as shown in FIG.
If the interrupt signal INT_ is asserted (L level) while the instruction stored in the address β is being executed, that is, while the instruction stored in the address β is being read, the instruction stored in the address β is read. In response to this, the value of the program counter is changed to β + 1. However, in response to the assertion of the interrupt signal INT_, after the execution of the instruction at the address β−1, the prefetched instruction at the address β is executed. Instead, branch to the interrupt routine. Therefore, the value β + 1 of the program counter is decremented and returned to β, and then this value β is saved. After the interrupt routine is completed, this value β is returned to the program counter, and the instruction stored in the address β is read again. Need to do it.

Therefore, when the look-ahead mechanism is provided, it is necessary to provide a computing unit for decrementing the value of the address counter once incremented again, and perform such a useless operation of incrementing and decrementing. This is disadvantageous in terms of the processing speed of the MPU and the circuit scale. The present invention has been made in view of the above circumstances, and in a microprocessor device having a look-ahead mechanism, a microprocessor device in which a useless operation such as increment and decrement is eliminated, thereby improving a processing speed and reducing a circuit scale. The purpose is to provide.

[0008]

According to a first aspect of the present invention, there is provided a microprocessor device for sequentially reading and executing a plurality of instructions stored in a predetermined memory area. A prefetch mechanism for prefetching the next instruction stored at the second address following the first address at which the currently executed instruction is stored; (2) the prefetch mechanism for reading the last instruction currently read Program counter indicating the address next to the storage address (3) In response to the occurrence of a predetermined condition, the instruction read destination is
A branch mechanism for branching to a third address different from the second address; (4) a register in which the second address is stored when an instruction is read; and (5) a register in which the second address is stored in the register. 2 according to the occurrence of the predetermined condition,
Pass through the second address as it is, or
And an incrementer for incrementing the address and sending the incremented address to the program counter.

Here, in the microprocessor device of the present invention, the program counter and the register may be constituted by latches which operate with clocks having different phases. The above-mentioned "predetermined condition" refers to all or a part of conditions that need to return to the original routine after branching, such as generation of an interrupt or execution of a branch instruction to a subroutine (for example, only "interrupt"). ).

The function (5) of “passing the second address as it is” of the incrementer may be a function of directly passing the inside of the circuit of the incrementer. What is included may be referred to as an incrementer according to the present invention.

[0011]

The microprocessor unit (MPU) of the present invention
Stores an address (second address) at the time when an instruction is read out in a register, and when no predetermined condition such as an interrupt occurs, the second address stored in the register is stored. Is incremented and stored in the program counter, and when a predetermined condition occurs, the second address stored in the register is stored in the program counter as it is. In addition, there is no need to perform a useless operation of incrementing and decrementing, which was necessary in the case of a method of uniformly incrementing the contents of the program counter, and therefore, an arithmetic unit for decrementing is unnecessary, and the processing speed is reduced. Improvement and reduction in circuit scale can be achieved.

The MPU of the present invention is particularly effective when the program counter and the register are constituted by latches.

[0013]

Embodiments of the present invention will be described below. FIG. 1 is a schematic configuration diagram showing an address generation circuit of an MPU according to one embodiment of the present invention, and FIG. 2 is a timing chart showing an operation sequence thereof. As shown in FIG. 1, the address generation circuit of the MPU includes a register 12 on the output side of the program counter 11. This register 12
As shown in FIG. 2, is configured by a latch that operates on the clock CK2 among the two-phase clocks CK1 and CK2 generated from the clock CLK, and the clock CK2 is
The data is input to the register 12 via the gate 13. The gate 13 allows the clock CK2 to pass when there is no interrupt in the instruction fetch cycle and when there is no interrupt even in the case of no instruction fetch cycle or even in the case of the instruction fetch cycle.
Cut off K2.

On the output side of the register 12, an incrementer 14 is provided, and the output of the incrementer 14 is stored in the program counter 11. The incrementer 14 is controlled by whether or not there is an interrupt. When there is no interrupt, the output of the register 12 is incremented and transmitted to the program counter 11, and when there is an interrupt, the output of the register 12 is not incremented. It is transmitted to the program counter 11 as it is.

The program counter 11 is constituted by a latch which operates by the clock CK1 of the two-phase clocks CK1 and CK2 shown in FIG. As shown in FIG. 2, the content PC = γ of the program counter 11 is output as the address A, and the interrupt signal INT_ is asserted (L level) while the instruction stored at the address A = γ is being read. And When the instruction stored at the address A = γ is being read, the clock pulse A of the clock CK2 passes through the gate 13 because the interrupt signal INT_ has not been received yet, and the content PCB of the register 12 is changed to γ. , Clock CK1
The content PC of the program counter 11 is rewritten to γ + 1 by the clock pulse B. Interrupt signal INT
_ Is accepted, the next clock pulse C of the clock CK2 is cut off by the gate 13 and is not input to the register 12, so that the content PCB of the register 12 becomes P
CB = γ. In addition, upon receiving this interrupt, the incrementer 14 enters a through state in which the input is passed as it is. Therefore, the content PCB = γ of the register 12 is stored in the program counter 11 by the clock pulse D of the clock CK1. Then, program counter 1
The content PC = γ of 1 is saved, and the process branches to a predetermined interrupt routine.

As described above, the MPU of the above embodiment has the register 12 for storing the contents of the program counter at the time of fetching an instruction, and when there is an interrupt, the value stored in this register is used as it is for the program counter 11.
With this configuration, there is no need to provide a computing unit for decrementing the contents of the program counter 11, and useless computation of incrementing and decrementing can be avoided.

Although the above embodiment has been described by taking an interrupt as an example, the same configuration may be applied to, for example, a branch to a subroutine.

[0018]

As described above, the microprocessor device of the present invention stores an address in a register when an instruction is read, and when a predetermined condition such as an interrupt does not occur, the microprocessor stores the address in a register. A second address stored in the register is incremented and stored in the program counter, and when a predetermined condition occurs, the second address stored in the register is directly stored in the program counter. As a result, a useless operation of incrementing and decrementing is avoided, an arithmetic unit for decrementing the contents of the program counter becomes unnecessary, and the processing speed is improved and the circuit size is reduced.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an address generation circuit of an MPU according to one embodiment of the present invention.

FIG. 2 is a timing chart showing an execution sequence of the address generation circuit shown in FIG.

FIG. 3 is a timing chart showing a change in a value of a program counter when there is no interrupt;

FIG. 4 is a timing chart showing a change in a value of a program counter when an interrupt occurs.

[Explanation of symbols]

 11 Program counter 12 Register 13 Gate 14 Incrementer

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-115133 (JP, A) JP-A-52-5231 (JP, A) JP-A-1-189728 (JP, A) JP-A-4-115 363726 (JP, A) JP-A-57-94854 (JP, A) JP-A-57-197654 (JP, A) JP-A-57-5156 (JP, A) JP-A-6-301531 (JP, A) Masashi Takahashi et al. “Exception handling method for high-performance 16-bit microcontroller core for control” IEICE Technical Report, Vol. 91, NO. 293 (ED91 92-99) (1991) p. 9-14 (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 9/30-9/42 G06F 9/46

Claims (3)

(57) [Claims] 1. A microprocessor device for sequentially reading and executing a plurality of instructions stored in a predetermined memory area, wherein, during execution of an instruction, a first address following a first address at which a currently executed instruction is stored. A prefetch mechanism for prefetching the next instruction stored at the address 2; a program counter for indicating the address next to the storage address of the last read instruction at the current time; A branch mechanism for branching an instruction read destination to a third address different from the second address, a register storing the second address when the instruction is read, and The stored second addresses are respectively stored in the second address according to the presence / absence of the predetermined condition.
The second address is incremented, and the incremented second address is sent to the program counter. 2. The microprocessor device according to claim 1, wherein said program counter and said register are constituted by latches operated by clocks having mutually different phases. 3. The microprocessor device according to claim 1, wherein said predetermined condition is an interrupt.