JP3176021B2 - Liquid crystal light valve and projection type liquid crystal display using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display which controls the intensity of light with the amplitude of a voltage, and more particularly to a liquid crystal light valve suitable for a projection type display.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display in which light is controlled by laminating switching elements and liquid crystal is disclosed in US Pat. No. 3,862,360 and IE80-81 of the Technical Report of the Institute of Electronics and Communication Engineers (1980). Have been. Each of these displays is a direct-view system in which an image controlled by a switching element is directly viewed. The switching element includes an MO formed on a single crystal silicon substrate.
An S (metal oxide-semiconductor) transistor is used.

When light is irradiated on a MOS transistor,
A photocurrent is generated at the PN junction forming the source and the drain. When this photocurrent is generated in the switching element for controlling the liquid crystal, the voltage applied to the liquid crystal changes, deteriorating the image quality. Further, when a photocurrent flows through the switching element and the drive circuit unit that controls the switching element, a phenomenon called latch-up is caused, a large current flows into the power supply, and the operation of the circuit is inhibited and the chip is broken.

[0004] FIG. 15 is a diagram for explaining a latch-up phenomenon.
1 shows a schematic diagram of a MOS LSI. PMO on the surface of n-type substrate
S and NMOS are formed in the region of the p well. The substrate is connected to VDD (for example, +5 V) through an n + diffusion layer,
The well is connected to VSS (for example, GND) via a p + diffusion layer.
To each other. The sources of the PMOS and NMOS transistors are respectively connected to VDD and VSS, the gate is commonly connected to the input terminal Vin, and the drain is also commonly connected to the output terminal Vout to form an inverter circuit.

In this CMOS LSI, the parasitic bipolar transistors Tr1 and Tr2 and the parasitic resistors R1 to R1 are connected.
R4 is done. Tr1 has an NMOS source as an emitter,
An npn transistor having a p-well as a base and a substrate as a collector, Tr2 has a PMOS source as an emitter,
This is a pnp transistor having a substrate as a base and a p-well as a collector. R1 and R2 are p wells, R3 and R
Reference numeral 4 denotes a resistance formed by the volume resistance of the substrate.

[0006] Parasitic bipolar transistors Tr1, T
r2 has a thyristor structure as shown. When the terminal voltage is increased by the trigger current Ip flowing through the parasitic resistance R1 or R4, the parasitic npn or pnp bipolar transistor is turned on, and the on-current rapidly increases through the parasitic resistance R1 or R4, and VDD and VSS are increased. During this time, a large current flows and latch-up occurs. This latch-up phenomenon causes the voltage inside the circuit to decrease, hindering the circuit operation, and melting the wiring and the silicon substrate to destroy the chip.

The trigger current causing latch-up is caused by light irradiation around the MOS transistor in addition to power supply noise. The electrons or holes generated in the substrate by the light irradiation move to the PN junction between the substrate and the p-well of the high electric field and become a photocurrent Ip. The photocurrent Ip flows between the n + diffusion layer of the substrate and the p + diffusion layer of the p well, and becomes a trigger current of the thyristor structure.

In the above technical report of the IEICE,
In order to reduce the photocurrent generated in the MOS transistor and prevent latch-up, in the switching region of the semiconductor substrate, the source region of the MOS transistor is arranged as far as possible from the light incident region, and a stopper diffusion for recombining generated carriers. It describes how to provide layers.

[0009]

A conventional liquid crystal display using a MOS transistor is of a direct-view type, and the light resistance required for a display panel is at most tens of thousands lux. However, in a projection-type display, since a control image is enlarged and projected on a screen, the light applied to the liquid crystal light valve reaches several million lux. For this reason, the conventional light-shielding structure is not sufficient, and a structure that completely covers the semiconductor substrate with respect to incident light is required. Further, it is necessary to improve the light resistance of not only the switching region for controlling the image but also the driving circuit portion and the like arranged around the switching region.

[0010] The object of the present invention, in view of such a current situation,
It is an object of the present invention to provide a highly reliable liquid crystal light valve capable of improving light-shielding properties against strong irradiation light and preventing latch-up.

Another object of the present invention is to provide a projection type liquid crystal display which displays a high quality image with a brightness of about 5 million lux.

[0012]

According to the present invention, there is provided a liquid crystal light valve which has, on one surface, a pixel circuit region comprising a plurality of switching elements arranged in a matrix and an element for driving the switching elements. A semiconductor substrate having a drive circuit region consisting of: and a peripheral region thereof; a plurality of metal layers having wiring means arranged hierarchically on the one surface of the semiconductor substrate via an insulating layer; The resulting metal layer is formed by dividing it with a slit,
A plurality of reflective electrodes serving as output terminals of the switching element, and a first metal layer under the uppermost portion, the first upper electrode being formed so as to overlap with a plane space of the uppermost slit.
Light shielding means, a second light shielding means in which at least one of the metal layers is formed so as to cover a surface space of the drive circuit area and the peripheral area, and a reflection electrode on a surface opposite to light irradiation. A transparent counter substrate having a counter electrode facing the substrate, and filling a gap between the semiconductor substrate and the counter substrate with liquid crystal.

Further, the metal layer is provided with a metal silicide layer such as WSi ₂ or MoSi ₂ on at least one of the upper surface and / or the lower surface.

[0014] Further, there is provided a carrier absorbing means which is formed in the peripheral region of the pixel circuit region or the drive circuit region of the semiconductor substrate and absorbs carriers generated by light irradiation.

Another means is provided at an uppermost portion in an area corresponding to a peripheral area of the pixel circuit area, and means for keeping the opposite electrode and the other electrode at the same voltage is provided.

[0016]

The light shielding means provided in the peripheral area, together with the reflective electrode, emits millions of lux of light or stray light applied to the pixel circuit area, the drive circuit area and their peripheral areas.
It has light resistance that reflects or absorbs almost completely, and can prevent a latch-up phenomenon that occurs on a semiconductor substrate, and has an effect of preventing deterioration in image quality due to deterioration and damage of circuit elements. This reflection / absorption function is further enhanced by the metal silicide layer.

Further, the carrier absorbing means provided in the peripheral region can absorb the carriers generated by the light reaching the semiconductor substrate, so that the photocurrent in the drive circuit region and the peripheral region can be greatly reduced, and In combination with increases the light resistance.

Another electrode that reflects light around the pixel circuit area is set to the same potential as the counter electrode, that is, 0.
Since the brightness around the screen can be reduced, the image quality can be improved.

Furthermore, since the light shielding means can be formed over a plurality of metal layers, the semiconductor substrate can be made compact.

By applying such a liquid crystal light valve, a high-definition and bright light source of about 5 million lux can be obtained.
A projection display that displays a high-quality image can be provided.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 9 shows a general circuit configuration of a liquid crystal light valve. The liquid crystal light valve includes a pixel circuit 1, a sample circuit 2, a horizontal scanning circuit 3, a vertical scanning circuit 4, and an AND gate 5. These circuits are formed on the surface of the semiconductor substrate.

In the pixel circuit 1, M MOS transistors 1a and storage capacitors 1b are arranged in the horizontal direction and N in the vertical direction. The scanning signals Vg1 to Vg from the AND gate 5 are applied to the gate electrode of the MOS transistor 1a.
N, the luminance signal V from the sample circuit 2 is applied to the drain electrode.
One end of the storage capacitor 1b and the liquid crystal 1c are connected to d1 to VdM and the source electrode. The other end of the storage capacitor 1b is connected to a voltage VSS for supplying a substrate voltage via a light shielding layer.
The liquid crystal 1c is an equivalent capacitance of a liquid crystal element mounted between the pixel circuit 1 and the opposing substrate.

The horizontal scanning circuit 3 receives the clock signal CLK and the start signal STA, and inputs an M-phase multiphase signal PH1.
~ PHM is output. The sample circuit 2 is constituted by a MOS switch, and its gate electrode is connected to the output signals PH1 to P1.
The HM and the drain electrode are connected to video signals VI1 or VI2 having different polarities. The luminance signals Vd1 to VdM are output from the source electrode of the MOS switch.

The vertical scanning circuit 4 receives the clock signal CKV and the start signal FST, and inputs an N-phase multi-phase signal PV1.
To PVN. The AND gate 5 receives the multi-phase signals PV1 to PVN and the control signal CNT, and outputs scanning signals Vg1 to VgN.

FIG. 10 is a timing chart for explaining the operation of the liquid crystal light valve. The start signal FST of the vertical scanning circuit 4 indicates the head of the frame of the video to be displayed, and the clock signal CKV indicates the switching timing of the scanning line. The vertical scanning circuit 7 captures the start signal FST at the rising timing of the clock signal CKV and outputs the multi-phase signals PV1 to PVN. The AND gate 5 receives the multi-phase signals PV1 to PVN and the control signal CNT, and outputs scanning signals Vg1 to VgN of the pixel circuit 1. In the case of the sequential scanning in which the scanning is performed for each line, the scanning signals Vg1 to VgN are changed to the multi-phase signals PV1 to PV1 by setting CNT to “H”.
Pixel circuits 1 equal to PVN and arranged in a matrix are sequentially selected in the vertical direction. Video signals VI1, VI2
Is a signal that changes with reference to the voltage COM of the counter electrode, the polarities of which are opposite to each other and inverted every frame.

Like the vertical scanning circuit 4, the horizontal scanning circuit 3 takes in the start signal STA indicating the head of the scanning line at the rising timing of the clock signal CLK and outputs the multi-phase signals PH1 to PHM. The sample circuit 2 converts the video signals VI1 and VI2 into phase signals PH1 to PHM.
Sampling at the timing of
Output VdM. The luminance signals Vd1 to VdM are input to the pixel circuits 1 arranged in a matrix for each column. At this time, since only the MOS transistors of the pixel circuits 1 in the row selected by the scanning signals Vg1 to VgN are turned on, the luminance signals Vd1 to VdM are written to the storage capacitors 1b of the pixel circuits in the selected row, and the hold signals are held. Is done. Since the voltage held in the storage capacitor 1b is applied to the liquid crystal 1c, the liquid crystal light valve displays an image according to the image signals VI1 and VI2.

FIG. 11 shows an example of the configuration of the horizontal and vertical scanning circuits of the liquid crystal light valve. In the drawing, when a symbol not enclosed in parentheses is used, a horizontal operation circuit is shown, and when a symbol in parentheses is used, a vertical operation circuit is shown. This circuit includes a D-type flip-flop FF, an inverter INV, and a level conversion circuit LS. Flip flop F
F is connected in series to form a shift register. The horizontal scanning circuit has M stages and the vertical scanning circuit has N stages.

The level conversion circuit LS includes two PMOS transistors MP1 and MP2 whose sources are connected to VDD.
And two NMOS transistors MN1 and MN2 whose sources are connected to VSS.
Are connected to the gate of MP1 while being inverted in phase by the inverter INV and connected to the gate of MP2.
The gates of MN1 and MN2 are connected to each other.
It is also connected to the drains of N1 and MP1. Furthermore, MN2
And the drain of MP2 are connected to each other, and this connection point is used as the output PH (PV) of the scanning circuit.

With this configuration, when the output of the FF is "H", MP1 and MN2 are turned off, MP2 is turned on, and the output PH (PV) becomes VDD. On the other hand, the output of the FF is "
L (= GND) ”, MP1 and MN2 are on, MP
2 is turned off, and the output PH (PV) becomes VSS. Thus, the level conversion circuit LS converts the 0-VDD signal to V
The signal is converted to an SS-VDD signal. The level conversion circuit LS is composed of a high-voltage CMOS transistor that operates with a power supply of VDD (+5 V) -VSS (−15 V), and the FF and INV are low-voltage CMOS transistors that operate with a power supply of VDD (+5 V) -0. Make up.

FIG. 1 shows the structure of a liquid crystal light valve according to one embodiment of the present invention. FIG. 1 (a) is a plan view taken along the line AA, and FIG. 1 (b) is a semiconductor viewed from the light irradiation direction. It is a top view of a board.

The liquid crystal light valve of the present embodiment has a semiconductor substrate 100 on which a pixel circuit and a driving circuit are formed, and a counter electrode made of a transparent conductive material such as ITO (Indium-tin-oxide) on the surface of a transparent glass substrate 301. It comprises a counter substrate 300 on which 302 is formed, and a sealing material 510 for filling the liquid crystal 200 between them and bonding the substrate 100 to the substrate 300.

Single-crystal silicon substrate 1 of semiconductor substrate 100
The surface of the first metal layer 140 is provided on the surface of the first metal layer 140 via an insulating layer.
Forming a second metal layer 160 and a third metal layer 180;
Pixel circuit region 101 in which a plurality of switching elements 101a formed by enhancement type NMOS transistors are arranged
And a drive circuit region 102 composed of a circuit element 102a such as an enhancement type NMOS or PMOS, and a wire bonding region 108 are further disposed. In this drive circuit area 102, a sample circuit 2, a horizontal scanning circuit 3, a vertical scanning circuit 4, and an AND circuit 5 are formed.

In the pixel circuit region 101, the pixel electrode 181 formed on the third metal layer 180 and the second metal layer 16 are masked so as to mask the surface of the silicon substrate 110 from light irradiation.
The light-shielding layers 163 formed at 0 are wrapped with each other. Further, a light-shielding layer 191 formed on the third metal layer 180 is arranged on the surface of the silicon substrate 110 in the drive circuit region 102 and other peripheral portions. Light shielding layers 163 and 19
Reference numeral 1 denotes a pattern formed on a metal layer, which reflects or absorbs incident light and blocks light that reaches a semiconductor element included in each circuit or a semiconductor substrate in a peripheral region thereof.

Next, the device structure of the liquid crystal light valve of this embodiment will be described in detail. FIG. 2 is a cross-sectional view showing a part of the pixel circuit area of the liquid crystal light valve. One pixel circuit 1 has a MOS structure composed of an enhancement type NMOS transistor on the surface of a single crystal silicon substrate 110.
It is composed of a transistor 1a, a MOS capacitor 1b, a reflection electrode and the like.

The semiconductor substrate 100 has a MOS surface on one surface.
An n-type silicon substrate 111 for forming a source region and a drain region constituting the transistor 1a and one electrode region of the storage capacitor 1b; a polysilicon layer 120 selectively formed on the substrate 111; 120
A first insulating layer 130 formed thereon and a first insulating layer 1
30 and n penetrating through the insulating layer 130.
A first metal layer 140 contacting the surface of the mold silicon substrate 111 and the polysilicon layer 120;
A second insulating layer formed on the second insulating layer and a second metal layer formed on the second insulating layer and penetrating the insulating layer to contact the first metal layer;
60, a third insulating layer 170 formed on the second metal layer 160, and formed on the third insulating layer 170 and penetrating through the insulating layer 170 to contact the second metal layer 160. It is composed of a third metal layer 180. First
The first metal layer 140, the second metal layer 160, and the third metal layer 180 are formed of, for example, aluminum.

The pixel circuit region 101 includes an n-type substrate layer 111
, P-type well layer 112, n + regions 113 and 116, n-region 114 formed on the surface of p-type well layer 112,
It is composed of a p + region 117 and an element isolation region 118. In a unit pixel circuit indicated by a dashed line, a pair of n
+ Region 113 serves as a source region and a drain region of MOS transistor 1a, respectively. The n region 114 becomes one electrode of the storage capacitor 1b. n + region 116 and n region 11
4. The p + region 117 and the p-type well layer 112 are electrically connected to each other.

The polysilicon layer 120 is selectively formed on the surface of the n-type silicon substrate 111 via the silicon oxide layer 115. Specifically, MOS transistor 1
The gate electrode 123 a is formed on the p-type well layer 112 between the pair of n + regions 113 and the other electrode 124 of the storage capacitor 1 b.
Are formed on the n region 114. The storage capacitor 1b is formed by the n region 114, the polysilicon layer 124, and the silicon oxide layer 115 interposed therebetween.

The first metal layer 140 is divided into a plurality of parts by slits 144, a wiring 141 connecting the MOS transistor 1a and the storage capacitor 1b, a drain wiring 142 of the MOS transistor 1a, and one electrode of the MOS capacitor 1b. A wiring 146 for supplying power to the p-type well layer 112 is formed.

The wiring 141 is provided in one of the pair of n + regions 113 and the polysilicon layer 124 in a contact hole 131 provided in the first insulating layer 130, and the drain wiring 142 is provided in the contact hole 131 provided in the first insulating layer 130. In the other of the pair of n + regions 113, a power supply wiring 146 is formed by a contact hole 131 provided in the first insulating layer 130 through a MOS.
The n + region 116 connected to one electrode of the capacitor and the p + region 117 connected to the p-type well layer 112 are in contact.

The second insulating layer 1 is formed on the first metal layer 140.
A second metal layer 160 on which a light-shielding layer 163 and an intermediate electrode 164 are formed is provided with a third insulating layer 1
A third metal layer (wiring layer) 180 on which a pixel electrode (reflection electrode) 181 is formed is provided via 70. Light shielding layer 1
63 and the intermediate electrode 164 are separated from each other by a slit 162, and the pixel electrodes are separated from each other by a slit 182. Light shielding layer 1
63 is connected to the wiring 146 through the through hole 152 to supply one voltage of the p-type well and the MOS capacitor. The wiring 141 is connected to the intermediate electrode 164 via the through hole 151 and to the pixel electrode 181 via the through hole 171, and outputs the source voltage of the MOS transistor 1 a to the pixel electrode 181.

The liquid crystal light valve thus configured is of a reflection type in which strong light emitted from the glass substrate 300 is reflected by the pixel electrode 181, and the intensity of the reflected light is controlled by the state of the liquid crystal 200. are doing. For example, when a polymer dispersed liquid crystal is used for the liquid crystal 200, the liquid crystal 200 changes from a scattering state to a transparent state by the output voltage of the pixel electrode 181, the reflectance of each pixel is high when the liquid crystal 200 is in the transparent state, and the scattering state is high. It becomes low when As described above, an image is displayed by controlling the change in the state of the liquid crystal by the voltage of the pixel electrode 181.

Next, the shielding of the irradiation light will be described. Reflection electrode 181 formed of uppermost third metal layer 180
The light incident from the inter-electrode slit 182 is blocked by the light shielding layer 163 formed by the second metal layer 160. That is, when viewed from the counter substrate 300 side, the third metal layer 1
80 and the second metal layer 160
The slits 162 formed on the counter substrate 30 are shifted from each other without overlapping each other.
Light incident from the 0 side is reflected by either the third metal layer or the second metal layer and does not reach the semiconductor substrate 110.

As described above, the direct light incident from the counter substrate 300 can be almost completely blocked. Incidentally, in addition to the direct light along the normal line, part of the light incident obliquely on the inter-electrode slit 182 and part of the light scattered at the non-flat portion of the light-shielding layer 163 is a third insulating light. The light is reflected by the layer 170 to become stray light, and the slit 164 of the second metal layer
Through the slit 144 of the metal layer of the semiconductor substrate 11
It may reach zero. The non-planar location of the light-shielding layer 163 is determined by the plane pattern of the MOS transistor 1a, the MOS capacitor 1b, the first metal layer 140, and the like.

In this embodiment, the positions of the inter-pixel slits 182 of the third metal layer 180 are arranged corresponding to the flat places of the light shielding layer 163 formed of the second metal layer 160. Further, at least one surface, such as each surface of the first metal layer 140 and the second metal layer 160 and the lower surface of the third metal layer 180, is made of a material such as tungsten silicon (WSi) or molybdenum silicon (MoSi). And a multi-layer structure of aluminum and aluminum. Thus, stray light reaching the semiconductor substrate 110 can be significantly reduced.

FIG. 3 is a sectional view of the liquid crystal light valve of this embodiment, including a pixel circuit and a peripheral portion. Pixel circuit area 10
1 forms a p-type well layer 112 on an n-type silicon substrate 111 and is provided therein. Pixel circuit area 101
Is provided with a light shielding layer 165 formed of the second metal layer 160 in the peripheral region of the third metal layer 18 which is the uppermost layer.
With 0, an electrode 183 electrically separated from the electrode 181 is formed, and the same voltage as that of the counter electrode 302 is supplied to the electrode 183. Thereby, the applied voltage of the liquid crystal facing the peripheral area of the pixel circuit is set to zero.

FIG. 4 is a cross-sectional view of the driving circuit of this embodiment and its peripheral portion. PM on the surface of the n-type silicon substrate 111
OS transistors and NMOS transistors are formed in the p-type well layer 112, respectively, and these transistors constitute driving circuits such as the horizontal scanning circuit 3 and the vertical scanning circuit 4. A light-shielding layer 1 for blocking incident light from the counter substrate 300 side is provided above the driving circuit and its peripheral region.
66 are provided by the second metal layer 160. In addition,
The light-blocking layer may be provided by another metal layer 140 or 180.

As described above, in the liquid crystal light valve of this embodiment, the light irradiated to the pixel circuit area is
At 63, the light radiated to the peripheral portion of the pixel circuit region is blocked by the light blocking layer 165, and the light radiated to the drive circuit region and its peripheral portion is blocked by the light blocking layer 166. According to this,
Even if strong light is irradiated like a projection display,
Light incident on the silicon substrate is reliably blocked, latch-up can be prevented, and deterioration and destruction of the characteristics of the device can be avoided. Further, since an electrode is provided above the pixel circuit peripheral portion so that the applied voltage of the liquid crystal facing the peripheral portion of the pixel circuit region becomes 0, the brightness of this portion is reduced to improve the image quality of the screen peripheral portion. Can be improved.

Next, a liquid crystal light valve according to a second embodiment of the present invention will be described. FIG. 5 is a plan view of the liquid crystal light valve, and FIG. 6 is a sectional view taken along line BB. This embodiment is different from the above-described embodiment in that a carrier stopper layer is provided.

The carrier stopper layer is formed in the pixel circuit region 10
1 and the drive circuit region 102. Specifically, n + region 191 provided on the surface of n-type silicon substrate 110 and p + region 19 provided on p-type well layer 112 are provided.
2, and the maximum voltage (VDD) is applied to the n + region 191.
A minimum voltage (VSS) is supplied to the p + region 192.

According to this, the carriers generated by the light radiated to the periphery of the semiconductor substrate 100 are attracted to the carrier stopper region, and from the n + region 191 to the p + region 19
The photocurrent Ip flows in the direction 2. As a result, the photocurrent does not flow through the elements of the drive circuit, and latch-up can be prevented.

A liquid crystal light valve which is a modification of the second embodiment will be described with reference to a plan view of FIG. 7 and a sectional view of FIG. In this example, the carrier stopper layer is realized in the p-type well layer. Specifically, ap + region and an n region are provided in a p-type well layer 193 provided on the surface of the n-type silicon substrate 110, an n + region is further provided in the n region, and the p + region and the n + region are connected by a wiring 148. Connected.

According to this, carriers generated by the light radiated to the periphery of the semiconductor substrate 100 are transferred to the p-type well layer 19.
The carrier current is converted into the photocurrent Ip in the carrier stopper region of No. 3.
As a result, the photocurrent does not flow to the elements of the drive circuit,
Latch-up can be prevented.

Next, the mounting structure of the liquid crystal light valve described in each of the above embodiments will be described with reference to the plan view of FIG.
This will be described with reference to the sectional view of FIG.

The semiconductor substrate 100 on which the pixel circuit 1, the horizontal scanning circuit 3, the vertical scanning circuit 4, and the like are formed is adhered to the ceramic substrate 500 with a conductive paste with the circuit portion facing upward. Liquid crystal 200 is filled between the semiconductor substrate 100 and the opposing substrate 300 provided opposite thereto. The liquid crystal 200 is sealed by a seal member 510 provided on the periphery thereof, and is protected from external humidity and the like. The opposing electrode 302 provided on the surface of the opposing substrate 300 is connected to a wiring pattern such as an electrode 181 formed on the uppermost metal layer 180 of the semiconductor substrate 100 by using a conductive paste 530.

The signal terminal 550 of the counter substrate 300 is connected to a wiring pattern formed on the ceramic substrate by wire bonding 520. Wire bonding position on semiconductor substrate 100 and counter electrode 302 on surface of counter substrate 300
Is connected to only one side of the upper side of the substrate 100, thereby reducing the area of the signal terminal portion of the semiconductor substrate 100.

FIG. 14 is a schematic diagram showing the configuration of a projection display to which the above-mentioned liquid crystal light valve is applied. The projection display includes a light source 700, a first lens 710,
It comprises a mirror 720, a second lens 730, a liquid crystal light valve 740, a projection lens 750 and a screen 760.

The light from the light source 700 is transmitted to the first lens 71
0, the light is condensed at the position of the mirror 720 and the first lens 73
At 0, the light is collimated and illuminates the liquid crystal light valve 740. The liquid crystal light valve 740 controls the reflection state of the irradiated light by a voltage applied to each liquid crystal pixel, and transmits the reflected light from the liquid crystal light valve to the second lens 730 and the projection lens 7.
The image is magnified and projected on the screen 760 via 50 to form an image.

The light beam from the light source is decomposed into three light beams of three primary colors, a liquid crystal light valve is provided for each light beam, and the reflected light from the three liquid crystal light valves is again synthesized and enlarged and projected. A projection display of color display can be obtained. Decomposition of light into three primary colors can be simultaneously performed using, for example, a dichroic mirror to combine reflected lights from three liquid crystal light valves.

In a projection type display, the light applied to the liquid crystal light valve reaches several million lux, and the quality of the image is deteriorated due to the deterioration or destruction of the element due to latch-up. However, according to the present embodiment, the liquid crystal light valve is provided with light irradiation on the silicon substrate forming the image circuit region, the operation circuit region and the peripheral region with respect to stray light caused by oblique incidence and scattering of the metal wiring layer. Light-shielding means that can shut off the light can be reliably prevented from latching up,
Light resistance was improved up to 1 million lux. This has enabled the practical use of a projection display using a liquid crystal light valve.

The liquid crystal light valve using the single crystal silicon substrate and the projection type display using the same have been described above. Needless to say, the liquid crystal light valve of the present invention can be realized by using a substrate having a semiconductor layer formed on an insulating substrate, a compound semiconductor substrate, or the like instead of the silicon substrate.

[0062]

According to the liquid crystal light valve of the present invention, since the pixel circuit area, the drive circuit area, and the light shielding means for blocking light irradiation to the peripheral area are provided, the photocurrent of the semiconductor substrate can be reduced. As a result, the occurrence of latch-up can be prevented, and there is an effect that the deterioration of the image quality due to the deterioration or destruction of the element is avoided and the definition of the image is improved.

Further, since a plurality of metal layers forming each circuit are used and light shielding means is provided in the lower metal layer so as to mask a space which cannot be reflected by the wiring pattern of the upper reflective electrode, reliable light shielding can be achieved in a compact manner. There is an effect that can be realized.

Furthermore, since the carrier blocking region for absorbing carriers generated by light irradiation is provided in the peripheral region together with the light shielding layer for each circuit region, the photocurrent of the semiconductor substrate can be greatly increased even when the irradiation light is strong. And it is possible to reliably prevent the occurrence of latch-up.

According to the projection type display of the present invention, it is possible to apply a liquid crystal light valve that can withstand light irradiation of about 500 million lux, and it is possible to provide an enlarged screen with high brightness and high definition.

[Brief description of the drawings]

FIG. 1 is a plan and sectional structural view of a liquid crystal light valve according to a first embodiment of the present invention.

FIG. 2 is a sectional structural view of a pixel circuit region of the liquid crystal light valve according to the first embodiment.

FIG. 3 is a sectional structural view of a pixel circuit and a peripheral region of the liquid crystal light valve according to the first embodiment.

FIG. 4 is a sectional structural view of a drive circuit region and a peripheral region of the semiconductor substrate according to the first embodiment.

FIG. 5 is a plan view of a driving circuit region and a peripheral region of a semiconductor substrate of a liquid crystal light valve according to a second embodiment of the present invention.

FIG. 6 is a sectional structural view of a drive circuit region and a peripheral region of a semiconductor substrate according to a second embodiment.

FIG. 7 is a plan view of a driving circuit region and a peripheral region of a semiconductor substrate according to a modification of the second embodiment.

FIG. 8 is a sectional structural view of a drive circuit region and a peripheral region of a semiconductor substrate according to a modification of the second embodiment.

FIG. 9 is a circuit diagram of a liquid crystal light valve.

FIG. 10 is a time chart showing a liquid crystal light valve operation.

FIG. 11 is a scanning circuit diagram of a liquid crystal light valve.

FIG. 12 is a plan view showing a mounting structure of the liquid crystal light valve of the embodiment.

FIG. 13 is a side sectional view showing a mounting structure of the liquid crystal light valve of the present embodiment.

FIG. 14 is a schematic diagram illustrating a configuration of a projection display to which the liquid crystal light valve of the present invention is applied.

FIG. 15 is a schematic diagram illustrating a latch-up phenomenon of a parasitic bipolar transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Pixel circuit, 1a ... MOS transistor, 1b ... Capacitance, 1c ... Liquid crystal capacity, 2 ... Sample circuit, 3 ... Horizontal scanning circuit, 4 ... Vertical scanning circuit, 5 ... AND gate, 10
0: semiconductor substrate, 101, 101a: pixel circuit area, 1
02, 102a: drive circuit region, 110: n-type silicon substrate, 112: p-type well layer, 120: polysilicon layer, 130: first insulating layer, 131: through hole, 1
40 ... first metal layer, 141, 142, 146 ... wiring,
150: second insulating layer, 151: through hole, 160
... Second metal layer, 163, 165, 166.
70: third insulating layer, 171: through hole, 180 ...
Third metal layer, 181... Pixel electrode (reflection electrode), 182
... Slit, 183 ... Another electrode, 191,192,19
3. Carrier stopper, 200 liquid crystal, 300 counter substrate, 302 counter electrode.

────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kazuya Takemoto 3300 Hayano Mobara-shi, Chiba Pref.Electronic Devices Division, Hitachi Hitachi, Ltd. (72) Katsumi Matsumoto 3681 Hayano Mobara-shi Chiba Hitachi Device Engineering (56) References JP-A-6-194690 (JP, A) JP-A-5-107550 (JP, A) JP-A-58-85478 (JP, A) JP-A-58-54679 (JP, A) U) (58) Field surveyed (Int.Cl. ⁷ , DB name) G02F 1/1368

Claims (10)

(57) [Claims] A semiconductor substrate having, on one surface, a pixel circuit region including a plurality of switching elements arranged in a matrix, a driving circuit region including elements for driving the switching elements, and a peripheral region thereof; On the one surface of the semiconductor substrate, there are provided a plurality of metal layers which are hierarchically arranged and have wiring means via an insulating layer.
The plurality of metal layers are divided by slits, and
A plurality of metal layers serving as output terminals of the switching element.
It is formed as a reflective electrode, a metal layer underlying the uppermost metal layer of gold of the uppermost
First light shielding means formed so as to overlap with respect to the plane space of the slit of the genus layer, and constitute a second light shielding means will covering the surface space of the drive circuit region and the peripheral region, the light irradiation A transparent counter substrate having a counter electrode facing the reflective electrode on a surface on the opposite side, and a liquid crystal light valve formed by filling a gap between the semiconductor substrate and the counter substrate with liquid crystal. 2. The liquid crystal light valve according to claim 1, wherein the first light blocking means is arranged in a flat place where the first light blocking means does not compete with the wiring means and the like. 3. The liquid crystal light valve according to claim 2, wherein the flat place where the first light shielding means is arranged is secured by a plurality of metal layers. 4. The method of claim 1, 2 or 3, wherein the metal layer is on the top and / or bottom of at least one layer, the liquid crystal light valve formed by providing a metal silicide layer of WSi ₂ or MoSi _2. 5. A semiconductor substrate having, on one surface, a pixel circuit region composed of a plurality of switching elements arranged in a matrix and a drive circuit region composed of elements for driving the switching elements; and the pixel of the semiconductor substrate. A carrier absorbing means formed in a peripheral region of the circuit region and the drive circuit region to absorb carriers generated by light irradiation; and a wiring which is hierarchically formed on the one surface of the semiconductor substrate with an insulating layer interposed therebetween. A plurality of metal layers having means, wherein the plurality of metal layers are divided by slits, and
At least one of the metal layers of the
Is formed as a plurality of reflective electrode serving as the output end of the element, the metal layer underlying the uppermost metal layer of gold of the uppermost
First light shielding means formed so as to overlap with respect to a plane space of the slit of the genus layer, and constitute a second light shielding means will covering the surface space of the drive circuit region and the peripheral region is irradiated with light A liquid crystal light valve comprising: a transparent counter substrate having a counter electrode facing the reflective electrode on the opposite surface; and a liquid crystal filled in a gap between the semiconductor substrate and the counter substrate. 6. The liquid crystal light valve according to claim 5, wherein a well layer or a diffusion layer to which power is supplied is used as the carrier absorbing means. 7. The liquid crystal light valve according to claim 1, wherein the switching element is formed in a well, and the well is supplied with a metal layer having the light shielding unit. 8. A semiconductor substrate having, on one surface, a pixel circuit region including a plurality of switching elements arranged in a matrix, a driving circuit region including elements for driving the switching elements, and a peripheral region thereof. On the one surface of the semiconductor substrate, a plurality of metal layers that are hierarchically arranged and have wiring means with an insulating layer interposed therebetween, and the topmost metal layer of the plurality of metal layers is divided by a slit, The top metal layer is the switching element
Formed as a plurality of reflective electrodes that serve as the output terminals of the
Ri, at least one metal layer of the lower layer of the and another electrode formed on the area corresponding to the peripheral region of the pixel circuit area at the top, the top of the metal layer
, Said first light shielding means you overlap the plane space of the slits of the uppermost metal layer, and a second light shielding means will covering the surface space of the drive circuit region and the peripheral region, the light irradiation A transparent counter substrate having a counter electrode facing the reflective electrode on the opposite side, a liquid crystal filling a gap between the semiconductor substrate and the counter substrate, and setting the counter electrode and the another electrode to the same voltage. Means to keep,
Liquid crystal light valve provided with. 9. A light source, a liquid crystal light valve for controlling a reflection state of irradiated light by a voltage applied to a liquid crystal pixel, a screen for displaying an image, and the liquid crystal light for converting light from the light source into parallel light. A projection display device comprising: an optical unit that irradiates a bulb and reflects and projects reflected light from the liquid crystal light valve onto the screen in an enlarged manner. The liquid crystal light valve according to any one of claims 1 to 8, A projection type liquid crystal display device using the liquid crystal light valve according to any one of the preceding claims. 10. The projection type liquid crystal display device according to claim 9, wherein the brightness of the light source applied to the liquid crystal light valve reaches about 5 million lux.