JP3037177B2 - Delay circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit, and more particularly to a delay circuit used for adjusting the timing of a logic circuit such as a gate array composed of MOS transistors.

[0002]

2. Description of the Related Art Generally, a plurality of CMs are used as delay circuits for adjusting the timing of a logic circuit such as a gate array.
There is a method of cascading OS inverter circuits. In a delay circuit using this type of CMOS inverter, it is necessary to increase the number of inverters having a large propagation delay time (hereinafter, delay time). Therefore, there is a problem that the number of gates, that is, the number of elements used in the delay circuit increases, and the circuit area increases.

Referring to FIG. 10, which shows a block diagram of a conventional first delay circuit of this type, this conventional first delay circuit comprises an Nch transistor N2 having a source grounded.
01 and a Pch transistor P2 having a source connected to a power supply
01 are connected in common to each other as an input terminal and are connected to an input terminal TI, and each drain is connected in common to form an output terminal as a CMOS inverter 201. An Nch transistor N202 and a Pch transistor P202, Inverters 202, 203, and 204, which are composed of an Nch transistor N203 and a Pch transistor P203, and an Nch transistor N204 and a Pch transistor P204, are connected in cascade, and a common connection drain of the final-stage inverter 204 has an output terminal TO.
Was connected to.

As described above, a plurality of CMs, in this example, four CMs
The required delay time is generated by cascading OS inverters.

In the conventional first delay circuit, in the case of a gate array type semiconductor integrated circuit device (hereinafter referred to as a gate array), usually, transistors of the same size are arranged in advance in layout, so that one transistor Ability is decided. Further, since the transistor is designed to have a low conduction resistance so that high-speed operation can be performed, the transistor characteristics are not suitable for increasing the delay time. Therefore, a large number of inverter stages are required to obtain a desired large delay time, and the layout area is large.

[0006] As an example, N,
Consider a case where a delay time of 20 ns is generated using a Pch transistor.

If the gate width of the transistor is 13 μm and the gate length is 0.6 μm, the area occupied by one transistor is about 1 including the wiring area associated with the transistor.
It becomes 8 μm × 7 μm. Therefore, the area per transistor is 1.26 × 10 −4 mm 2. When estimating the delay value based on the typical transistor characteristics described above,
The delay time per inverter stage using one Nch and one Pch transistor is about 0.083 ns, which is very high. Therefore, 2
In the case of making a delay time of 0 ns, 20 ＝ 0.083 = 24
Zero-stage cascade connection is required. Therefore, the total layout area of this circuit is 1.26 × 10−4 × 2 × 240 =
6.048 × 10- ² mm ² and becomes very large layout area.

A conventional second delay which reduces the circuit area, which is a drawback of the first delay circuit, by increasing the delay time per inverter by reducing the drive capability of the inverter by connecting transistors in series. Referring to FIG. 11 which shows a circuit as a block, this second conventional delay circuit includes an inverter 101 including a series connection of Pch transistors P101 to P104 and a series connection of Nch transistors N101 to N104, and a Pch transistor P1.
21 to P124 in series and Nch transistor N12
1 to N124 in series. Transistor P101 of inverter 101
To P104 and N101 to N104 are commonly connected, the common connection point is connected to the input terminal TI, and the drains of the transistors P104 and N104 are commonly connected to the node TN1 which is the output terminal of the inverter 101.
Connect to 00.

Similarly, the gates of the transistors P201 to P204 and N201 to N204 of the second-stage inverter 102 are commonly connected to each other, and this common connection point is connected to a node TN100 which is an input terminal.
The drains of N204 are commonly connected and connected to an output terminal TO which is an output terminal of the inverter 201.

The sources of the transistors P101 and P121 are connected to the power supply VDD by the transistors N101 and N121.
Are connected to ground, respectively.

The drive capability of each of the inverters 101 and 102 is reduced by the series connection of the transistors as described above, and the number of cascade connection stages is reduced by increasing the delay time per one stage of the unit delay circuit. As a result, the circuit area is reduced. Was shrinking.

In this conventional second delay circuit, the delay time per stage is increased, so that the circuit occupied area is reduced and improved. However, since the number of elements per unit circuit is also increased, the improvement is achieved. The degree was insufficient.

For example, when a transistor having the same characteristics as the conventional first delay circuit is used to generate a delay time of 20 ns in the same manner as described above, the delay value per unit delay circuit is as follows:
2.86 ns. Therefore, with a delay time of about 20 ns, it was necessary to connect 20 ÷ 2.86 = 7 stages in series. Similarly, estimate the layout area of the transistor,
When approximately ^{18μm × 7μm = 1.26 × 10- 4} mm 2, because it requires the unit delay circuit 16 transistors per stage, the layout total area 1.26 × 10-4
× has required ^{16 × 7 = 1.41 × 10- 2} mm 2.

Further, the third conventional delay circuit described in Japanese Patent Application Laid-Open No. 5-206803 is provided with a delay section which mainly performs a delay operation, and a waveform shaping section for shaping an output waveform. By limiting the amplitude, the potential difference between the gate and the source of each transistor in the waveform shaping unit is reduced, and the driving capability of each transistor is reduced, thereby lowering the driving capability of the waveform shaping unit with respect to the load and obtaining a large delay value. I tried.

Referring to FIG. 12, which shows a block diagram of a third conventional delay circuit, the third conventional delay circuit comprises an inverter circuit and delays an input signal VI supplied from an input terminal TI to a node. An output signal V having a predetermined waveform in response to the supply of the drive signal Vn0 from the delay unit 1 which includes a delay unit 1 for outputting the drive signal Vn0 to TN0 and an inverter circuit.
And a waveform shaping unit 2 for shaping the signal into O and outputting it to the output terminal TO.

The delay unit 1 has a Pch transistor P having a source connected to the power supply VDD and a gate connected to the input terminal TI.
11, an Nch transistor N31 having a gate and a drain commonly connected and a drain connected to the drain of the transistor P11; an Nch transistor N11 having a source connected to the ground G and a gate commonly connected to the gate of the transistor P11; A Pch transistor P31 commonly connected and having a drain connected to the drain of the transistor N11.

The substrate electrodes (hereinafter referred to as back gates) of the transistors P11 and P31 are connected to the power supply VDD, and the back gates of the transistors N11 and N31 are connected to the ground G.

The waveform shaping section 2 has a source connected to a power supply VDD, a gate connected to a node TN0 which is an output terminal of the delay section 1, and a drain connected to an output terminal TO.
And a source connected to the ground G and a gate connected to the transistor P2.
And an N-channel transistor N21 having a drain connected to the drain of the transistor P21.

The back gate of the transistor P21 is connected to the power supply VDD, and the back gate of the transistor N21 is connected to the ground G.

Next, the operation of the third conventional delay circuit will be described with reference to FIG. 12 and FIG. 13 which shows the operation state of each part in a waveform diagram. The input signal VI supplied to the input terminal TI is high. When the level is at the level, the transistor N11 is turned on and the drain of the transistor N11 is at the L level. At this time, the gate of the transistor P31 also becomes L level. Here, assuming that the threshold voltage of the Pch transistor P31 is VTP1, the signal of the source of the Pch transistor P31, that is, the signal of the node TN0 which is the output terminal of the delay unit 1, that is, the drive signal Vn0 is lower than the L level as shown in the graph A. The voltage becomes higher by the threshold voltage VTP for one minute. When the transistor P21 conducts, a delayed H-level output signal VO is output to the output terminal TO.

When the input signal VI is at the L level, the transistor P11 is turned off and the drain is at the H level. At this time, the gate of the transistor N31 also becomes H level. Here, assuming that the threshold voltage of the transistor N31 is VTN1, the drive signal Vn0 of the source of the transistor N31, that is, the node TN0 is lower than the power supply potential VDD by the threshold voltage VTN1 as shown in the graph B. At this time, the transistor N25 becomes conductive and outputs the delayed L-level output signal VO to the output terminal TO.

Therefore, the amplitude of the output signal of delay section 1, that is, drive signal Vn0 is changed from ground potential VG + | VTP1 | to power supply potential VD-VTN1. However, the output signal Vn
, Always exceeds the threshold voltage of each transistor of the next-stage waveform shaping section 2, a steady current flows in the waveform shaping section 2.

Referring to FIGS. 14A and 14B which are characteristic diagrams showing the relationship between the potential difference (hereinafter referred to as VBS) between the back gate and the source of each of the Nch and Pch transistors and the threshold voltages VTN and VTP, respectively. As the threshold voltage increases, the threshold voltages VTN and VTP of the transistors increase. This phenomenon is called "back gate effect". Generally, the variance (variation) of the characteristics due to the process of the semiconductor integrated circuit device and other manufacturing steps, that is, the variance of the delay time of a predetermined circuit of the semiconductor circuit device is used as one of the measures of the manufacturing variance. Each shows the characteristic of the threshold value when there is no manufacturing dispersion, that is, the standard characteristic.
TSN and VTSP are threshold characteristics when the delay time is maximized due to manufacturing dispersion, that is, upper limit characteristics.
The VTFP indicates a threshold characteristic when the delay time is minimized due to manufacturing dispersion, that is, a lower limit characteristic.

Also, as a feature of the back gate effect, V
The influence of manufacturing dispersion on the threshold value increases as the BS increases. Here, dFN0, dFP0 and dSP
0 and dSP0 are VTTN and VTTP at the time of the standard characteristic at 0 V of VBS and VTTN and VTFP at the time of the lower limit characteristic.
And the threshold voltage difference between VTTN, VTTP and VTSN, VTSP at the time of the upper limit characteristic, respectively. Further, each of dFN, dFP and dSN, dSP is the difference between the threshold voltage between VTTN, VTTP at an arbitrary voltage of VBS and VTTN, VTFP at the lower limit characteristic, and VTSN, VTS at VTTN, VTTP at the upper limit characteristic.
The difference between P and the threshold voltage is shown.

As can be seen from the drawing, the threshold voltage differences dFN0, dFP0 and dSP0, dSP0 at the time of VBS of 0 V are larger than the threshold voltage differences dFN, dFP, dSN, at the arbitrary voltage.
It turns out that it is smaller than dSP. From this, it can be said that the back gate effect is such that the larger the VBS, the larger the dispersion of the threshold voltage due to the manufacturing dispersion.

The amplitude of the output signal VO of the delay unit 1 of the third conventional delay circuit is V when the input signal VI is at the H level.
G + | VTP1 |, as described above, the power supply VDD
Is 5V and the potential VG of the ground G is 0V,
This value is about 1.7 V for the following reason.

Assuming that the initial potential of the output signal VO is 5 V when the input voltage is at the H level, the transistor P
The VBS of 31 is 0V. Accordingly, the threshold voltage VTP1 of the transistor P31 is about 0.8 V as shown in the figure, and the drain of the transistor P31 is almost 0 V because the transistor N11 is conducting. Therefore,
Transistor P31 is turned on, and output signal VO is output.
Potential starts to drop. Accordingly, the transistor P3
1 rises, which causes transistor P31
Also increases the threshold voltage VTP1. At this time, since the power supply voltage is 5V, the possible values of VBS and the threshold voltage VTP1 are in a range where the relationship of VBS + VTP1 ≦ 5V holds. Here, according to the graph of the standard characteristic VTTP of the Pch transistor shown in the figure, VBS + VTP = 5V
Looking at the points where VBS = 3.3 V, VTP = 1.7
V. Therefore, the node TN0 which is the output terminal of the delay unit 1
Is equal to VG + | VTP1 | = 0V + 1.
7V = 1.7V.

Also, it has been described that when the input voltage is at the L level, the power supply potential is VD-VTN1, but for the same reason as the above-described relationship between VBS and the threshold voltage, the value in this example is about It becomes 3.3V.

Referring again to FIG. 14, the threshold voltages VTP and VTN when the VBS of each of the Pch transistor and the Nch transistor is 0 V are approximately 0.8 V from the figure.
It is. Therefore, the output signal Vn of the delay unit 1 is normally 0 V + 0.8 V = 0.8 V or less when it is at the L level.
Unless 5V-0.8V = 4.2V or more is output at the H level, a steady current flows. However, this circuit uses transistors P31 and N
Since the threshold voltage of the Nch and Pch transistors constituting the circuit is increased by VBS / 31
When the threshold characteristics follow the standard characteristics VTTN and VTTP, only an amplitude of 1.7 V to 3.3 V can be obtained. Therefore, the transistors N21 and P21 of the waveform shaping unit 2 are always in a conductive state, and a steady current flows. In this example, the steady-state current value at this time is 0.6 mA both when the output signal VO is at the H level and the L level.

Similarly, since the potential of the output signal Vn of the delay unit 1 cannot exceed the threshold voltage of the waveform shaping unit 2,
Both transistors of the waveform shaping unit 2 are always in a conductive state, and the potential of the output signal VO does not fully swing at L level of 0.3 V and H level of 4.7 V.

In the third conventional delay circuit, as described later, the delay time when the output signal VO transitions from the L level to the H level in a standard state without manufacturing dispersion is 1.58 ns, The delay time when transitioning from level to L level is 1.51 ns.

When the same third delay circuit generates the same delay time, the occupied area of the third conventional delay circuit can be smaller than that of the first and second conventional delay circuits.

The same characteristic as the conventional first and second delay circuits, that is, VBS / threshold voltage characteristic is VTT of FIG.
20 n in the same manner as described above using N, VTTP transistors.
When the delay time of s is generated, the delay time per unit delay circuit is 1.45 ns. Therefore, 20
In the case of ns, it is necessary to cascade connect the unit circuits of 20 ＝ 1.45 = 14 stages. The area occupied by the transistor is similarly estimated to be about 18 μm × 7 μm = 1.26 × 10 −4 mm ²
Then, since seven transistors are required per unit circuit, the total layout area is 1.26 × 10−
⁴ × 7 × 14 = 1.23 × 10−2 mm ² .

Further, the fluctuation of the delay time caused by the manufacturing dispersion will be described in detail. As described above, the output voltage Vn of the delay unit 1 is equal to the ground potential VG + | VTP1 |
D-VTN1, but these threshold voltages VTP1,
VTN1 includes a back gate effect. If the threshold voltage fluctuation of the transistor due to the back gate effect is included, the output voltage Vn of the delay unit 1 becomes dSN, dFN and dSP,
VG + VTP1 is equal to V
G + VTP1 + dSP or VG + VTP1-dFP, and VD-VTN1 is VD-VTN1-dSN or VD
−VTN1 + dFN. Therefore, when manufacturing dispersion occurs, the threshold voltage of the transistor fluctuates. On the other hand, in the transistors N31 and P31, the threshold voltage fluctuation due to the back gate effect due to the increase in VBS is added.

Next, using the gate-source voltage (VGS) of the transistor and the drain current (IDS) when the drain and source are 5 V, the input voltage Vn of the waveform shaping section 2 is obtained.
Referring to FIG. 15 showing the output current ID characteristic, delay unit 1
And the operation of the waveform shaping unit 2 when manufacturing dispersion occurs, IDTN and IDTP are Nch and Pc, respectively.
h When there is no transistor dispersion, ie, standard VG
S-IDS characteristics are shown, IDSN and IDSP show VGS-IDS characteristics when the delay time is maximum due to manufacturing dispersion, respectively, and IDFN and IDFP show cases where the delay time is minimum due to manufacturing dispersion, ie VGS at the lower limit. -IDS characteristics are respectively shown. VnTT indicates a standard state, and VnSF indicates an input voltage Vn in a state where the delay time of an Nch transistor is maximum and the delay time of a Pch transistor is minimum (hereinafter SF state) due to manufacturing dispersion. In this figure, dotted lines in contact with the left and right ends of VnTT and VnSF indicate the voltage of the output signal VO of the waveform shaping unit 2 when the voltage Vn is at the L level and the H level, respectively.

As an example, comparing the standard state with the SF state, the input of the waveform shaping unit 2 is VnTT in the standard state.
, The driving transistor is dominant in both D2 and D4, and the IDS ratio of each transistor becomes L level when the VGS of the Nch transistor is large and H level when the VGS of the Pch transistor is large. Output each. Here, SF is considered in consideration of manufacturing dispersion.
State, when the voltage Vn is VnSF, the VGS of the Nch transistor is compared with the standard state as indicated by D3.
And the IDS of the Pch transistor increases. Therefore, there is almost no difference between the output IDS of each of the Nch and Pch transistors. This means that the current that can be used for driving the next stage is small. That is, the driving capability is extremely reduced as compared with the standard state without manufacturing dispersion.

As an example, Nc constituting this delay circuit
h, the gate width and gate length of each Pch transistor are 1
When the VBS / threshold voltage characteristic of each transistor is VTTN, VTTP, that is, the transistor has the same size as that in the standard state, the Vch / threshold voltage characteristic of the Nch transistor is VTSN. When the VBS / threshold voltage characteristic of the Pch transistor complies with VTFP, that is, in the case of the FS state, the delay values are estimated as follows.

First, in the case of the standard state, as described above,
The delay time when the output voltage VO transitions from the L level to the H level is 1.58 ns, and the delay time when the output voltage VO transitions from the H level to the L level is 1.51 ns.

Next, in the case of the FS state, the output voltage VO becomes L
The delay time from the level to the H level is 4.57 n
s, the delay time when the output voltage VO transitions from the H level to the L level is 7.06 ns.

Therefore, in the third conventional delay circuit, the dispersion of the delay time due to the dispersion of the manufacturing is caused by the output voltage VO.
Is 2.9 times when transitioning from the L level to the H level, and 4.7 times when transitioning from the H level to the L level, which indicates that the dispersion of delay values due to manufacturing dispersion is large.

[0041]

In the above-mentioned conventional first delay circuit, transistors of the same size and therefore of the same capacity are arranged in advance in layout, and the conduction resistance of these transistors is designed to be low so as to correspond to high-speed operation. As a result, it is unsuitable for obtaining a large delay time, so that a large number of cascade stages is required to generate a desired delay time, and the occupied area becomes large.

In the conventional second delay circuit, since the delay time per stage increases, the area occupied by the circuit is reduced and improved. However, since the number of elements per unit circuit also increases, There is a disadvantage that the degree of improvement is insufficient.

When the same third delay circuit generates the same delay time, the occupied area of the third delay circuit can be smaller than that of the first and second delay circuits. Outputting an intermediate level amplitude lower by the threshold voltage of the transistor than the L level by the threshold voltage of the Pch transistor, and each transistor of the waveform shaping unit at the next stage is not completely shut off by the back gate effect. Since a leak current is generated, there is a disadvantage that a steady current is large.

Further, the third conventional delay circuit is susceptible to a change in the threshold voltage of the transistor due to the back gate effect, and furthermore, the change in the threshold voltage causes a drastic reduction in the driving capability for the next stage. There is a drawback that the dispersion of the delay time due to the manufacturing dispersion is large due to the configuration.

An object of the present invention is to solve the above-mentioned disadvantages, to provide a delay circuit which has a small circuit occupation area, suppresses dispersion of propagation delay time, and has a small steady-state current.

[0046]

A delay circuit according to the present invention receives a supply of an input signal, delays the input signal and outputs a drive signal, and the input signal in response to the supply of the drive signal. In a delay circuit comprising a waveform shaping section for further delaying by a predetermined time and outputting an output signal shaped to a predetermined amplitude, the delay section has a gate connected to an input terminal, a source and a substrate electrode.
First poles of a first conductivity type with respective poles connected to a first power supply
A second transistor of a second conductivity type having a gate connected to the gate of the first transistor and a source and a substrate electrode connected to a second power source, respectively, and a first transistor connected in common with the gate and drain. And the substrate electrode is connected to the drain of the first transistor.
A third transistor of the first conductivity type connected to the first power supply, and a gate and a drain commonly connected to each other to form a second transistor.
And a fourth transistor of a second conductivity type having a source connected to the drain of the second transistor and a substrate electrode connected to the second power supply, respectively . 1 is connected to the third current terminal.
A fifth transistor having a drain connected to the other of the second current terminal connected to the drain of the fourth transistor, and a gate and a drain commonly connected to each other; A first conductivity type sixth transistor having a source connected to the first power supply, a drain connected to the output terminal, and a substrate electrode connected to the first power supply, respectively , receiving the supply of the first drive signal. A second conductive layer having a gate receiving the second drive signal, a source connected to the second power supply, a drain connected to a drain of the sixth transistor, and a substrate electrode connected to the second power supply. And a seventh transistor of the type.

[0047]

FIG. 1 shows an embodiment of the present invention.
2, the same components as those of FIG. 2 are denoted by common reference characters / numerals, and FIG. 1 is also shown by a block. The delay circuit of the present embodiment shown in FIG. Basically, instead of the delay unit 1, a Pch transistor P11,
A delay unit 1A including P12 and Nch transistors N11, N12, and N13, and a Pch transistor P21 and an Nch transistor n21 having respective gates connected to nodes TN1 and TN2 of the delay unit 1A instead of the waveform shaping unit 2, respectively. And a waveform shaping unit 2A.

The delay unit 1A includes a Pch transistor P11 having a source connected to the power supply VDD, a Pch transistor P12 having a gate and a drain connected in common and a source connected to the drain of the transistor P11, and an Nch transistor having a source connected to the ground G. N11, an Nch transistor N12 having a gate and a drain connected in common and a source connected to the drain of the transistor N11, and an Nch transistor N13 having a gate and drain connected in common and having the source connected to the drain of the transistor P12 and the source connected to the drain of the transistor N12, respectively. And a transistor P
11 and N11 are commonly connected to an input terminal TI.

The substrate electrodes (hereinafter referred to as back gates) of the transistors P11 and P12 are connected to the power supply VDD, and the back gates of the transistors N11, N12 and N13 are connected to the ground G.

The waveform shaping section 2 has a source connected to the power supply VDD, a gate connected to a node TN1, which is a common connection point between the drains of the transistors P12 and N13 of the delay section 1, and a drain connected to the output terminal TO.
Nch transistor N21 having a source connected to ground G, a gate connected to a node TN2 which is a common connection point between the drain of the transistor N12 and the source of the transistor N13 of the delay unit 1, and a drain connected to a drain of the transistor P21. And

The back gate of the transistor P21 is connected to the power supply VDD, and the back gate of the transistor N21 is connected to the ground G.

Next, the operation of the present embodiment will be described with reference to FIG. 1 and FIG. 2 which shows the state of operation of the circuit in a waveform diagram. The delay unit 1A receives the supply of the input signal VI from the input terminal TI. TN1 and TN2 after the elapse of a predetermined delay time
From the waveform shaping unit 2 as drive signals Vn1 and Vn2.
Output to A. The waveform shaping unit 2A outputs these drive signals Vn
1 and Vn2 are shaped and output from the output terminal TO as an in-phase output signal VO.

As a method of determining circuit constants, design is made so as to satisfy the following conditions. That is, the transistors N12,
The threshold voltage of each of N13 and P12 is VTN
1, VTN2 and VTP1, VDD> | VTP1
| + VTN2 + VTN1 needs to be designed. Because, when | VTP1 | + VTN2 + VTN1 becomes larger than VDD, the transistors N12 and N1
3, the potential difference between the gate and the drain of P12 becomes smaller than the threshold voltage of each of the transistors N12, N13, and P12, so that each transistor is always shut off. Therefore, the drive signal Vn to the waveform shaping unit 2A
This is because the potentials of 1 and Vn2 become a certain value regardless of the potential of the input signal VI, and the circuit does not operate. Further, it is preferable that | VTP1 | + VTN2 + VTN1 be larger. This is because if this value is large, a large delay value can be obtained.

The input signal VI supplied from the input terminal TI
Is input to the gates of the transistor N11 and the transistor P11 to turn on or off each element. Hereinafter, for convenience of description, the description will be made with reference to the level of the input signal VI.

When the input signal VI is at the H level, the drive signal V
The initial potential of n1 becomes VDD− | VTP1 |. Also,
The initial potential of the drive signal Vn2 is VDD− | VTP1 | −V
TN2. The transistor N11 becomes conductive and the drain potential becomes the same as the ground potential. Here, the potential of the drain of the transistor N12 drops to VTN1 as shown. Here, since the source potential and the back gate potential of the transistor N12 are the ground potential G and are substantially equal, there is no back gate effect, and the threshold voltage VTN1 of the transistor N12 becomes the same as the threshold voltage of the transistor N21. Therefore, the potential of the drive signal Vn2 continues to drop until the transistor N12 is turned off.
Can also be cut off, and the potential of the drive signal Vn2 is G + V
TN1. Therefore, the path through which the steady current flows is cut off, and no current flows.

At this time, since the potential of the drive signal Vn2 decreases, the potential of the drive signal Vn1 also decreases. The potential is the sum of the threshold voltages VTN1 and VTN2 of the transistors N12 and N13, G + VTN1 + VTN2
It is. As a result, the potential of the drive signal Vn1 decreases, the transistor P21 conducts, the potential of the output terminal TO increases, and the VDD level is output as the output signal VO.

Next, when the input signal VI is at the L level, the transistor P11 is turned on and the drain / gate of the transistor P12 and the drain / gate of the transistor N13 are turned on.
The gate, that is, the potential of the drive signal Vn1 is VDD− | VT
P1 |. Here, since the source potential and the back gate potential of the transistor P12 are substantially equal to the power supply potential VDD, there is no back gate effect, and the threshold voltage VTP1 of the transistor P12 becomes the same as the threshold voltage of the transistor P21. Therefore, the drive signal Vn1 becomes VDD−
| VTP1 |, and the transistor P12 is cut off. Here, the threshold voltage of transistor P21 is also | VTP1.
Therefore, the transistor P21 is also shut off, and therefore, the inflow path of the steady current is shut off.

On the other hand, the potential of the source of the transistor N13 becomes VDD− | VTP1 | −VTN2, the gate potential of the transistor N21 rises, and the transistor N21 becomes conductive. Therefore, the same level as the ground potential G is output from the output terminal TO as the output signal VO.

Next, the Nch and P described in the prior art
Referring again to FIGS. 14A and 14B, which are characteristic diagrams showing the relationship between the potential difference (hereinafter VBS) between the back gate and the source of each transistor of each channel and the threshold voltages VTN and VTP, respectively, referring to FIG. When the VBS / threshold voltage characteristic including the back gate effect of each transistor has the same size as that of the conventional delay circuit according to this figure at the time of transition from the H level to the H level, the delay circuit per stage of the present embodiment has The calculated delay time is about 2.37 ns. Therefore, in order to generate a delay time of 20 ns as in the related art, nine stages of cascade connection are required.

As in the conventional case, when the gate width of the transistor is 13 μm and the gate length is 0.6 μm, the area occupied by one transistor is about 18 μm × 7 μm = 1.2.
6 × a 10- ⁴ mm ^2, because it requires seven per unit circuits 1-stage transistor, layout total area,
1.26 × 10-4 × 7 × 9 = 7.94 × 10- 3 mm
It becomes ² .

The delay circuit of the present embodiment has a smaller variance in delay time due to manufacturing dispersion than the third conventional delay circuit. The reason is shown below.

The dispersion of the delay time due to the manufacturing dispersion of the delay circuit of this embodiment is determined by the transistor P2 of the waveform shaping section 2A.
1 and N21 as drive signals Vn1 and Vn2.
, The potential can be replaced with the dispersion of the potentials of these drive signals Vn1 and Vn2. As described above, the drive signals Vn1 and Vn2 are VDD− | VTP1 | when the input signal VI is at the L level and G + VTN when the input signal VI is at the H level.
1 + VTN2. The drive signal Vn2 is VDD- | VTP1 | -VTN2 when the input level is L level,
At the time of H level, it becomes G + VTN1. Changes in these potentials due to manufacturing dispersion will be described below.

Referring again to FIGS. 14A and 14B,
A case will be described as an example where the VBS / threshold voltage characteristic of each of the Nch and Pch transistors having the largest delay time variance in the conventional estimation of the delay time in consideration of the manufacturing dispersion follows VTSN and VTSP, respectively.

First, when the input signal VI is at the H level, the initial potential of the drive signal Vn1 is VDD− | VTP1 | −dFP
It becomes 0. The initial potential of the drive signal Vn2 is VDD-
| VTP1 | -dSP0-VTN2-dSN. Therefore, the transistor N11 conducts, and the drain potential of the transistor N11 becomes equal to the ground potential G. Here, the drain potential of the transistor N12 is VTN1 + d
It descends to SP0. At this time, since the potential of the drive signal Vn2 decreases, the potential of the drive signal Vn1 also decreases.
The potential is equal to the VT of each of the transistors N12 and N13.
Addition value of N1, VTN2 and increase or decrease due to manufacturing dispersion, G + VTN1 + dSP0 + VTN2 + d
SN. As a result, the potential of the drive signal Vn1 decreases, the transistor P21 conducts, the potential of the output terminal TO increases, and the VDD level is output as the output signal VO.

Next, when the input signal VI is at the L level, the transistor P11 is turned on, and the potential of the drain / gate and the drain / gate of the transistor N13, that is, the drive signal Vn1 becomes VDD-│VTP1│-dSP0. Therefore, the source potential of the transistor N13 is VDD
-| VTP1 | -dSP0-VTN2-dSN,
The gate potential of the transistor N21 rises and becomes conductive. Thus, the output signal VO of the ground potential G is output from the output terminal TO.

Next, referring to FIG. 3 which is a characteristic diagram showing the input signal VI of the waveform shaping section 2A and the VGS-IDS characteristics of each of the transistors P21 and N21, the IDT shown in FIG.
N and IDTP show the standard VGS-IDS characteristics when there is no manufacturing dispersion of the Nch and Pch transistors, respectively, and IDSN and IDSP show the case where the delay time becomes maximum due to the manufacturing dispersion, that is, the upper limit VGS-IDS.
IDFN and IDFP indicate the case where the delay time is minimized due to manufacturing dispersion, that is, the lower limit VGS-IDS characteristics, respectively. VnNT1 and VnPT1 are the values of the drive signals Vn1 and Vn2 in the standard state, VnN, respectively.
S1 and VnPS1 respectively represent the values of the drive signals Vn1 and Vn2 when the delay time is in the maximum state due to manufacturing dispersion.

Here, as compared with the conventional third delay circuit, the conventional third delay circuit determines the delay time at the next stage driving by the ratio of IDS. Then, it is determined by the absolute value of IDS. Thereby, delay time dispersion caused by manufacturing dispersion can be reduced.

The reason is that when the input signal VI is at the L level, the values VnNT1 and VnNS of the drive signals Vn1 and Vn2 are set.
1 is the leftmost voltage in the graphs of IDTN and IDSN, the transistor N21 is turned off, and IDS is 0. On the other hand, the values VnPT1 and VnPT of the drive signals Vn1 and Vn2
nPS1 becomes the voltage at the left end of the graph of IDTPN and IDSP, and the transistor P21 becomes conductive, the IDS flows, and the value depends on the IDS of each transistor. For the same reason, when the input signal VI is at the H level, the transistor N21 becomes conductive and depends on its IDS dispersion.

Here, the decisive difference from the third conventional delay circuit is that the third conventional delay circuit has a transistor P2
1 and N21, the IDSs themselves have a variation, that is, a variance, and the delay time is determined by the driving ability depending on the ratio of the IDSs including the variance. On the other hand, in the present embodiment, the transistor P21 , N21 always shuts off, so that the dispersion of the delay time depends only on the characteristic dispersion of the transistor that is conducting. Therefore, in the present embodiment, the dispersion of the delay time due to the manufacturing dispersion is smaller.

Next, Nch and P described in the prior art
Referring again to FIGS. 14A and 14B, which are characteristic diagrams showing the relationship between the potential difference between the back gate and the source of each channel transistor (hereinafter referred to as VBS) and the threshold voltages VTN and VTP. When the VBS / threshold voltage characteristic including the back gate effect of each transistor and having the same size according to this figure is calculated, the delay time per one stage of the delay circuit of this embodiment is calculated from the H level to the L level of the output signal VO. It becomes about 2.37 μs at the time of transition to. Therefore, in order to generate a delay time of 20 ns as in the related art, nine stages of cascade connection are required.

As in the conventional case, when the gate width of the transistor is 13 μm and the gate length is 0.6 μm, the area occupied by one transistor is about 18 μm × 7 μm = 1.2.
6 × a 10- ⁴ mm ^2, because it requires seven per unit circuits 1-stage transistor, layout total area,
1.26 × 10-4 × 7 × 9 = 7.94 × 10- 3 mm
It becomes ² .

The delay time of the circuit shown in FIG. 1 is changed from the L level of the output signal VO to the H level in a standard state without manufacturing dispersion.
3.27 ns at the time of transition to the level and 2.37 ns as described above at the time of transition from the H level to the L level.

The condition in which the variation of the delay value is largest in the estimation of the delay value in consideration of the manufacturing dispersion in the conventional third delay circuit, that is, the VBS of the Nch transistor
In the case where the / threshold voltage characteristic conforms to VTSN and the VBS of the Pch transistor conforms to VTFP, that is, in the FS state, in the present embodiment, output signal V
6.38 ns when O transitions from L level to H level, H
The transition time from the level to the L level is 4.76 ns.

From this, the dispersion of the delay time due to the manufacturing dispersion of the delay circuit of this embodiment is 1.9 times when the output signal VO transitions from the L level to the H level, and from the H level to the L level.
At the time of transition to the level, it is 2.0 times, which is improved compared to the conventional 2.9 times and 4.7 times, respectively.

Next, a second embodiment of the present invention will be described with reference to FIG. 4 in which constituent elements common to those in FIG. This embodiment is different from the above-described first embodiment in that a delay unit 1B including a transistor P13 instead of the transistor N13 is provided instead of the delay unit 1A.

The role of the transistor N13 in the first embodiment is to maintain a large potential difference between the drive signals Vn1 and Vn2 and to reduce the amplitude of each of the drive signals Vn1 and Vn2. Therefore, there is no limitation on the circuit type as long as the circuit can perform the same function. In the case of the present embodiment, the transistor P13 is the first
It is clear that the same operation as the transistor N13 of the embodiment can be achieved. Therefore, in consideration of the threshold voltage fluctuation due to the manufacturing dispersion of the transistor elements, the restriction on the layout, and the like, the transistor of the Nch or Pch type, whichever is the best, can be used.

Next, a third embodiment of the present invention will be described with reference to FIG. 5 in which constituent elements common to those in FIG. This embodiment is different from the above-described first embodiment in that transistors P11, P12, and N1 are used instead of the delay unit 1A.
1, N12, and N13 are provided with a delay unit 1C in which each back gate is connected to each source.

As a result, the transistors P11, P11,
Each of P12, N11, N12, and N13 has a VBS of 0.
Since V becomes V, the threshold voltage is kept constant without being affected by the back gate effect, and the threshold voltage fluctuation due to manufacturing dispersion can be minimized. Therefore,
VD, which is a condition for determining the circuit constant of this delay circuit,
D> | VTP1 | + VTN2 + VTN1 variance on the right side can be suppressed to a minimum.

In the fourth embodiment of the present invention, similarly to the third embodiment, the back gates of the transistors P11, P12, P13, N11, and N12 in the second embodiment are respectively set. (Not shown).

Next, a fifth embodiment of the present invention will be described with reference to FIG. 6 in which constituent elements common to those in FIG. This embodiment is different from the above-described first embodiment in that a delay unit 1D further including a transistor N14 connected in series with a transistor N13 between nodes TN1 and TN2 is provided instead of the delay unit 1A. . That is, the gate and the drain are commonly connected, connected to the drain of the transistor P12, and the source is connected to the drain of the transistor N13.

As a result, the drive signals Vn1, Vn
The potential difference of n2 can be increased, and transistors P21 and N2
1 to the conductive state is applied to these transistors P2
1, the threshold voltage of N21 can be approached, and the delay time can be further increased.

Under the same conditions as in the first embodiment, the delay time of the circuit of this embodiment is 20.34 ns. Therefore, the number of stages required for generating the delay time of 20 ns may be one. The number of transistors per stage of the delay circuit of this embodiment is eight. Therefore, when transistors of the same size are used, the total layout area of the circuit is 1.26.
× 10 −4 × 1 × 8 = 1.01 × 10 ⁻³ mm ² . That is, it is only about に of the first embodiment.

Next, a sixth embodiment of the present invention will be described with reference to FIG. 7 in which constituent elements common to those in FIG. This embodiment is different from the above-described first embodiment in that an Nch transistor N41 having a gate and a drain connected in common between the nodes TN1 and TN2 and connected to the drain of the transistor P11 instead of the delay section 1A. A delay unit 1E including a transistor P41 having a gate and a drain connected in common and connected to the drain of the transistor N11 and a source connected to the source of the transistor N41.

The back gates of the transistors P11 and P41 are connected to the power supply VDD, and the transistors N11 and P41 are connected.
The back gate of N41 is connected to ground G.

First, a circuit constant is determined so as to satisfy the following conditions. That is, the threshold voltages of the transistors N41 and P41 including the back gate effect are VTN1 and VTP1, respectively, and the threshold voltages of the transistors N21 and P21 are VTN2 and VTN, respectively.
Assuming that TP2, when the input signal VI is at L level, VD
D-VTN2> VTN1 + | VTP1 |, input signal VI
Is high, VDD− | VTP2 |> VTN1 +
| VTP1 | must be designed to be satisfied.

First, when the input signal VI is at the L level, | VTP1 | + VTN1 becomes VDD−VTN2.
If it becomes larger, the gate drive voltage Vn2 of the transistor N21 is always lower than VTN2, so that the transistor N21 is always cut off, and the output signal VO does not become L level. When the input signal VI is at the H level, V
When TN1 + | VTP1 | becomes larger than VDD- | VTP2 |, the gate drive voltage Vn1 of the transistor P21
Is always larger than VDD− | VTP2 |, so that the output signal VO does not go to the H level because the output signal VO does not become H level. In addition, it is preferable that | VTP1 | + VTN1 be as large as possible without violating the above conditions. This is because if this value is large, a large delay value can be obtained.

Next, the operation will be described with reference to FIG. 7 and FIG. 8 showing operation waveforms. First, when the input signal VI is at L level, the transistor P11 becomes conductive and the drain goes to H level. At this time, the gate and the drain of the transistor N41 are also at the H level, which is the drive signal Vn1. Therefore, the transistor P21 is turned off. The source of the transistor N41 has a voltage lower than the H level of the drain by the threshold voltage VTN1. The drain / source of the transistor P41 is VDD-VTN1
− | VTP1 |. Circuit constant determination condition VDD
Since −VTN2> VTN1− | VTP1 |, the voltage of the gate of the transistor N21 becomes higher than VTN2, and the transistor N21 conducts to delay and output the L-level output signal VO.

When the input signal VI is at the H level, the transistor N11 is turned on, and the drain, that is, the drive signal Vn2 and the gate and drain of the transistor P41 are at the L level. Therefore, the source of the transistor P41 and the source of the transistor N41 have a potential higher than the L level by | VTP1 |. Here, when the L level is set to 0 V, the source potential of the transistor N41 becomes “| VTP1 |”. And the transistor N41
Gate / drain is VTN1 more than | VTP1 |
And the drive signal Vn1 becomes | VTP1 | + VT.
N1. Circuit constant determination condition VDD- | VTP2 |>
From VTN1 + | VTP1 |, the gate of the transistor P21 becomes less than VDD- | VTP2 | and becomes conductive, delaying and outputting the H-level output signal VO.

The delay time of the delay circuit of the present embodiment is 3.
When the delay value is 48 ns, and a delay value of about 20 ns is made as in the other embodiments, a cascade connection of six stages is sufficient. 1 of this circuit
Since the number of transistors per transistor is 7, the total layout area is 1.26 × 10 −4 × 7 × 6 = 5.29
× 10 ⁻³ mm ² .

Next, a sixth embodiment of the present invention will be described with reference to FIG. 9 in which components common to those in FIG. The present embodiment is different from the above-mentioned sixty-first embodiment in that the source is connected to the drain of the transistor P11 and the gate and the drain are commonly connected between the nodes TN1 and TN2 instead of the delay section 1A. A delay unit 1F including a transistor P42, a transistor N42 having a gate and a drain connected in common, connected to the drain of the transistor P42, and a source connected to the drain of the transistor N11.

That is, the connection order of the transistors P41 and N41 of the sixth embodiment is
42 and N42, and the operation is the same.

The present invention is not limited to the above-described embodiment, and it goes without saying that various modifications and applications can be made without departing from the spirit of the present invention.

In particular, in the delay section, the connection method of each transistor and the way of applying the back gate potential are such that, when each transistor of the waveform shaping section is cut off, a voltage lower than the threshold voltage of each transistor can be supplied; The circuit type can be freely selected as long as a means for maintaining the conduction state of each transistor of the waveform shaping section near the threshold voltage of each transistor can be established.

Although the input logic and output logic of the delay circuit of the present invention have all been described as being in phase, they need not be in phase but may be in opposite phases.

Next, in the waveform shaping section, the circuit format can be freely selected by using means for shaping the waveform generated by the delay section, without being limited to the embodiment. Further, in addition to the function of causing the waveform shaping unit to shape the waveform, a circuit configuration having a complex function other than increasing the delay time may be provided by providing other circuit functions.

For example, the waveform shaping section inputs another control signal from the outside to the waveform shaping section, and logically combines the control signal and the signal output from the delay section of the present invention and input to the waveform shaping section. Alternatively, a waveform shaping unit that obtains a desired output logic and delay time may be used.

More specifically, a NAND operation is performed between the two drive signals of the delay unit and the external control signal, and this NAND gate is used as a waveform shaping unit. The output terminal of the shaping section always outputs the H level, and when the control signal is at the H level, it is possible to add control such that a signal whose logic is inverted between the two drive signals of the delay section is output. is there.

Further, the circuit configuration of the waveform shaping section is similar to the circuit configuration of the delay section, except that Pch, Nc
(h) By connecting another transistor in series with each transistor, the driving capability may be reduced, and a variation that further increases the delay time may be considered.

[0099]

As described above, the delay circuit according to the present invention includes the fifth transistor inserted in series between the output terminals of the first and second drive signals of the delay section, so that these first transistors are provided. Since the potential difference between the second drive signal and the potential difference between the source and gate of each transistor in the waveform shaping section can be reduced, the layout area of the delay circuit for obtaining a desired delay time can be reduced.

Further, since one of the transistors of the waveform shaping section is always in the cutoff state, the conventional problem of the steady current can be eliminated, and the power consumption can be reduced.

Further, since one transistor of the waveform shaping circuit is always cut off and the driving capability depends only on the saturation current (IDS) characteristics of the transistor on the conduction side, the influence of manufacturing dispersion on the delay time can be reduced. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a delay circuit according to the present invention.

FIG. 2 is a waveform chart showing an example of the operation of the delay circuit of the present embodiment.

FIG. 3 is a characteristic diagram illustrating an IDS characteristic of each transistor with respect to an input voltage in a waveform shaping unit of the delay circuit according to the present embodiment.

FIG. 4 is a block diagram showing a second embodiment of the delay circuit of the present invention.

FIG. 5 is a block diagram showing a third embodiment of the delay circuit of the present invention.

FIG. 6 is a block diagram showing a fifth embodiment of the delay circuit of the present invention.

FIG. 7 is a block diagram showing a sixth embodiment of the delay circuit of the present invention.

FIG. 8 is a waveform chart showing an example of the operation of the delay circuit of the present embodiment.

FIG. 9 is a block diagram showing a seventh embodiment of the delay circuit of the present invention.

FIG. 10 is a block diagram showing an example of a conventional first delay circuit.

FIG. 11 is a block diagram showing an example of a conventional second delay circuit.

FIG. 12 is a block diagram showing an example of a conventional third delay circuit.

FIG. 13 is a waveform chart showing an example of the operation of the conventional delay circuit.

FIG. 14 is a characteristic diagram showing a relationship between a potential difference between a back gate and a source of each of Nch and Pch transistors and a threshold voltage.

FIG. 15 is a characteristic diagram illustrating an input voltage-output current characteristic of the waveform shaping unit.

[Explanation of symbols]

1, 1A, 1B, 1C, 1D, 1E, 1F Delay unit 2, 2A Waveform shaping unit 101, 102, 201-204 Inverter N11-N14, N31, N41, N42, N101-
N104, N201 to N204, P11 to P13, P3
1, P41, P42, P101 to P104, P201 to
P204 transistor

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-5-291940 (JP, A) JP-A-6-244701 (JP, A) JP-A-5-206803 (JP, A) US Pat. U.S. Pat. No. 5,471,150 (US, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 5/13 H03K 19/0948

Claims (7)

(57) [Claims] 1. A delay section for receiving a supply of an input signal and delaying the input signal to output a drive signal, and in response to the supply of the drive signal, delaying the input signal by a predetermined time and shaping the input signal to a predetermined amplitude. A delay circuit including a waveform shaping unit that outputs an output signal, wherein the delay unit has a first transistor of a first conductivity type having a gate connected to an input terminal and a source and a substrate electrode connected to a first power supply, respectively; A gate connected to the source of the first transistor and a source ;
A second transistor of a second conductivity type having a plate electrode connected to a second power supply, and a gate and a drain commonly connected to each other to output a first drive signal and a source to a drain of the first transistor substrate
A third transistor of a first conductivity type having an electrode connected to the first power supply ; a gate and a drain commonly connected to each other to output a second drive signal; and a source connected to a drain of the second transistor. substrate
A fourth transistor of a second conductivity type having an electrode connected to the second power supply, and a first current terminal, which is one of a source and a drain, connected to the drain of the third transistor. A fifth transistor having a second current terminal connected to the drain of the fourth transistor, and a gate and a drain commonly connected, the waveform shaping unit receiving the first drive signal at the gate. A sixth transistor of a first conductivity type having a source connected to the first power supply, a drain connected to the output terminal and a substrate electrode connected to the first power supply, and a gate for supplying the second drive signal. receiving second conductivity type which is connected to the substrate electrode to a drain of said connection to drain to the second power supply sixth transistor source to said second power supply seventh transistor of Delay circuit, characterized in that it comprises and. Wherein said fifth transistor is a second conductivity type, said first and second current terminals Ri Oh drain and source, respectively, connect the substrate electrode to the second power supply
2. The delay circuit according to claim 1, wherein Wherein said fifth transistor is a first conductivity type, said first and second current terminals Ri source and drain der respectively, connect the substrate electrode to the first power supply
2. The delay circuit according to claim 1, wherein 4. A delay section for receiving a supply of an input signal and delaying the input signal to output a drive signal, and in response to the supply of the drive signal, delaying the input signal by a predetermined time and shaping the input signal to a predetermined amplitude. A delay circuit including a waveform shaping unit that outputs an output signal, wherein the delay unit includes a first transistor of a first conductivity type having a gate connected to an input terminal and a source connected to a first power supply, and A second transistor of a second conductivity type having a source connected to a second power supply and a gate connected to the gate of the first transistor, and a gate and a drain connected in common to output a first drive signal and change the source to the second of the first conductivity type connected to the drain of the first transistor third transistor and a gate and a drain and a common connection to the drain of the second driving signal output the source to the second transistor A fourth transistor of a second conductivity type connected to the second transistor; a first current terminal, one of a source and a drain, connected to the drain of the third transistor; And a fifth transistor connected to the drain of the fourth transistor and having a gate and a drain connected in common, wherein the waveform shaping unit receives the first drive signal at the gate and changes the source to the first power supply. A sixth transistor of the first conductivity type, the drain of which is connected to the output terminal; the second drive signal being supplied to the gate, the source being connected to the second power supply, and the drain being the sixth transistor. A seventh transistor of a second conductivity type connected to the drain of the transistor, wherein substrate electrodes of the first to seventh transistors are connected to respective sources. Circuit. 5. An apparatus for receiving an input signal and delaying the input signal.
A delay unit that outputs a drive signal,
Predetermined time slow cast predetermined vibration from said input signal in response to the sheet
A waveform shaping unit that outputs an output signal shaped to a width
In the delay circuit, the delay unit includes a first transistor of a first conductivity type having a gate connected to an input terminal and a source and a substrate electrode connected to a first power supply, respectively, and a gate connected to a source of the first transistor. And base
A second transistor of a second conductivity type having a plate electrode connected to a second power supply, and a gate and a drain commonly connected to each other to output a first drive signal and a source to a drain of the first transistor substrate
A third transistor of a first conductivity type having an electrode connected to the first power supply ; a gate and a drain commonly connected to each other to output a second drive signal; and a source connected to a drain of the second transistor. substrate
A fourth transistor of a second conductivity type having an electrode connected to the second power source, and a first current terminal that is one of a source and a drain connected to a drain of the third transistor, respectively, A fifth transistor having a drain and a common connection, a first current terminal that is one of a source and a drain being connected to a second current terminal of the fifth transistor, and a second current terminal being the other. fourth respectively connected retarded <br/> extending circuit anda sixth transistor of said fifth transistor of the same conductivity type to the drain of the transistor. 6. An input signal is supplied and the input signal is delayed.
A delay unit that outputs a drive signal,
The input signal is delayed by a predetermined time in response to
A waveform shaping unit that outputs an output signal shaped to a width
In the delay circuit, the delay unit includes a first transistor of a first conductivity type having a gate connected to an input terminal and a source and a substrate electrode connected to a first power supply, respectively, and a gate connected to a source of the first transistor. And base
A second transistor of a second conductivity type having a plate electrode connected to a second power source; and a gate and a drain commonly connected to output the first drive signal and to a drain of the first transistor. A third transistor of a second conductivity type having a substrate electrode connected to the second power source ; a gate and a drain commonly connected to output the second drive signal and a drain of the second transistor; And the source is based on the source of the third transistor.
Slow <br/> extending circuit you anda fourth transistor of the first conductivity type which is connected to the plate electrode to the first power supply. 7. An input signal is supplied and the input signal is delayed.
A delay unit that outputs a drive signal,
The input signal is delayed by a predetermined time in response to
A waveform shaping unit that outputs an output signal shaped to a width
In the delay circuit, the delay unit includes a first transistor of a first conductivity type having a gate connected to an input terminal and a source and a substrate electrode connected to a first power supply, respectively, and a gate connected to a source of the first transistor. And base
A second transistor of a second conductivity type having a plate electrode connected to a second power supply, and a source connected to the drain of the first transistor to output the first drive signal and to form a gate and a drain. A third transistor of a first conductivity type having a common connection and a substrate electrode connected to the first power supply ; a gate and a drain commonly connected to each other and a substrate electrode connected to the drain of the third transistor; A fourth transistor of a second conductivity type , each of which is connected to a power supply of the second type and has a source connected to the drain of the second transistor to output the second drive signal. delay circuit you.