JP3007425B2 - IC card - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC for making it possible to use an application having a different address system in a storage area.
About the card.

[0001]

2. Description of the Related Art As is well known, in recent years, cards generally referred to as so-called IC cards have been widely used. For example, CP cards are used in bank cards, ID cards, credit cards, and the like.
U and IC cards with a built-in memory, and IC memory cards with only a memory for simply storing data as an external storage device such as an electronic organizer or a portable personal computer are used.

As a storage means mounted on this kind of card, a nonvolatile memory such as a ROM and an E ² PROM, or a volatile memory such as a DRAM and an SRAM is used. In particular, in an IC card with a built-in CPU and memory,
2. Description of the Related Art A microprocessor in which both are incorporated and formed on one chip is often used. Such an IC card transmits and receives data via a card reader / writer. Each of the IC cards accesses the memory of the IC card by a built-in CPU.
The access to the memory of the memory card is performed by
The processing is performed by the CPU on the terminal side.

At the time of this access, data is read and written according to a predetermined memory address system. The address method includes a logical address method, a physical address method, and a record management method. First, the logical address method is a method in which an address space of the memory is defined by a relative address defined in software for managing the memory, and a predetermined storage area is accessed based on the relative address. . This relative address is converted into an actual memory address (absolute address) by a predetermined conversion table. The physical address method is a method in which an address space is defined by the absolute address and a predetermined storage area is accessed based on the absolute address. The record management method is a method of dividing a storage area on a memory into records of a predetermined data length, and managing the storage area using a record number or a record pointer for identifying the divided record. Therefore, when data is transmitted and received, an application compliant with the applicable card addressing system is provided, and data is read and written based on the application.

[0004]

The conventional IC
In the card, the storage area of the memory is managed by any of the above-described various address systems, and various applications corresponding to these address systems are mixed. Therefore, in order to make the IC card compatible with applications of different address systems,
A microchip for individually managing these addressing schemes must be provided in the card. In such a case,
This leads to various inconveniences such as an increase in the cost of the card.
For this reason, in reality, there is a disadvantage that data on the card cannot be accessed unless the application is compatible with the address method of the IC card. The present invention has been made in view of the above circumstances, and has as its object to provide an IC card that can easily cope with applications having different address systems.

[0005]

As shown in FIG. 1, the present invention has a storage area divided into at least two or more sections.
And attribute information b for identifying an address method for each storage area.
Storage means a provided with an area of
Control means c for input / output control by a corresponding address method;
It is characterized by comprising.

[0006]

According to the above arrangement, the storage means a has at least
Also recognizes the address method for each of the two or more divided storage areas.
There is provided another area for attribute information b, and the control means c
Input / output control by address method corresponding to the area of attribute information b
Do. As a result, it is possible to cope with applications having different address systems.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. A. FIG. 2 is a block diagram showing a configuration of an embodiment according to the present invention. As shown in this figure, the IC card 11 has an I / O 12 for transmitting and receiving commands and data to and from the card reader / writer 21 and an E / O 12 for storing a command processing or data processing program and data.
An EPROM 13, a CPU 14 for controlling data communication and performing data processing based on these programs,
RAM used as a work area of the CPU 14
15 is provided.

A card reader / writer 21 for exchanging data with the IC card 11 has an I / O 21
, A ROM 23, a CPU 24, and a RAM 25. In addition, this card reader / writer 21
Data communication can be performed with the host computer via a communication line.

In this IC card 11, EEPRO
The storage area of M13 is divided into a system area for storing system information and a user area for storing user information, and has a file structure shown in FIG. As shown in FIG. 3, the IC card 11 has three root directories RT1 to RT3 under the system directory SD, and these are used for file management. Here, the directory RT1
Is an area where the above-mentioned physical address file is managed, directory RT2 is an area where the above-mentioned logical address file is managed, and directory RT3 is a directory RT3.
Is an area in which a file of the record management method described above is managed. As described above, the IC card according to the present embodiment is configured such that a predetermined area of the memory is divided into three, and each is managed by each address method. This IC card is provided with a CPU so that file management of each address method is performed.

Address management information is registered in each of the directories RT1 to RT3 in the format shown in FIG. 4A shows the management format of the physical address system, FIG. 4B shows the management format of the logical address system, and FIG. 4C shows the management format of the record management system. In this figure, F1 to Fn are frames of a predetermined byte length forming each of the above formats. For example, F1 is an 8-byte length frame in which a file name is registered, and F2 is a storage format for identifying the above-described addressing system.
This is a byte-length frame. F3 is the frame F1
Is a frame in which the head address of the file name defined in the above is registered. Fn is a block check code, which is used when checking this address management information.

FIG. 5 is a diagram showing a description format of the frame F2. As shown in FIG.
The address system is identified by bits. In this frame F2, for example, the lower three bits are “0”.
"01" indicates the physical address method, "010" indicates the logical address method, and "100" indicates the record management method. When the lower three bits indicate the physical address system, the frames F4, F5, and F6 in FIG. 4A are all unused. On the other hand, when the lower three bits indicate the logical address system, the address pointer is registered in the frame F5 in FIG. 4B and the area size is registered in the frame F6. The address pointer indicates an input address of a conversion table used for converting a logical address into an absolute (physical) address. When the lower three bits indicate the record management method,
(C) The number of stored records is registered in frame F4, and the next record number and frame F are stored in frame F5.
6, the record size is registered.

B. Operation of Embodiment Next, an operation when accessing the IC card 11 having the above configuration will be described with reference to FIGS. In the description of the operation, it is assumed that the IC card 11 is set in the card reader / writer 21 and a predetermined file is accessed by the card reader / writer 21. First, when the IC card 11 is set in the card reader / writer 21, the CPU 14 mounted inside the card is used.
Starts. Thus, the main routine shown in FIG. 6 starts, and the process proceeds to step Sa1. In step Sa1,
After initialization is performed and various internal registers and the like are reset, ATR information (information indicating that the reset has been performed) is output to the card reader / writer 21 side. Next, when the process proceeds to step Sa2, the CPU enters a standby state until receiving a command from the card reader / writer. Here, when various commands, which will be described later, are received from the card reader / writer, the result of the determination in step Sa2 is "YES", and the flow proceeds to the next step Sa3. In step Sa3, a command processing routine corresponding to the received command is executed. Then, in step Sa4, the execution result of this command processing routine is sent to the card reader / writer as response data based on a predetermined format. Then, thereafter, the above-described step Sa2
To Sa4 are repeated.

In the following, steps Sa2 to S
In the operation a4, a case where a file of each address method described above is accessed will be described in detail. Operation when opening a predetermined file In this case, the IC card 1 is read from the card reader / writer 21 side.
1 is supplied with an open command. The command format of the open command is as shown in FIG. When such an open command is supplied, the determination result of step Sa2 in the main routine described above becomes “YES”, and the process proceeds to step Sa3.
Thus, the open command processing routine shown in FIG. 7 is started, and the process proceeds to step Sb1. In step Sb1, the status data STS1 is set to “0”, and the process proceeds to the next step Sb2. Here, the status data STS1
Is data indicating the presence or absence of an error in the command processing routine. In step Sb2, the above-mentioned root directories RT1 to RT3 are searched based on the file name FN given to the open command. In step Sb3, it is determined whether a file corresponding to the file name FN exists as a result of the search. Here, when a file corresponding to the file name FN exists, the determination result is “YES”, and the process proceeds to the next step Sb4. In step Sb4, the head address of the file is set in the frame F3 of the directory where the file exists. Next, in step Sb5,
The address management information of this directory is read, and this routine ends.

On the other hand, if the result of the determination in step Sb3 is "NO", that is, if there is no file corresponding to the file name FN assigned to the open command, the process proceeds to step Sb6. In step Sb6, "4" is added to the status data STS1, and this routine ends. Then, the processing of the CPU 14 returns from the open command processing routine to the main routine, and the response transmission processing (step Sa4) is performed. In the response transmission process in this case, the response data in the format shown in FIG.
Is sent to the card reader / writer 21 side. here,
If the status data STS1 is “4”, the card reader / writer 21 displays an error indicating that the corresponding file does not exist.

Operation when Accessing a File of Physical Address Method When a file opened by the above-described open command processing is managed by the physical address method, the following read operation and write operation are performed. a. Read Operation In this read operation, a read command in the format shown in FIG. 10A is supplied from the card reader / writer 21 to the IC card 11. When such a read command is supplied, the read command processing routine shown in FIG. 9 is started, and the processing of the CPU 14 is executed in step Sc.
Proceed to 1. In step Sc1, the status data ST
S1 is set to “0”, and the process proceeds to the next step Sc2. In step Sc2, it is determined whether or not the frame F2 of the directory RT1 has a storage format representing a physical address.
If the lower three bits of the frame F2 are "001", the result of this determination is "YES", and the flow proceeds to step Sc3. In step Sc3, the address RA assigned to the read command is read, and this is set in an internal register. Next, in step Sc4, the data of the file is sequentially read from this address RA. At the time of this read, the data length LEN (see FIG. 10A) included in the read command is used as a read unit. Next, in step Sc5, it is determined whether there is an address error in reading for each data length LEN. If there is no error, step Sc
The program proceeds to step 6, where the read data is set in an output buffer (not shown), and this routine is terminated.

On the other hand, if the result of the determination in step Sc2 is "NO", that is, if the file is not of the physical address type, the flow advances to step Sc7 to add "1" to the status data STS1. If there is an address error at the time of reading, step S
The result of the determination at c5 is "NO", the flow proceeds to step Sc8, and "1" is further added to the status data STS1. When the processing of the CPU 14 shifts to the response transmission processing (step Sa4) of the main routine, response data in the format shown in FIG. 10B is transmitted from the IC card 11 to the card reader / writer 21. As a result, the read data is received by the card reader / writer 21 side. The status data STS1 in the response data is "2".
In the case of (1), the card reader / writer 21 displays an error indicating that there is an error in the above-described read command processing.

B. Write operation In this write operation, the card reader / writer 21
A write command in the format shown in FIG. When such a write command is supplied, a write command processing routine shown in FIG. 11 is started, and the process proceeds to step Sd1. Step Sd1
Then, the status data STS1 is set to "0", and the process proceeds to the next step Sd2. In step Sd2, it is determined whether or not the frame F2 of the directory RT1 has a storage format representing a physical address. If the lower three bits of the frame F2 are "001", the result of this determination is "YES", and the flow proceeds to step Sd3. In step Sd3, the write address WA assigned to the write command is read and set in an internal register.
Next, in step Sd4, it is determined whether the write area of the opened file is insufficient. If the write area is not insufficient, the determination result is "NO", and the flow advances to the next step Sd5. In step Sc5, the write data WD added to the write command is written sequentially from the write address WA, and this routine ends.

On the other hand, if the result of the determination in step Sd2 is "NO", that is, if the file is not of the physical address type, the process proceeds to step Sd6, where "2" is added to the status data STS1. If the file writing area is insufficient, step S
The result of the determination at d4 is "YES", the process proceeds to step Sd7, and "1" is further added to the status data STS1. When the processing of the CPU shifts to the response transmission processing of the main routine (step Sa4), FIG.
Response data in the format shown in 2 (b) is an IC
It is sent from the card 11 to the card reader / writer 21 side. Here, if the status data STS1 of the response data is “3”, the card reader / writer 21 displays an error indicating that there is an error in the above-described write command processing.

Operation for Accessing Logical Address System File When a file opened by the above-described open command processing is managed by the logical address system, the following read operation and write operation are performed. a. Read operation In this read operation, the IC is read from the card reader / writer side.
A read command in the format shown in FIG. 15A is supplied to the card. When such a read command is supplied, a read command processing routine shown in FIG. 13 is started, and the processing of the CPU 14 proceeds to step Se1. In Step Se1, the status data STS1 is set to “0”, and the process proceeds to the next Step Se2. Step Se
In 2, it is determined whether or not the frame F2 of the directory RT2 is described in a storage format representing a logical address. Then, the lower 3 bits of the frame F2 are set to “01”.
If it is "0", the result of this determination is "YES", and the flow proceeds to step Se3. In step Se3, the start address of the opened file is set. next,
In step Se4, the value of the address pointer registered in the frame F5 is set in the internal register.

Next, in step Se5, the set start address is converted into an absolute address according to the address pointer, and the data of the file is sequentially read from the absolute address. At the time of this read, the data length LEN (see FIG. 15A) included in the read command is used as a read unit. Next, step Se6
In, it is determined whether an EOF code indicating the end of the file is detected at the time of reading. Here, if this EOF code is not detected, since it is not the end of the file, no EOF error occurs, and the result of this determination is “NO”.
And the process proceeds to the next Step Se7. Then, in step Se7, the read data is set in an output buffer (not shown). Subsequently, in step Se8, the address pointer of the above-described frame F3 is updated to indicate the logical address after the completion of the reading, and this routine ends.

On the other hand, if the result of the determination in step Se2 is "NO", that is, if this file is not of the logical address type, the flow advances to step Se9 to add "1" to the status data STS1. When the end of the file is reached at the time of reading and an EOF error occurs, the determination result in step Se6 becomes “YES” and the process proceeds to step Se10, and “1” is further added to the status data STS1. I do. When the processing of the CPU 14 shifts to the response transmission processing (step Sa4) of the main routine described above, FIG.
Response data in the format shown in 5 (b) is sent from the IC card 11 to the card reader / writer 21 side. As a result, the read data is received by the card reader / writer 21 side. On the other hand, when the status data STS1 of the response data is “2”,
The card reader / writer 21 displays an error indicating that there is an error in the above-described read command processing.

B. Write Operation In this write operation, a write command in the format shown in FIG. 16A is supplied from the card reader / writer to the IC card. When such a write command is supplied, a write command processing routine shown in FIG. 14 is started, and the process proceeds to step Sf1. In step Sf1, the status data STS1 is set to “0”, and the next step Sf1 is executed.
Proceed to f2. In step Sf2, the directory RT2
It is determined whether or not the frame F2 has a storage format representing a logical address. If the lower 3 bits of the frame F2 are “010”, the result of this determination is “YE
S ", and proceeds to step Sf3. In step Sf3, the start address of the opened file is set,
Subsequently, in step Sf4, the value of the address pointer registered in the frame F5 of the directory RT2 is referred to, and this value is set in an internal register.

Next, in step Sf5, it is determined whether or not the file writing area is insufficient. If the write area is not insufficient, the result of the determination here is "NO", and the routine proceeds to the next step Sf6. In step Sf6, the set top address is converted into an absolute address according to the address pointer, and the write data WD assigned to the write command is written sequentially from this absolute address. Next, in step Sf7, the address pointer of the above-described frame F3 is updated so as to indicate the logical address after the completion of the writing, and this routine ends. On the other hand, if the result of the determination in step Sf2 is “NO”, that is, if the file is not of the logical address type, the process proceeds to step Sf8,
"2" is added to the status data STS1. Also,
If the file write area is insufficient, the result of the determination in step Sf5 is "YES" and the
9, the status data STS1 is further set to "1".
Is added.

When the processing of the CPU 14 shifts to the response transmission processing of the main routine (step Sa4), response data in the format shown in FIG. 16B is transmitted from the IC card 11 to the card reader / writer 21. You. Here, when the status data STS1 of the response data is “3”, the card reader / writer 21 displays an error indicating that there is an error in the above-described write command processing.

Operation when Accessing a File of Record Management Method When a file opened by the above-described open command processing is managed by a record management method, the following read operation and write operation are performed. a. Read operation In this read operation, the IC is read from the card reader / writer side.
A read command in the format shown in FIG. 19A is supplied to the card. The record number N in this format specifies the number of the record to be read. When this record number N is "0",
Indicates the next record number, and usually indicates the record number to be read in the range of 1 to 255. When such a read command is supplied, the read command processing routine shown in FIG. 17 is started, and the process proceeds to step Sg1.
In step Sg1, the status data STS1 is set to “0”, and the process proceeds to the next step Sg2. Step Sg
In 2, it is determined whether or not the frame F2 of the directory RT3 is described in a storage format representing record management. Then, the lower three bits of the frame F2 are set to “10”.
If it is "0", the result of this determination is "YES", and the flow proceeds to step Sg3. In step Sg3, the head address of the record in the opened file is read from frame F3. Then, in a step Sg4, it is determined whether or not the record number N is "0". Here, if the record number N is not “0”,
The result of the determination is "NO", and the routine proceeds to the next step Sg6. On the other hand, if the record number N is “0”, the result of this determination is “YES”, and the routine proceeds to step Sg5. In step Sg5, the next record number registered in the frame F5 is read and set in an internal register.

Next, in step Sg6, the frame F4
Then, it is determined whether or not the number of stored records read from is greater than or equal to the record number N to be read, that is, whether or not the record number N to be read is an appropriate value. Here, if the record number is a valid value, the determination result is “YES”, and the flow proceeds to the next step Sg7. In step Sg7, the record size of frame F6 is read, and this record size and record number N
An absolute address from which reading is to be started is determined from the starting address and the starting address. That is, a process of multiplying the record size by the next record number (N-1) and adding the result to the head address is performed. Then, in step Sg8, the data of the record is sequentially read from the absolute address obtained by such processing. Then, step S
In g9, the read data is set in an output buffer (not shown), and the routine ends.

On the other hand, if the result of the determination in step Sg2 is "NO", that is, if the file does not conform to the record management method, the flow advances to step Sg10 to add "2" to the status data STS1. On the other hand, when the read record number is smaller than the number of stored records and is invalid, the above-described step Sg6 is performed.
Is "NO", the process proceeds to step Sg11, and "1" is further added to the status data STS1. When the processing of the CPU 14 shifts to the response transmission processing (step Sa4) of the main routine described above, response data in the format shown in FIG.
Sent to one side. Thus, the read data is received by the card reader / writer 21 side. By the way, the status data STS of this response data
When 1 becomes “3”, the card reader / writer 21
An error is displayed assuming that there is an error in the above-described read command processing.

B. Write Operation In this write operation, a write command in the format shown in FIG. 20A is supplied from the card reader / writer to the IC card. Note that the record number N in this format specifies a record number to be written. When such a write command is supplied,
The write command processing routine shown in FIG.
Proceed to step Sj1. First, in step Sj1, the status data STS1 is set to “0”, and the next step Sj1 is executed.
Proceed to j2. In step Sj2, the directory RT3
Frame F2 is described in a storage format representing record management. And this frame F
If the lower three bits of 2 are “100”, the result of this determination is “YES”, and the flow proceeds to step Sj3. In step Sj3, the head address of the record in the opened file is read from frame F3, and is set in an internal register. Next, step Sj4
Then, it is determined whether or not the record number N assigned to the write command is “0”. Here, when the record number N is not “0”, the determination result is “NO”, and the process proceeds to the next step Sg6. On the other hand, record number N
Is “0”, the result of this determination is “YES”,
Proceed to step Sj5. In step Sj5, the next record number that is one greater than the record number registered in frame F5 is set in the internal register, and the next step Sj6
Proceed to.

In step Sj6, it is determined whether or not the number of stored records read from the frame F4 is equal to or larger than the record number N for writing, that is, whether or not the record number N for writing is an appropriate value. here,
If this record number is a valid value, the determination result is "YES", and the flow advances to the next step Sj7. In step Sj7, the record size registered in the frame F6 is read, and the absolute address at which writing is started is determined from the record size, the record number N, and the start address. That is, a process of multiplying the record size by the next record number (N-1) and adding the result to the head address is performed. Then, in step Sj8, the write data WD assigned to the write command is written sequentially from the absolute address obtained by such processing. Next, in step Sj9, the number of stored records registered in the frame F4 is incremented by one, and this routine ends.

By the way, in the above-mentioned step Sj6, if the record number N to be written is an invalid value,
The result of the determination is "NO", and the routine proceeds to step Sj10.
In step Sj10, a record area is secured in the file based on the record size registered in the frame F6. Next, in step Sj11, when securing this record area, it is determined whether or not the write area is insufficient. Here, if the writing area is sufficient,
The result of this determination is "NO" and the next step Sj12
Proceed to. In step Sj12, the current record number is incremented by 1 as the record number to be written, and the process proceeds to step Sj7. As a result, the new record is written.

On the other hand, if the result of the determination in step Sj2 is "NO", that is, if the file does not conform to the record management method, the flow advances to step Sj13 to add "1" to the status data STS1. When the write area is insufficient when expanding the record area, the result of the determination in step Sj11 is “YE
S ", the flow advances to step Sj14, and" 2 "is further added to the status data STS1. And CP
When the processing of U14 shifts to the response transmission processing (step Sa4) of the main routine described above, FIG.
Is sent from the IC card 11 to the card reader / writer 21 side. By the way, the status data ST of this response data
When S1 becomes “3”, the card reader / writer 21
Displays an error indicating that there is an error in the above-described read command processing.

As described above, in the embodiment described above,
A file corresponding to each address method is provided in the IC card, and a read command and a write command according to each address method can be executed. Therefore, it is possible to correspond to any card reader / writer application. I have.

[0033]

As described above, according to the present invention, the storage means has at least two divided storages.
Attribute information area for identifying the address method is provided for each storage area
Control means for controlling an address corresponding to the attribute information area
Since the input / output control is performed by the method, it is possible to cope with applications having different address methods.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing a configuration of the present invention.

FIG. 2 is a block diagram showing a configuration of one embodiment of the present invention.

FIG. 3 is a view showing a file structure in the embodiment.

FIG. 4 shows directories RT1 to RT3 in the embodiment.
FIG.

FIG. 5 is an exemplary view showing an example of a storage format of a frame F2 in the embodiment.

FIG. 6 is a flowchart showing a main routine in the embodiment.

FIG. 7 is a flowchart showing an open command processing routine in the embodiment.

FIG. 8 is a diagram showing a format of an open command and response data to the command in the embodiment.

FIG. 9 is a flowchart showing a read command processing routine of the physical address method in the embodiment.

FIG. 10 is an exemplary view showing a read command and a format of response data to the command in the physical address method in the embodiment.

FIG. 11 is a flowchart showing a physical address type write command processing routine in the embodiment.

FIG. 12 is a diagram showing a format of a write command and response data to the command in the physical address method in the embodiment.

FIG. 13 is a flowchart showing a read command processing routine of the logical address method in the embodiment.

FIG. 14 is a flowchart showing a write command processing routine of the logical address method in the embodiment.

FIG. 15 is a diagram showing a format of a read command and response data to the command in the logical address method in the embodiment.

FIG. 16 is a view showing a format of a write command and response data to the command in the logical address method in the embodiment.

FIG. 17 is a flowchart showing a read command processing routine of a record management method in the embodiment.

FIG. 18 is a flowchart showing a write command processing routine of a record management method in the embodiment.

FIG. 19 is a diagram showing a format of a read command and response data to the command in the record management system in the embodiment.

FIG. 20 is an exemplary view showing a write command and a format of response data to the command in the record management system in the embodiment.

[Explanation of symbols]

 13 EEPROM (storage means) 14 CPU (control means)

 ──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Yoshikazu Yorimoto 1-5-1, Taito, Taito-ku, Tokyo Inside Toppan Printing Co., Ltd. (56) References JP-A-62-251992 (JP, A)

Claims (1)

(57) [Claims] 1. A storage area divided into at least two or more sections.
Attribute that has an area and identifies the address method for each storage area
An IC card comprising: storage means provided with an information area; and control means for performing input / output control by an address method corresponding to the attribute information area .