JP3098155B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having volatile and nonvolatile storage functions, and to facilitate control of a recall operation and a refresh operation in the nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art Conventionally, nonvolatile semiconductor memory devices (NVD)
RAM [Non-Volatile Dynamic RandomAccess Memory])
There are two types: a memory cell using a ferroelectric material is shared as a volatile and nonvolatile storage element;
M [Dynamic Random Access Memory] and nonvolatile EEP
ROM [Electrically Erasable Programmable Read-Onl
y Memory].

In the case of a nonvolatile semiconductor memory device combining a DRAM and an EEPROM, ordinary access is
The data is stored in the RAM (volatile), and immediately before the power is turned off (or at any time), the data on the DRAM is EEPRO
M (non-volatile). Therefore, normally, high-speed access to the DRAM is possible, and when non-volatile storage is required, this data can be stored in the EEPROM in a short time. Further, the data stored in the EEPROM in this manner can be recalled to the DRAM by a recall operation when the power is turned on (or at any time). Regarding this nonvolatile semiconductor memory device, "A256k-bit Non-
-Volatile PSRAM with Page Recall and Chip Store ",
1991 Sym. VLSI circuit Dig. Tech. Papers, May,
Sections 91-92, and "Development of 256Kbit Non-Volat"
ile DRAM (NV-DRAM) Operating as a Pseudo-SRAM ", Sha
Since the detailed description is given in rpTechnical Journal, No. 49, pp. 45-49, June, 1991, the structure and operation of a nonvolatile semiconductor memory device using a ferroelectric will be described in detail below.

The following literature describes a nonvolatile semiconductor memory device using a ferroelectric substance.

(1). "An Experimental 512-bit Non-No
nvlatile Memory with FerroelectricStorage Cell "IE
EE Journal of Solid State Circuits, vol.23, pp.117
1-1175, October, 1988. (2). "A Ferroelectric DRAM Cell for High-Density
NVRAM's ", IEEE Electron Device Lett., Vol. 11, pp. 4
54-456, October, 1990. The nonvolatile semiconductor memory device using this ferroelectric is Y1
(It is a common name for ferroelectric ceramics developed recently and the components are not disclosed), PZT (PbZrTiO ₃ [leadzirconat
e titanate], perovskite type such as PLZT (PbLaZrTiO ₃ ) or PbTiO ₃
A capacitor element having a ferroelectric thin film having the above crystal structure is used for a memory cell. When an AC voltage is applied to such a capacitor, the polarization state of the ferroelectric exhibits hysteresis characteristics as shown in FIG. That is, when a positive electric field is applied to the ferroelectric substance in the state of the point A which is not polarized first, the polarization state moves to the point B. However, even if this electric field is removed, the polarization state returns only to the point C, and a positive remanent polarization occurs.
When a negative coercive electric field is applied, the remanent polarization disappears. When the negative electric field is further increased, the polarization state is reversed and moves to the point D. However, when the negative electric field is removed, the polarization state changes to the point E. And the negative remanent polarization occurs. Therefore, by inverting the polarization of the ferroelectric to generate positive or negative remanent polarization, data can be stored in a nonvolatile manner. Also, this capacitance element
If only the operation of adding or removing one of the positive and negative electric fields is performed, the polarization state of the ferroelectric moves only between the points B and C or between the points D and E. Like the DRAM, the data can be stored in a volatile manner. However, to retain this volatile stored data,
A refresh operation is required like a DRAM.

A nonvolatile semiconductor memory device using such a ferroelectric material can reduce the number of elements constituting a memory cell as compared with a device combining a DRAM and an EEPROM. There is an advantage that integration is possible. But DRAM and EEP
In the case of a combination of ROMs, these DR
An advantage is that separate data can be stored in the AM and the EEPROM.

The structure of a nonvolatile semiconductor memory device based on the two-transistor / cell system using the ferroelectric material will be specifically described with reference to FIG. This nonvolatile semiconductor memory device has a large number of word lines WL and corresponding plate lines P
T, which are connected to a word line decoder 31 and a plate line decoder 32, respectively. Further, it has a number of bit line pairs, bit bars, and is connected to the sense amplifier 33 for each pair. However, FIG. 8 shows only one set of the bit line pair bit, bit bar and the sense amplifier 33.

Memory cells 34 are arranged at intersections where the word lines WL and the corresponding plate lines PT intersect the bit line pairs bit and bit bar.
However, FIG. 8 shows only one memory cell 34. The memory cell 34 includes two capacitance elements C1 and C2 and two selection transistors Q1 and Q2. One terminal of each of the capacitance elements C1 and C2 has a pair of bit lines bit and bit via selection transistors Q1 and Q2, respectively.
Bar and the other terminal is a plate wire PT
It is connected to the. The gates of the select transistors Q1 and Q2 are connected to a word line WL.

In the nonvolatile semiconductor memory device having the above structure, the word line decoder 31 and the plate line decoder 32 select one word line WL and plate line PT based on the address input to the address buffer 35, and control signals Access to the memory cell 34 is performed in a mode based on the control signal input to the input buffer 36. That is, in the DRAM mode for accessing volatile stored data,
In the recall mode in which the data stored in the nonvolatile memory is read (and rewritten) under the control of the DRAM mode timing control circuit 37, the data is controlled by the recall mode timing control circuit 38 to perform the writing for storing the data in the nonvolatile memory. In the store mode, the access operation is performed under the control of the store mode timing control circuit 39. The data to be accessed is the data I
It is exchanged with the outside via the / O interface 40.

The store mode timing control circuit 39
The data write operation in the store mode will be described in detail with reference to FIGS. For example, when writing data “0”, as shown in FIG.
With a voltage of 0 V applied to the bit line bit and a voltage of 5 V (power supply voltage VCC) to the bit line bit bar, and with the word line WL activated, 0 V → 5 V →
A voltage pulse that changes to 0 V is applied. Then, the ferroelectric substance of one capacitance element C1 changes the polarization state from point C or E in FIG. 7 to point B → C point, and the ferroelectric substance of the other capacitance element C2 changes the polarization state. The point is changed from point D to point E to point D. Therefore, even if the voltage is removed thereafter, remanent polarization occurs at the points C and E in the ferroelectrics of these capacitive elements C1 and C2, thereby storing "0" data in a nonvolatile manner.

When writing "1" data, as shown in FIG. 10, a bit line pair bit, bi
A voltage of 5 V and 0 V opposite to the above is applied to t-bar. Thereafter, when the word line WL is activated and a voltage pulse that changes from 0V to 5V to 0V is applied to the plate line PT in the same procedure, the ferroelectrics of the capacitors C1 and C2 are respectively set to the point E opposite to the above. Residual polarization occurs at the point C, and the data “1” is stored in a nonvolatile manner.

Next, the data read operation in the recall mode in the recall mode timing control circuit 38 will be described in detail with reference to FIG. In this case,
After the bit line pair bit and bit bar are precharged to a potential of 0 V, they are opened. Then, when the word line WL is activated and the voltage of the plate line PT is changed from 0 V to 5 V, for example, when data of “0” is stored, the polarization state of the ferroelectric of one capacitor C 1 is changed. The point C changes from point C to point B, and the polarization state of the ferroelectric of the other capacitive element C2 changes from point E to point B. Then, in the case of the ferroelectric material of the other capacitive element C2, the polarization state is inverted, so that the potential of the bit line bit bar connected thereto becomes higher by several hundred mV than the potential of the bit line bit.
Therefore, if the potential difference between the bit line pair bit and bit bar is sensed by the sense amplifier 33, the data stored in the nonvolatile memory can be read. However, in this case, the polarization states of the ferroelectrics of the capacitors C1 and C2 are both B
Since the data is moved to the point and the data stored in the nonvolatile memory is lost, destructive reading is performed. Then, after this, the voltage of the plate line PT is changed from 0 V to the voltage in the same procedure as in the store mode.
By changing the voltage from 5 V to 0 V, rewriting is performed so that the data once read out is once again nonvolatilely stored.

In this recall mode, bit line pair b
Since the potential difference between the it and the bit bar is proportional to the remanent polarization and inversely proportional to the bit line capacitance, it can be seen that the larger the remanent polarization is and the smaller the bit line capacitance is, the larger the potential difference is, and the detection by the sense amplifier 33 becomes easier.

The DRAM mode timing control circuit 3
7, access in the DRAM mode uses the plate line P
The operation is performed in the same manner as a normal DRAM with 0 V (or 5 V [power supply voltage VCC]) applied to T. Then, the polarization state of the ferroelectric substance in the capacitive elements C1 and C2 moves only between the points D and E (or between the points B and C) in FIG. As in the case of the DRAM, volatile data can be read, written and refreshed by the electric charges stored in the electrodes of the capacitors C1 and C2.

In the above description, a nonvolatile semiconductor memory device using a two-transistor / cell type ferroelectric material which is hardly affected by variations in the ferroelectric film thickness has been described. The same applies to a non-volatile semiconductor memory device having a one-transistor / cell type memory cell array configuration having a small cell area as described above.

[0016]

By the way, both of the above-mentioned conventional nonvolatile semiconductor memory devices can be operated only in the store mode and the recall mode of the nonvolatile memory. However, in the case of a nonvolatile semiconductor memory device combining a DRAM and an EEPROM, an EEPROM
The number of times of rewriting the ROM is limited to about 100,000 times. Also, in the case of a nonvolatile semiconductor memory device using a ferroelectric material, the number of times that the ferroelectric material used for the capacitance elements C1 and C2 of the memory cell 34 can perform polarization inversion is limited, and the recall / store operation is not performed. It is limited to about 10 8 to 10 12. Then, under such restrictions, if continuous access is performed at a cycle period of about 10 MHz, the life of the nonvolatile semiconductor memory device will expire in a few days.

Therefore, such a non-volatile semiconductor memory device operates in a DRAM mode during a normal operation.
Access to the EEPROM only when non-volatile storage is required, such as performing a store operation immediately before the power is turned off and performing a recall operation when the power is turned on. By performing access involving polarization reversal of a ferroelectric substance or the like, the number of rewrites of the EEPROM or the number of polarization reversals of the ferroelectric substance is reduced as much as possible.

However, in the conventional nonvolatile semiconductor memory device, the recall operation and the refresh operation are performed by a combination of a plurality of external input signals. That is, conventionally, for example, the nonvolatile storage enable signal NE bar, the chip enable signal CE bar, and the output enable signal OE bar are made active (L level), and the write enable WE bar and the refresh signal RFSH bar are made inactive (H level). , The recall operation is performed, and only the chip enable signal CE is activated to supply an address from the outside, thereby performing the volatile memory refresh operation. However, by setting only the refresh signal RFSH bar to active (L level), the pseudo SRAM [Static
When self-refreshing is performed by an internal counter as in [RAM], volatile storage can be automatically refreshed without frequently changing an external input signal. However, even in the case of performing such a self-refresh, an operation of recalling the data stored in a non-volatile manner once by a recall operation and storing the data in a volatile manner is required.

For this reason, in the conventional nonvolatile semiconductor memory device, it is necessary to perform a recall operation once before shifting to the access in the DRAM mode. For this purpose, a combination of external input signals must be controlled. S
There has been a problem that control is troublesome as compared with other memory devices such as a RAM.

This problem occurs when the nonvolatile semiconductor memory device is configured as a single memory device,
This is common to all cases such as the case where it is configured as a memory module of a chip microcomputer.

The present invention solves the above-mentioned conventional problem. A nonvolatile memory which makes the control easy by automatically instructing the self-refresh of the volatile memory and automatically performing the recall operation when necessary. It is an object to provide a semiconductor memory device.

[0022]

A nonvolatile semiconductor memory device according to the present invention has a volatile storage function that requires a refresh operation to maintain storage contents and a nonvolatile storage function that allows rewriting of storage contents. Signal input means for inputting a refresh signal, and at least power-on
A recall request signal generating means for generating a recall request signal at the time of and when the store operation is completed; an address generating means for automatically generating an address of each memory cell sequentially based on a clock signal; and a refresh signal input to the refresh signal input means. And when the recall request signal generating means is generating a recall request signal, the storage contents of each of the memory cells stored in a nonvolatile manner based on the address generated by the address generating means are sequentially stored in the same memory cell. Recall means for performing a recall operation for volatile storage;
When the recall means performs a predetermined number of recall operations on each memory cell, a refresh signal is input to the recall operation control means for canceling the generation of the recall request signal by the recall request signal generation means and a refresh signal input means. And, when the recall request signal generating means does not generate a recall request signal, refreshing is performed by sequentially rewriting the stored contents volatilely stored in each memory cell based on the address generated by the address generating means. Refresh means for performing an operation , the clock signal having a shorter cycle during the recall operation.
Clock signal is supplied during refresh operation.
The clock signal with the longer period is supplied , thereby achieving the above object.

Preferably, the memory cell in the nonvolatile semiconductor memory device of the present invention is constituted by a capacitive element with a ferroelectric material interposed therebetween, thereby achieving the above object.

Further, the nonvolatile semiconductor memory device of the present invention has a nonvolatile memory cell having a volatile memory cell requiring a refresh operation to maintain the stored content and a nonvolatile memory cell capable of rewriting the stored content. In a semiconductor memory device, refresh signal input means for inputting a refresh signal, recall request signal generating means for generating a recall request signal, address generation means for automatically generating addresses of respective memory cells sequentially based on a clock signal, A refresh signal is input to the signal input means,
And a recall operation for sequentially calling each storage content of the non-volatile memory cell to the volatile memory cell based on the address generated by the address generation means when the recall request signal generation means generates the recall request signal. A recall operation control means for canceling the generation of the recall request signal by the recall request signal generation means when the recall means executes a predetermined number of recall operations for each memory cell; and a refresh signal input means. When a refresh signal is input and the recall request signal generating means has not generated a recall request signal,
Refresh means for performing a refresh operation by sequentially rewriting the stored contents of the volatile memory cells based on the address generated by the address generating means, thereby achieving the object described above.

Still preferably, in a nonvolatile semiconductor memory device according to the present invention, a volatile memory cell which requires a refresh operation to maintain stored contents is constituted by a DRAM, and a nonvolatile memory capable of rewriting stored contents. In this case, the memory cell is configured by an EEPROM, thereby achieving the above object.

Further, preferably, in the nonvolatile semiconductor memory device of the present invention, after the RAS bar signal becomes active after the CAS bar signal becomes active,
A refresh signal generating means for generating a refresh signal for a period from when the AS bar signal returns to inactive to when the RAS bar signal becomes inactive is provided, thereby achieving the above object.

Still preferably, in a nonvolatile semiconductor memory device according to the present invention, the clock signal supply means for supplying two kinds of clock signals having different periods for automatically generating an address, and the recall means performs a recall operation. Clock signal switching means for supplying a clock signal having a shorter cycle from the clock signal supply means, and supplying a clock signal having a longer cycle from the clock signal supply means when the refresh means performs a refresh operation. Therefore, the above object is achieved.

Preferably, the refresh means in the nonvolatile semiconductor memory device of the present invention refreshes by sequentially rewriting the storage contents volatilely stored in each memory cell based on the address generated by the address generation means. In addition to performing the operation, when refreshing each memory cell, a store operation is performed to store the volatile stored data in the same memory cell in a nonvolatile manner, thereby achieving the above object.

Still preferably, in a nonvolatile semiconductor memory device according to the present invention, the refresh unit sequentially rewrites the storage contents stored in each of the volatile memory cells based on the address generated by the address generation unit. A refresh operation is performed, and a store operation for storing the stored contents in the volatile memory cells in the nonvolatile memory cells at the time of refreshing each memory cell is performed, thereby achieving the above object. Is done.

[0030]

With the above arrangement, the refresh signal input means inputs a refresh signal from an external terminal of an LSI (Large Scale Integrated circuit), a pad on a chip, or another circuit on the same chip. The present invention is intended to control the recall operation and the refresh operation of the nonvolatile semiconductor memory device only by controlling the refresh signal.

The recall request signal generating means generates a recall request signal when volatile storage contents are not maintained by the refresh operation, for example, when the power is turned on or after the store operation is completed. Then, the generation of the recall request signal is canceled after the recall operation is completed by the recall operation control means described later. The address generation means automatically generates an address of each memory cell sequentially based on a clock signal input from the outside or a clock signal generated internally. Then, the recall means and the refresh means perform a recall operation and a refresh operation of each memory cell based on the address.

When the power is turned on or when the store operation is completed,
Since a recall request signal is generated, when a refresh signal is first input thereafter, the recall means performs a recall operation to call out nonvolatile storage contents and store them in volatile storage. When the recall operation is completed, the recall operation control means cancels the generation of the recall request signal as described above, and thereafter, the refresh means performs a refresh operation to maintain volatile storage contents. Further, if the input of the refresh signal is temporarily stopped for access to the nonvolatile semiconductor memory device and then restarted, the refresh operation by the refresh means continues since the recall request signal remains stopped in this case. Is done.

Therefore, a device or a circuit that accesses the nonvolatile semiconductor memory device only controls the refresh signal, and automatically recalls the nonvolatile storage content if the nonvolatile storage content has not been called as volatile yet. After the operation is performed, the refresh operation of the volatile storage content can be performed, so that the nonvolatile semiconductor memory device whose control is complicated can be easily used in such a manner as to handle a pseudo SRAM, for example.

The first aspect of the present invention is directed to a case where a memory cell of a nonvolatile semiconductor memory device shares a volatile storage function and a non-volatile storage function. A case where a cell is constituted by a capacitive element with a ferroelectric material interposed is shown.

According to a third aspect of the present invention, there is provided a case where the nonvolatile semiconductor memory device has a volatile memory cell and a nonvolatile memory cell separately.
The case where these memory cells are constituted by a DRAM and an EEPROM will be described.

According to the nonvolatile semiconductor memory device of the present invention, a refresh signal can be handled in the same manner as a pseudo SRAM by controlling the refresh signal. When the generating means is provided, CAS [Column Address Stro
be] Before RAS [Raw Address Strobe] Refresh type DRAM can be handled in the same manner.

The recall operation by the recall means should be performed as quickly as possible. In the refresh operation by the refresh means, the power consumption decreases as the cycle becomes longer. Therefore, the refresh operation should be performed in a cycle as long as possible within a prescribed refresh cycle. Therefore, in the invention of claim 6, when the clock signal switching means switches the clock signal from the clock signal supply means and the recall means performs the recall operation, the clock signal having the shorter cycle is supplied to the address generation means. Along with
When the refresh means performs the refresh operation, the above request is realized by supplying a clock signal having a longer cycle to the address generation means and changing the address generation speed.

The invention of claims 7 and 8 shows a case where the refresh means performs a refresh operation of volatile storage contents and also refreshes nonvolatile storage contents by a store operation.

If the recall operation by the recall means is to destructively read out the non-volatile storage contents, the read-out storage contents are stored as non-volatile again if necessary.

[0040]

Embodiments of the present invention will be described below.

FIGS. 1 to 5 show one embodiment of the present invention. FIG. 1 is a block diagram showing a configuration of a control section of a nonvolatile semiconductor memory device, and FIG. 2 shows a specific configuration of an address counter. FIG. 3 is a partial circuit block diagram showing a specific configuration of the address selection circuit, FIG. 4 is a circuit block diagram showing a specific configuration of the second control signal generation circuit, and FIG. 5 is an operation of the nonvolatile semiconductor memory device. FIG.

In this embodiment, a nonvolatile semiconductor memory device using a ferroelectric will be described. The nonvolatile semiconductor memory device may be configured as a single memory device or as a memory module of a one-chip microcomputer.

The memory section 1 of this nonvolatile semiconductor memory device shown in FIG. 1 comprises a memory cell array, a sense amplifier, a data I / O interface and the like. It is assumed that the memory cell array includes, for example, a large number of the two-transistor / cell type memory cells 34 shown in FIG. However, this memory cell array may be based on the one-transistor / cell system or the like. Also, if the memory unit 1
The present invention can be similarly implemented in a nonvolatile semiconductor memory device or the like combining an AM and an EEPROM.

External addresses AEX0 to AEX0 input from outside
AEXn is sent to the driver / decoder circuit 4 via the external address transition detection circuit 2 and the address selection circuit 3. This nonvolatile semiconductor memory device has an address counter 5. As shown in FIG. 2, the address counter 5 is composed of n D-type flip-flops 5a. The address counter 5 sends a clock signal input from the outside to the clock input CK of the first-stage D-type flip-flop 5a. The output Q of the type flip-flop 5a is sequentially sent to the clock input CK of the next stage. The reset signal input from the outside corresponds to the reset input R of the D-type flip-flop 5a of each stage.
It is sent to the ESET bar (L active). Although not shown, the inverted output Q of the D-type flip-flop 5a at each stage is connected to the data input D of the same D-type flip-flop 5a. Therefore, when a clock signal is input from the outside, the address counter 5 sequentially divides the frequency of the clock signal by two by the D-type flip-flops 5a at each stage. Therefore, this address signal and the output Q of each D-type flip-flop 5a Internal addresses A0 to An in which binary values are sequentially incremented can be generated. As shown in FIG. 1, an initialization signal PON which temporarily goes high when the power is turned on is input to the address counter 5 via the inverter circuit 9 as a reset signal (L active). ,
As a result, the internal addresses A0 to An are reset to the initial value (all bits are at L level). The internal addresses A0 to An output from the address counter 5 are input to the address selection circuit 3 via the internal address transition detection circuit 6.

The external address transition detection circuit 2 sends the external addresses AEX0 to AEXn to the address selection circuit 3 when the external address activation signal φEXA is active,
This circuit detects the change of the external addresses AEX0 to AEXn and sends an address transition signal to the word line control circuit 7 and the plate line control circuit 8 to that effect. Further, the internal address transition detection circuit 6 outputs the internal address activation signal φIN
When A is active, the internal addresses A0 to An are sent to the address selection circuit 3 and the internal addresses A0 to An
This is a circuit which detects that An has changed and sends an address transition signal to the word line control circuit 7 and the plate line control circuit 8 to that effect. When receiving the address transition signal from the external address transition detection circuit 2 or the internal address transition detection circuit 6, the word line control circuit 7 receives the driver / decoder circuit 4.
When the address line transition signal is received, the plate line control circuit 8 controls the driver / decoder circuit 4 to change the plate line PT of the memory unit 1. It is a circuit to be driven.

FIG. 3 shows a specific configuration of an input / output circuit for one bit of an address in the address selection circuit 3.
The one-bit external address AEXi is input to the buffer circuit 3b via the external address selection circuit 3a, and the one-bit internal address Ai is input to the same buffer circuit 3b via the internal address selection circuit 3c. When the external address activation signal φEXA is active (H level), the external address selection circuit 3a turns on the P-channel and N-channel FETs and sends the external address AEXi to the buffer circuit 3b. Also, the internal address selection circuit 3c
When the internal address activation signal φINA is active, the P-channel and N-channel FETs are turned on, and the internal address Ai is sent to the buffer circuit 3b. Therefore, the address selection circuit 3 supplies the external address activation signal φ
When either EXA or the internal address activation signal φINA is active, one of the external addresses AEX0 to AEXn and the internal addresses A0 to An is sent to the driver / decoder circuit 4 as a selected address.

The driver / decoder circuit 4 shown in FIG.
A circuit that decodes the selected address sent from the address selection circuit 3, selects the corresponding word line WL and plate line PT in the memory unit 1, and drives according to the control of the word line control circuit 7 and the plate line control circuit 8. It is.

Here, the internal address activating signal φIN
A is a signal generated by the first control signal generating circuit 10 which receives an external refresh signal RFSH bar. The first control signal generating circuit 10 activates the internal address activation signal φINA when the refresh signal RFSH goes active (L level). The control signal generating circuit 10 also controls the internal refresh signal RSH obtained by inverting the refresh signal RFSH bar.
An EF is also generated. The refresh signal RFSH bar is input from an external terminal when the nonvolatile semiconductor memory device is configured as a single memory device, and is applied to a pad on the chip when configured as a memory module such as a one-chip microcomputer. Can be entered from The external address activation signal φEXA is a signal that becomes active when externally accessed, and is generated by a control circuit (not shown) based on a chip enable signal CE or the like input from the outside.

According to the above configuration, when external address activating signal φEXA becomes active, external address AEX0
AEXn are sent to the driver / decoder circuit 4 via the external address transition detection circuit 2 and the address selection circuit 3,
The memory cells in the memory unit 1 corresponding to the external addresses AEX0 to AEXn are accessed. At this time, based on the address transition signal generated by the external address transition detection circuit 2, the word line control circuit 7 and the plate line control circuit 8 connect the word line WL of the memory unit 1 with a mode corresponding to a control signal (not shown). The plate line PT is driven. When the internal address activation signal φINA is activated, the internal addresses A0 to An are supplied to the driver / decoder circuit 4 via the internal address transition detection circuit 6 and the address selection circuit 3.
And the memory cells in the memory unit 1 corresponding to the internal addresses A0 to An are accessed. At this time, based on the address transition signal generated by the internal address transition detection circuit 6, the word line control circuit 7 and the plate line control circuit 8 connect the word line WL of the memory unit 1 with a mode corresponding to a control signal (not shown). The plate line PT is driven. Therefore, in the case of normal access from the outside, the external address activation signal φEXA becomes active, and the memory cells of the memory unit 1 are operated in various modes based on the external addresses AEX0 to AEXn sent from the outside. Access is made. When the refresh signal RFSH bar becomes active, the internal address activation signal φINA becomes active, and various kinds of memory cells of the memory unit 1 are controlled based on the internal addresses A0 to An sequentially generated by the address counter 5. Mode access is performed.

The internal address A of the most significant bit among the internal addresses A0 to An generated by the address counter 5
n is input to the recall counter 11. The recall counter 11 is a counter that counts the falling of the internal address An and changes the output from the L level to the H level when the predetermined number of counts is completed. Therefore, the recall counter 11 counts once each time the internal addresses A0 to An make one cycle and all the addresses are output once. When the internal addresses A0 to An make a predetermined number of rounds, the output becomes H. Change to level. The predetermined number of times may be only one.

The output of the recall counter 11 is sent to the latch circuit 13 and the reset terminal (L active) of the recall request latch circuit 14 via the inverter circuit 12. Latch circuit 13 and recall request latch circuit 14
Is actually configured by an RS flip-flop circuit, which is set and outputs an H level when a set terminal (H active) goes to an H level, and is reset and outputs an L level when a reset terminal goes to an L level. Therefore,
When the output of the recall counter 11 becomes H level,
Outputs of the latch circuit 13 and the recall request latch circuit 14 are reset to L level. The recall request latch circuit 14 is configured to input a store completion signal generated by a control circuit (not shown) when the store operation is completed and the initialization signal PON to a set terminal via an OR circuit 15. Therefore, the store completion signal and the initialization signal P
When any of the ONs goes to H level, the recall request latch circuit 14 is set and the output goes to H level.

The output of the recall request latch circuit 14 is sent to an output buffer 16. Output buffer 16
Outputs an L-level recall request signal RC bar when the output of the recall request latch circuit 14 is at an H level, and outputs an H level when the output of the recall request latch circuit 14 is at an L level. A refresh request signal RF is output.
The recall request signal RC and the refresh request signal RF are actually the same signal. When the signal is at the L level, it becomes the recall request signal RC, and when it is at the H level, it becomes the refresh request signal RF. Since this recall request signal RC / refresh request signal RF is also output to the outside of the nonvolatile semiconductor memory device, an external device or the like can easily know the state of the nonvolatile semiconductor memory device of the present invention. Will be able to do it. If the output of the output buffer 16 is configured to have an open drain configuration, almost no current can be consumed unless an external device or the like accesses it.

The output buffer 16 is merely a buffer circuit for outputting a substantial recall request signal output from the recall request latch circuit 14 to the outside. Since the latch circuit 13 latches this substantial recall request signal in conjunction with the recall request latch circuit 14, the latch circuit 13 can be omitted integrally with the recall request latch circuit 14.

The output of the recall request latch circuit 14 is also sent to the set terminal of the latch circuit 13. Therefore, when the output of the recall request latch circuit 14 goes high, the output of the latch circuit 13 is set high. The output of the latch circuit 13 is sent to the plate line control circuit 8 via the AND circuit 17.
The power supply voltage VCC is input to the other input of the AND circuit 17. Therefore, the output of the recall request latch circuit 14 is sent to the plate line control circuit 8 as it is. The plate line control circuit 8 includes a latch circuit 13
Becomes an H level, an enable state is established. In this case, the voltage of the plate line PT is changed from 0 V to 5 V to perform a recall operation of reading data from the nonvolatile memory. Since the recall operation of the nonvolatile memory is a destructive read operation, the voltage of the plate line PT is changed again from 0 V to 5 V to 0 V after the sense amplifier operation to rewrite the nonvolatile memory. . When the output of the latch circuit 13 becomes L level, the enable state is released, and the plate line PT is fixed at 0 V, for example, to access volatile storage. Therefore, when the initialization signal PON or the store completion signal temporarily becomes H level when the power is turned on or when the store operation is completed, the recall request latch circuit 14
And the latch circuit 13 are set, and the plate line control circuit 8
Can perform a recall operation on the memory cells of the memory unit 1, and when the recall counter 11 finishes counting and the recall request latch circuit 14 and the latch circuit 13 are reset, the plate line control circuit 8 can access the memory cells of the memory unit 1 for volatile storage.

The recall request signal RC / refresh request signal RF output from the output buffer 16 is ORed directly and via the inverter circuit 18 and the delay circuit 19.
The output of the OR circuit 20 is sent to a reset terminal (L active) of the recall counter 11. Therefore, this recall counter 1
When the output of the output buffer 16 changes from the refresh request signal RF (H level) to the recall request signal RC bar (L level), the internal count number is reset until the delay time of the delay circuit 19 elapses. Output is L
Returned to level.

The recall request signal RC / refresh request signal RF output from the output buffer 16
Is also sent to the second control signal generation circuit 21. The refresh signal RFSH is supplied to the second control signal generation circuit 21.
The bar and the initialization signal PON are also input. As shown in FIG. 4, the second control signal generation circuit 21 has a D-type flip-flop (latch circuit) composed of a flip-flop circuit 21a and a gate circuit 21b. That is, the flip-flop circuit 21a is composed of two inverter circuits, and the initialization signal PON is temporarily set to H when the power is turned on.
When the level reaches the level, the N-channel FET 21c turns ON, and the output is initialized to the H level. Gate circuit 21b
When the refresh signal RFSH is active (L level), the P-channel and N-channel FETs are turned on, and the recall request signal RC / refresh request signal RF is input to the flip-flop circuit 21a. Therefore, the refresh signal RFSH
When the bar is activated, the flip-flop circuit 21
a outputs a signal obtained by inverting the recall request signal RC / refresh request signal RF and outputs the refresh signal RF
When the SH bar returns to the inactive state, the output of the signal obtained by inverting the immediately preceding recall request signal RC / refresh request signal RF is maintained thereafter. The output of the flip-flop circuit 21a is output from the second control signal generation circuit 21 as it is as a self-recall signal SR, and is inverted by an inverter circuit 21d and output as a self-store signal SS. Therefore, the self-recall signal SR is initialized to H level when the power is turned on, and is switched to L level only when the refresh signal RFSH is active (L level) and the refresh request signal RF (H level) is output. The self recall signal SR is a signal obtained by inverting the self store signal SS.

The internal refresh signal REF output from the first control signal generation circuit 10 is sent to the timer circuit 23. The timer circuit 23 has an internal refresh signal REF
Oscillates only when is at the H level, and outputs a first clock signal T1 having a long cycle (eg, a 16 μsec cycle) and a second clock signal T2 having a short cycle (eg, a 500 nsec cycle).

The clock signal T generated by the timer circuit 23
1 and T2 are sent to the address counter 5 via the selection circuit 24. The selection circuit 24 outputs the clock signals T1, T2
Is a multiplexer that selects one of them and supplies it to the address counter 5. The output of the latch circuit 13 is connected to a control input. When the output of the latch circuit 13 is at L level, the clock signal T1 having a long cycle is used.
Is transmitted, and when it becomes H level, a clock signal T2 having a short cycle is transmitted.

The specific operation of the control section of the nonvolatile semiconductor memory device having the above configuration will be described with reference to the time chart of FIG.

As described with reference to FIG. 1, when the power is turned on, the initialization signal PON temporarily goes to the H level, so that the internal addresses A0 to An generated by the address counter 5 are reset to the initial values and the recall request is issued. Latch circuit 1
4 is set to output an L level recall request signal RC through the output buffer 16, and the latch circuit 13 is also set. When the recall request signal RC is output, the recall counter 11 is reset before the delay time of the delay circuit 19 elapses. Power ON
Immediately after the refresh signal RFSH bar is inactive, the internal refresh signal REF generated by the control signal generation circuit 10 also becomes inactive (L level), and the timer circuit 23 does not generate the clock signals T1 and T2. Note that the self-recall signal SR output from the second control signal generation circuit 21 becomes H level by initialization.

Here, assuming that refresh signal RFSH goes active (L level) at time t0 shown in FIG. 5, internal refresh signal REF goes active (H level) and internal address activating signal φ.
INA also becomes active (H level).

As described above, the internal refresh signal REF
Becomes active (H level), the timer circuit 23 starts generating the long-period clock signal T1 and the short-period clock signal T2. In FIG. 5, the cycle of the clock signal T2 is unclear, but actually, in the case of the above example (16 μsec cycle and 500 nsec cycle), the clock signal T1
Becomes 1/32 of the period. Here, since the latch circuit 13 outputs the H level, the selection circuit 24 supplies the clock signal T2 having the shorter cycle to the address counter 5.
Accordingly, the internal address A0 of the least significant bit among the internal addresses A0 to An generated by the address counter 5
Changes at the same cycle as the clock signal T2. And
The internal addresses A0 to An are sent to the driver / decoder circuit 4 via the internal address transition detection circuit 6 and the address selection circuit 3. At this time, the address transition of the internal addresses A0 to An due to the change of the clock signal T2 is detected by the internal address transition detection circuit 6, and the word line control circuit 7 and the plate line control circuit 8 are driven. Since the circuit 8 is enabled by the output of the H level of the latch circuit 13, the clock signal T
The recall operation is sequentially performed on each memory cell of the memory unit 1 in the cycle of 2. Hereinafter, this recall operation is referred to as a self-recall operation.

The internal address An of the most significant bit of the internal addresses A0 to An is obtained by dividing the internal address A0 of the least significant bit n times by 2 and changes at a cycle much longer than the cycle of the clock signal T2. I do. Here,
Internal address A for convenience in showing the time scale equally
The period of n is shown shorter than the actual one. Since the internal address An goes through the internal address A0 to An each time the pulse falls, a series of self-recall operations are performed for all the memory cells. Then, the recall counter 11 counts the number of times of the series of self-recall operations by counting each time the internal address An falls.

When the recall counter 11 finishes counting a predetermined number of times at time t2 as described above, the latch circuit 13 and the recall request latch circuit 14 are reset, and
The recall request signal RC changes to the H level refresh request signal RF. Then, the selection circuit 24 supplies the clock signal T1 having a long cycle to the address counter 5 instead of the clock signal T2, and the internal address A0 of the least significant bit starts to change at the same cycle as the clock signal T1. Also, since the plate line control circuit 8 is also released from the enable state, the self-recall operation is stopped and the operation shifts to the volatile memory refresh operation. Since the refresh operation here is the same as the auto refresh and the self refresh in the pseudo SRAM,
Hereinafter, this operation is referred to as a self-refresh operation. The second
Self-recall signal S output from control signal generation circuit 21
R changes to L level, and self-store signal SS changes to H level.

When refresh signal RFSH is returned to inactive at time t3 after the start of the self-refresh operation, internal refresh signal REF also becomes inactive, timer circuit 23 stops oscillating, and the self-refresh operation is stopped. You. Since the internal address activation signal φINA becomes inactive, the external address activation signal φEXA is activated by activating the chip enable signal CE bar, the output enable signal OE bar, the write enable WE bar, etc. The external address transition detection circuit 2 operates. The address selection circuit 3 also selects the address output from the external address transition detection circuit 2 and sends it to the driver / decoder circuit 4. Therefore, during this period, it is possible to access the data stored in the volatile storage from the outside. At the time t2, the output of the output buffer 16 changes from the recall request signal RC to the refresh request signal RF in order to know from the outside that the self-recall operation has been completed and the volatile memory can be accessed. What is necessary is just to detect that.

When the refresh signal RFSH is activated again at time t4 after the external access is completed, the internal refresh signal REF is also activated, the timer circuit 23 resumes oscillation, and the internal address activation signal φINA is activated. Return. At this time, the latch circuit 13 and the recall request latch circuit 14 are reset to output the L level, and the output of the output buffer 16 remains the refresh request signal RF. Therefore, the self refresh operation is immediately performed without performing the self recall operation. Will be resumed.

If the refresh signal RFSH returns to inactive during the self-recall operation between the time t0 and the time t2 (for example, at the time t1), the timer circuit 23 stops oscillation and the self-recall operation is stopped. Operation is suspended. However, since the latch circuit 13 and the recall request latch circuit 14 have not yet been reset and output the H level and the output of the output buffer 16 maintains the recall request signal RC bar, when the refresh signal RFSH bar becomes active thereafter, Then, the self-recall operation is restarted, and the recall counter 11 also continues counting from the previous time. In addition, the conventional pseudo SRAM
In this embodiment, a refresh operation synchronized with a refresh signal is called an auto-refresh operation, and a refresh operation not synchronized with the refresh signal is called a self-refresh operation. Is called self-recall. However, the self-recall operation here includes both the auto-recall operation and the self-recall operation.

As a result, according to the nonvolatile semiconductor memory device of the present embodiment, the recall request signal RC bar is issued when the power is turned on or when the store is completed. The self-recall operation is automatically performed, the data stored in the non-volatile memory is recalled, and volatile storage is performed. Therefore, devices and circuits that access this nonvolatile semiconductor memory device only control the refresh signal RFSH bar,
The data stored in the nonvolatile storage can be called into the volatile storage and refreshed, and access control to the data in the volatile storage can be easily performed. In the self-recall operation, the internal addresses A0 to An are generated at high speed based on the short-period clock signal T2 so that the recall operation can be completed quickly. Based on this, the internal addresses A0 to An can be generated at a low speed, and waste of power consumption due to excessive refresh operation can be eliminated. However, depending on circumstances, the clock signal T1 may have the same cycle as the clock signal T2 or a cycle shorter than this.

Japanese Patent Application No. 5-262648 discloses that when a self-refresh operation by an internal counter continues for a predetermined time or more, a self-store operation is executed and data is saved as a non-volatile memory so that access is not performed for a long time. An invention that suppresses power consumption by a data self-refresh operation is described. Also, in the present embodiment, when the self-recall operation shifts to the self-refresh operation, the present invention can be implemented by counting the elapse of a predetermined time by a counter or the like (not shown) and automatically executing the self-store operation. It is possible. The self-recall signal SR and the self-store signal SS output from the second control signal generation circuit 21 are used to control such a self-recall operation and a self-store operation. That is, when the self-recall signal SR is active, the plate line control circuit 8 in the enabled state is set.
Drive the recall operation, and the self-store signal SS
Is active, the plate line control circuit 8 in the enabled state may be controlled to drive the store operation. Further, since many circuits for the self-store operation can be shared with the circuit for the self-recall operation of the present embodiment, they can also be used for controlling these shared circuits.

In the nonvolatile semiconductor memory device according to the present embodiment to which the self-store operation is added, when the refresh signal RFSH bar becomes active after the power is turned on, the self-recall signal SR becomes active first, so that the self-recall operation is executed. Thereafter, the self-refresh operation is performed, and then the self-store signal SS becomes active. Therefore, if the self-refresh operation is continued for a predetermined time or more, the self-store operation is performed. After the self-store operation is performed, the standby state with low power consumption can be set thereafter.

However, the second control signal generating circuit 21 is not constituted by the above-mentioned D-type flip-flop, and the recall request signal RC / refresh request signal RF is latched only at the falling timing of the refresh signal RFSH. According to this configuration, when the refresh signal RFSH bar is first activated, the self-recall signal SR is continuously activated, so that only the transition from the self-recall operation to the self-refresh operation is performed. However, if the refresh signal RFSH bar becomes inactive after returning to inactive once, the self-store signal SS becomes active this time, so that the self-store operation is executed when the restarted self-refresh operation continues for a predetermined time or more. Will be done.

The data I / O interface of the memory unit 1 is constituted by a three-status buffer.
By controlling to be in a high impedance state during a self-recall operation or a self-refresh operation, data I / O terminals of a large number of nonvolatile semiconductor memory devices can be directly connected.

FIG. 6 shows another embodiment of the present invention, and is a block diagram showing a configuration of a control section of a nonvolatile semiconductor memory device. Note that components having the same functions as those of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In the first embodiment shown in FIG. 1, the output of the latch circuit 13 is sent to the plate line control circuit 8 via the AND circuit 17, but the nonvolatile semiconductor memory device of this embodiment is
The internal refresh signal REF is sent directly to the plate line control circuit 8. When the internal refresh signal REF is active, the plate line control circuit 8 is always turned on.
Is enabled. The plate line control circuit 8
Changes the mode by the self-recall signal SR and the self-store signal SS output from the second control signal generation circuit 21. When the self-recall signal SR is active, the self-recall operation is driven.
When S is active, the self-refresh operation of the volatile memory is performed, and the plate line P
The self-store operation is also performed by changing the voltage of T from 0V → 5V → 0V.

With the above configuration, the refresh signal RFS
When H bar becomes active, a self-recall operation is first performed, and then a self-refresh operation of volatile storage is performed. In this self-refresh operation, a self-store operation of nonvolatile storage is also performed at the same time.
Therefore, in the case of the present embodiment, there is an advantage that the refresh of the volatile storage and the refresh of the nonvolatile storage can be performed simultaneously. However, when the nonvolatile memory is refreshed in this manner, there is a problem in that the number of times of polarization inversion of the ferroelectric material is limited. However, if the number of times of polarization reversal is 10 10 times or more, operation for 10 years or more can be guaranteed by setting a refresh cycle so that each memory cell is selected at a cycle of about 10 ms or more. . For example, if the number of word lines WL is 1000 and the cycle of the clock signal T1 is set to 16 μs, the refresh cycle of each memory cell is 16 ms, which can satisfy this condition.

In the above embodiment, the case where the control similar to the pseudo SRAM is performed using the refresh signal RFSH for the control of the self-refresh operation has been described. It is also possible to control the self-refresh operation by a combination of a plurality of control signals such as a bar signal. In this case, since the addresses are multiplexed and input, the size of the package can be reduced and the mounting density can be increased.

Further, the nonvolatile semiconductor memory device of the above embodiment has an R
Since the RAM and the PROM can be used in common instead of the AM and the PROM, a decoder circuit and a sense amplifier circuit required for each of the RAM and the PROM can be shared.
The chip area and the circuit area on the substrate can be reduced.

[0078]

As described above, according to the nonvolatile semiconductor memory device of the present invention, the nonvolatile storage contents can be automatically called out to the volatile storage and refreshed only by controlling the refresh signal. Access control to volatile storage contents can be easily performed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a control unit of a nonvolatile semiconductor memory device according to one embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of an address counter in the nonvolatile semiconductor memory device according to one embodiment of the present invention.

FIG. 3 is a partial circuit block diagram showing a specific configuration of an address selection circuit in the nonvolatile semiconductor memory device according to one embodiment of the present invention.

FIG. 4 is a circuit block diagram showing a specific configuration of a second control signal generation circuit in the nonvolatile semiconductor memory device according to one embodiment of the present invention.

FIG. 5 is a time chart showing an operation of the nonvolatile semiconductor memory device according to one embodiment of the present invention.

FIG. 6 is a block diagram showing a specific configuration of an address counter in a nonvolatile semiconductor memory device according to another embodiment of the present invention.

FIG. 7 is a diagram illustrating hysteresis characteristics of a ferroelectric substance.

FIG. 8 is a block diagram illustrating a configuration of a nonvolatile semiconductor memory device using a ferroelectric substance.

FIG. 9 is a diagram illustrating an operation when data “0” is written to a memory cell using a ferroelectric substance in a store mode.

FIG. 10 is a diagram illustrating an operation when data “1” is written in a memory cell using a ferroelectric substance in a store mode.

FIG. 11 is a diagram illustrating an operation when data is read from a memory cell using a ferroelectric substance in a recall mode.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory part 5 Address counter 8 Plate line control circuit 10 1st control signal generation circuit 11 Recall counter 13 Latch circuit 14 Recall request latch circuit

Claims (8)

(57) [Claims] 1. A nonvolatile semiconductor memory device comprising a memory cell having a volatile storage function requiring a refresh operation to maintain storage contents and a nonvolatile storage function capable of rewriting storage contents. Refresh signal input means for inputting a signal; recall request signal generating means for generating a recall request signal at least at power-on and when a store operation is completed; and address generation for sequentially and automatically generating addresses of respective memory cells based on a clock signal. Means, when a refresh signal is input to the refresh signal input means, and the recall request signal generating means is generating a recall request signal, the memory is nonvolatilely stored based on the address generated by the address generating means. The stored contents of each memory cell are sequentially stored in the same memory cell in a volatile manner. Recall means for performing a recall operation that performs a predetermined number of recall operations on each memory cell; recall operation control means for canceling generation of a recall request signal by the recall request signal generation means; When a refresh signal is input to the refresh signal input means and the recall request signal generating means has not generated a recall request signal, the refresh signal is volatile-stored in each memory cell based on the address generated by the address generating means. Refresh means for performing a refresh operation by sequentially rewriting the stored contents , wherein the clock signal has a short cycle during the recall operation.
Clock signal is supplied and the refresh operation is performed.
Sometimes a clock signal with a longer cycle is supplied.
Non-volatile semiconductor memory device. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said memory cell is constituted by a capacitance element with a ferroelectric material interposed. 3. A refresh signal is input to a nonvolatile semiconductor memory device including a volatile memory cell requiring a refresh operation to maintain stored contents and a nonvolatile memory cell capable of rewriting stored contents. Refresh signal input means; recall request signal generating means for generating a recall request signal; address generating means for automatically generating addresses of respective memory cells sequentially based on a clock signal; and a refresh signal input to the refresh signal input means. And, when the recall request signal generating means generates a recall request signal, each storage content of the nonvolatile memory cell is sequentially called to the volatile memory cell based on the address generated by the address generating means. Recall means for performing a recall operation; and the recall means is provided for each memory cell. When a predetermined number of recall operations are performed, recall operation control means for canceling generation of a recall request signal by the recall request signal generation means, a refresh signal is input to the refresh signal input means, and the recall request signal Refresh means for performing a refresh operation by sequentially rewriting the storage contents of volatile memory cells based on the address generated by the address generation means when the generation means does not generate a recall request signal. Nonvolatile semiconductor memory device. 4. A volatile memory cell requiring a refresh operation to maintain the storage contents is formed by a DRAM, and a nonvolatile memory cell whose storage contents can be rewritten is formed by an EEPROM. 3. The nonvolatile semiconductor memory device according to 3. 5. After the RAS bar signal becomes active after the CAS bar signal becomes active,
5. The nonvolatile semiconductor device according to claim 1, further comprising a refresh signal generating means for generating said refresh signal during a period from when the S bar signal returns to inactive to when the RAS bar signal becomes inactive. Storage device. 6. A clock signal supply unit for supplying two types of clock signals having different periods to automatically generate the address, and a shorter period from the clock signal supply unit when the recall unit performs a recall operation. And clock signal switching means for supplying a clock signal having a longer cycle from said clock signal supply means when said refresh means performs a refresh operation. 3. The nonvolatile semiconductor memory device according to 1. 7. The refresh unit performs a refresh operation by sequentially rewriting the storage contents volatilely stored in each memory cell based on the address generated by the address generation unit, and refreshes each memory cell. 7. The nonvolatile semiconductor memory device according to claim 1, wherein a store operation for nonvolatilely storing the volatilely stored content in the same memory cell is performed. 8. The refresh unit performs a refresh operation by sequentially rewriting the storage content stored in each volatile memory cell based on the address generated by the address generation unit, and performs a refresh operation of each memory cell. 7. The non-volatile semiconductor memory device according to claim 3, wherein a refresh operation for storing the stored contents in said volatile memory cells in said non-volatile memory cells is performed at the time of refreshing.