JP3093011B2 - FIELD-EFFECT TRANSISTOR AND ITS MANUFACTURING METHOD, AND NONVOLATILE STORAGE ELEMENT AND NONVOLATILE STORAGE DEVICE USING THE TRANSISTOR - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an EEPROM (Electr
Field of the Invention The present invention relates to a field effect transistor suitably used in a nonvolatile memory such as an erasable / programmable read only memory (IC) and a method of manufacturing the same, and a nonvolatile memory element and a nonvolatile memory device using the transistor.

[0002]

2. Description of the Related Art For example, PZT (lead (Pb) ZirconateTi
When an electric field is applied to a ferroelectric material such as
It is known that the polarization direction is aligned with the direction of the electric field, and this alignment remains even after the electric field is removed. That is, the polarization of the ferroelectric material exhibits a hysteresis characteristic with respect to the application of an electric field. Therefore, it is possible to configure a nonvolatile memory element by utilizing such hysteresis characteristics.

A memory element using a ferroelectric material is disclosed in, for example, US Pat. No. 3,832,700 and “PbTiO ₃ Thin Film
Gate Nonvolatile Memory FET (1979 Proceedings of
the2nd Meeting on Ferroelectric Materials and Thei
r Applications F-8 pp239-244) ”and“ MFS FET ”
-A New Type of Nonvolatile Memory Swich Using PLZT
Film (Proceedings of the 9th Conference on Solid S
tate Devices, Tokyo, 1977; Japanese Journal of App
lied Physics, Volume 17 (1978) Supplument17-1, pp209
-214)].

That is, as shown in FIG. 7, a ferroelectric film 3 is formed as a gate insulating film on the surface of a P-type silicon substrate 2 on which an N ⁺ -type high-concentration impurity region 1 serving as a source / drain region is formed. The gate electrode 4 is formed on the ferroelectric film 1.
Are formed to form a field effect transistor. Then, for example, when the substrate 2 is grounded and a positive write voltage _VP is applied to the gate electrode 4, in the ferroelectric film 3, FIG.
The polarization shown in (a) occurs, and the P-type silicon substrate 2
The electrons of the minority carriers are attracted to the surface of the channel 5 to form a channel 5, and the source and the drain are brought into a conductive state. Polarization of the ferroelectric film 3 remains because also maintained after removal of the write voltage V _P, the state in which the channel 5 is formed even after the removal of the write voltage V _P.

On the other hand, a negative erase voltage −V _E is applied to the gate electrode 4.
When the voltage Vp is applied to the ferroelectric film 3, polarization occurs in the direction opposite to the direction in which the write voltage _VP is applied, as shown in FIG.
As a result, the channel disappears, and the source and the drain are cut off. This state is also maintained after the removal of the erase voltage -V _E. In this way, two states, a write state and an erase state, can be set according to the presence or absence of the channel 5, and information storage is achieved. That is, stored information can be read by checking whether the transistor is on or off.

[0006]

In the above-described transistor, the ferroelectric film 3 is formed directly on the surface of the P-type silicon substrate 2. For this reason, a metal such as Pb in the ferroelectric film 3 diffuses into the silicon substrate 2 during a heat treatment in a diffusion step at the time of forming an element or a thin film forming step, or a surface of the silicon substrate 2 is formed at the time of forming a ferroelectric film. It is oxidized. For this reason, there is a problem that characteristics as a field-effect transistor are deteriorated.

In order to solve this problem, a technique has been proposed in which a silicon oxide film is first formed on the surface of a silicon substrate, and a ferroelectric film is deposited on the silicon oxide film. In the technique according to this proposal, the circuit shown in FIG. 8 is equivalently configured near the gate. That is,
A state equivalent to the case where a capacitor C1 corresponding to the ferroelectric film and a capacitor C2 corresponding to the silicon oxide film are connected in series between the gate electrode and the channel region of the silicon substrate.

However, since the dielectric constant of the ferroelectric film is about 100 to 1000 times that of the silicon oxide film, the capacitance C1
Is much larger than the capacitance C2. Therefore, most of the voltage applied to the gate electrode is applied to the silicon oxide film corresponding to the capacitance C2. Therefore, when applying a voltage to achieve a desired polarization state to the ferroelectric film, it is necessary to apply an extremely high voltage between the gate electrode and the silicon substrate. It is difficult.

On the other hand, the diffusion of metal and oxygen hardly occurs in the silicon carbide crystal. Therefore, it is conceivable that a storage element is formed by forming a ferroelectric film on the surface of the silicon carbide substrate. However, in the silicon carbide substrate, it is difficult to diffuse impurities as well as it is difficult to diffuse metal and oxygen. Therefore, there is a problem that it is difficult to control the conductivity type by impurity diffusion. That is, when a silicon carbide substrate is used, it is difficult to form a high-concentration impurity region serving as a source / drain.

As described above, there is a major obstacle in applying a ferroelectric film to a storage device, and a storage device using a ferroelectric film has not yet been put to practical use. Therefore,
An object of the present invention is to solve the above-mentioned technical problems, to provide a good field-effect transistor using a ferroelectric film, and to provide a nonvolatile memory element and a nonvolatile memory that can be put to practical use using this field-effect transistor. Sexual storage device.

It is another object of the present invention to provide a method for manufacturing the above-mentioned field effect transistor.

[0012]

In order to achieve the above object, a field effect transistor according to the present invention comprises a semiconductor in which high-concentration impurity regions of a certain conductivity type serving as source / drain regions are formed at intervals. A silicon carbide layer having a conductivity type opposite to that of the high-concentration impurity region formed on the surface of the semiconductor substrate so as to connect between the substrate and the high-concentration impurity region, and formed on the silicon carbide layer; It includes a ferroelectric film and a gate electrode formed on the ferroelectric film.

In such a field-effect transistor, a connection is made between a region where the high-concentration impurity region is to be formed and a surface of a semiconductor substrate where a high-concentration impurity region of a certain conductivity type serving as a source / drain region is to be formed. Forming a silicon carbide layer having a conductivity type opposite to that of the high-concentration impurity region, forming the high-concentration impurity region, forming a ferroelectric film on the silicon carbide layer, It can be manufactured by forming a gate electrode thereon and forming source / drain electrodes so as to be electrically connected to the high concentration impurity region.

According to the above-described structure, since the ferroelectric film is formed on the silicon carbide layer formed on the semiconductor substrate, the metal and oxygen in the ferroelectric film diffuse into the silicon carbide layer. That is, good FET characteristics can be obtained by using a region near the surface of the silicon carbide layer as a channel region. In addition, if a silicon substrate or the like, whose conductivity type can be easily controlled by diffusion of impurities, is used as a semiconductor substrate, a high-concentration impurity region serving as a source / drain region can be easily formed. It won't be. The silicon carbide layer forms a channel region, but it is not necessary to increase the impurity concentration in the channel region, so that it is not difficult to control the conductivity type of the silicon carbide layer.

In the field effect transistor having the above structure, two types of thresholds can be set for generating a channel on the surface of the silicon carbide layer according to the polarization direction of the ferroelectric film. Is realized. In other words, a field effect transistor having two stable states is realized. Further, in the nonvolatile memory element of the present invention, by applying an electric field in a predetermined direction between the field effect transistor and the gate electrode and the semiconductor substrate, the polarization direction of the ferroelectric film is changed in a certain direction. Means for aligning and writing information, and applying an electric field in a direction opposite to the predetermined direction between the gate electrode and the semiconductor substrate to invert the polarization direction of the ferroelectric film and And means for reading out information by checking the level of the threshold value of the field effect transistor.

With this configuration, writing and erasing of information can be achieved by reversing the direction of polarization in the ferroelectric film by applying an electric field to the ferroelectric film. Further, since the threshold value for forming a channel on the surface of the silicon carbide layer changes according to the direction of polarization in the ferroelectric film, information can be read out by examining the level of this threshold value.

The ferroelectric film is preferably made of PZT. This is because the lattice constants of PZT and silicon carbide are extremely close to each other. By using a combination of a ferroelectric film made of PZT and a silicon carbide layer, a ferroelectric film having good hysteresis characteristics can be obtained. Can be formed, and the storage performance can be improved.
That is, by applying a low voltage and a low power, the polarization in the ferroelectric film can be inverted.

The large-capacity nonvolatile memory device is arranged in an array and has memory cells each having the above-mentioned field-effect transistor, means for selecting an arbitrary memory cell, and the gate of the selected memory cell. Means for applying an electric field in a predetermined direction between the electrode and the semiconductor substrate to write information by aligning the polarization direction of the ferroelectric film in a certain direction, and the gate of the selected memory cell Means for applying an electric field in a direction opposite to the predetermined direction between the electrode and the semiconductor substrate to align the polarization direction of the ferroelectric film in the opposite direction to erase information; Means for reading information by examining the level of the threshold value of the field effect transistor of the memory cell.

[0019]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view of a part of a nonvolatile memory device according to an embodiment of the present invention, showing a configuration of a field-effect transistor used as a memory transistor. An element formation region separated by a field oxide film 12 is formed on a P-type silicon substrate 11,
High-concentration impurity regions 13A and 13B (collectively referred to as "high-concentration impurity regions 13") serving as source / drain regions are formed at predetermined intervals in this element formation region. A P-type silicon carbide layer 14 is formed on the surface of substrate 11 so as to connect between high-concentration impurity regions 13A and 13B.
A ferroelectric film 15 made of PZT or the like and a gate electrode 16 made of polysilicon are sequentially stacked.

N ⁺ -type polysilicon films 17A and 17B (collectively referred to as "polysilicon film 17") are formed in a region extending from the surface of high-concentration impurity region 13 to the edge of silicon carbide layer 14. Further, a silicon oxide film 18 for preventing contact between the polysilicon film 17 and the ferroelectric film 15 is formed. A silicon oxide film 19 is formed so as to cover gate electrode 16 and the like. In the silicon oxide film 19, contact holes 20A and 20B are formed at positions corresponding to the upper portions of the high-concentration impurity regions 13A and 13B, and the contact holes 20A and 20B are formed with metal 2 serving as source / drain electrodes.
1A and 21B are deposited. Metal 21A, 21
B and the N ⁺ -type high-concentration impurity regions 13A and 13B
Are connected via the mold-type polysilicon films 17A and 17B, whereby a good ohmic contact is formed. Incidentally, reference numeral 22 denotes a passivation film.

FIG. 2 is a diagram showing a change in polarization when an electric field is applied to the ferroelectric film. As the electric field applied to the ferroelectric film increases, the polarization P in the direction of the electric field increases and the state C is saturated. Next, when the electric field is reduced, the polarization P decreases. However, even when the electric field is reduced to zero, the polarization P remains and the state D is established. Further, the polarization P decreases by applying an electric field in the opposite direction, and the polarization P becomes zero in a state E in which a certain negative electric field is applied. further,
As the electric field in the opposite direction increases, the polarization P increases in the opposite direction, and the state F is saturated. When the negative electric field is decreased from this state, the polarization P remains even when the electric field is reduced to zero, and the state becomes the state A. From this state, by increasing the positive electric field, through the state B, the saturated state C
Leads to.

As described above, the polarization P of the ferroelectric film 2 exhibits a hysteresis characteristic with respect to the electric field, and the storage device of the present embodiment achieves a storage operation by utilizing the hysteresis characteristic. FIG. 3 is a conceptual diagram showing a basic configuration of the transistor shown in FIG. Table 1 below shows the operations at the time of writing, erasing, and reading information. Hereinafter, the operation will be described with reference to FIG. 3 and Table 1.

[0023]

[Table 1]

<Write Operation> When the P-type semiconductor substrate 11 is grounded and a positive write voltage _VP is applied to the gate electrode 16,
The state shown in FIG. That is, the ferroelectric film 15
In this case, a polarization P is generated such that the gate electrode 16 side becomes “−” and the substrate 11 side becomes “+”.
Becomes the state C of FIG. At this time, electrons serving as minority carriers are induced on the surface of the silicon carbide (SiC) layer 14 in contact with the ferroelectric film 15, and the source region (N ⁺ -type high-concentration impurity region 17A) and the drain region (N ⁺ Thus, a channel connecting the high-concentration impurity region 17B) is formed. That is, in this case, the field-effect transistor is turned on (ON). After the write voltage _VP is removed, the state of the ferroelectric film 15 becomes the state D in FIG. 2 and the polarization P remains, so that the state where the channel is formed is maintained.

<Erase Operation> When a negative erase voltage −V _E (for example, V _E = V _P ) is applied to the gate electrode 16, the state shown in FIG. That is, the ferroelectric film 15
In this case, a polarization P is generated such that the gate electrode 16 side is positive and the substrate 11 side is negative, and the state becomes the state F in FIG. At this time,
Since holes are induced on the surface of the silicon carbide layer 14, the channel disappears and the source and drain are cut off. After removal of the erase voltage -V _E is strong and the state of the dielectric film 15, the state A next 2, since the polarization direction P is equal to the case of state F remains, kept in a state where the channel is lost It is.

<Read Operation> When reading stored information, no voltage is applied to the gate electrode 16. That is, as described above, the transistor is turned on in the writing state, and is turned off in the erasing state. For example, when a current is supplied to the drain, it is checked whether or not the current is detected on the source side. Thus, reading of stored information can be achieved.

As described above, in the field effect transistor constituting the storage device of this embodiment, the high-concentration impurity region 13
A ferroelectric film 15 is laminated on a silicon carbide layer 14 formed on the surface of the silicon substrate 11 so as to connect between A and 13B, and a channel is formed on the surface of the silicon carbide layer 14. Silicon carbide, compared to silicon, the diffusion rate of metal and oxygen contained in the ferroelectric,
It has a characteristic of extremely low 1/10 to 1/1000. Therefore, even during the heat treatment in the element formation process, the metal or oxygen in the ferroelectric film 15 does not diffuse into the silicon carbide layer 14. Therefore, in the above-described field effect transistor in which a channel is formed by the silicon carbide layer 14, good FET characteristics can be achieved.

On the other hand, the lattice constant of silicon is 5.43 °, while the lattice constant of silicon carbide is 4.36 °.
It is. The lattice constant of this silicon carbide is very close to the lattice constant of PZT (4.08 to 4.12 °).
Therefore, when the ferroelectric film 15 is made of PZT, the hysteresis characteristic of the inversion polarization of the ferroelectric film becomes extremely good, and a good storage operation can be achieved. That is, at low voltage and low power, the ferroelectric film 15
Can be reversed.

Further, in this embodiment, the high-concentration impurity regions 13 serving as source / drain regions are formed in the silicon substrate 11. That is, since it is difficult to control the conductivity type by impurity diffusion in the silicon carbide crystal, high-concentration impurity region 13 is formed in silicon crystal in which impurity diffusion is easy. In this manner, the channel is formed by the silicon carbide layer 14 to achieve good FET characteristics, and the high-concentration impurity region 13 is formed in the silicon substrate 11 to facilitate the fabrication of the device. I have. It is necessary to control the conductivity type of the silicon carbide layer 14 serving as a channel region to be P-type. However, since a low impurity concentration is sufficient in the channel region, it is difficult to control the conductivity type of the silicon carbide layer 14. Absent.

FIGS. 4 and 5 are sectional views showing a method of manufacturing the above-mentioned nonvolatile memory device in the order of steps. First, FIG.
As shown in (a), a silicon oxide film 41 (for example, 500 °) for a pad is formed on the surface of a P-type silicon substrate 11 by a thermal oxidation method, and a silicon nitride film (Si ₃ N ₄ ) 42 is patterned. This silicon nitride film 42 is formed, for example, under reduced pressure CV.
It is formed by the method D and has a thickness of, for example, 1500 °. Patterning after film formation is performed by applying a normal photolithography technique and a photoetching technique.

Next, as shown in FIG. 4B, a field oxide film 12 for element isolation is selectively formed by a thermal oxidation method using the silicon nitride film 42 as a mask. Then
As shown in FIG. 4C, the silicon nitride film 42 is peeled off, and the silicon oxide film 41 in the channel region is selectively removed by photolithography. Further, silicon carbide is selectively grown on the surface of substrate 11 from which silicon oxide film 41 has been removed, and silicon carbide layer 14 is formed. Silicon carbide layer 14 has a thickness of, for example, 10 n
m. Since silicon carbide does not easily grow on a silicon oxide film, selective growth of silicon carbide layer 14 in contact with substrate 11 can be easily achieved.

In this state, the silicon oxide film 41 in the source / drain regions is removed, and then,
A 00 nm polysilicon film is formed by a low pressure CVD method, and phosphorus ions are implanted. After the implantation of phosphorus ions, thermal diffusion of impurities is performed by annealing. Thereby, the N ⁺ -type high-concentration impurity regions 13A, 1
3B is formed in the substrate 11, and the polysilicon film also becomes N ⁺ type. Then, by patterning this polysilicon film, N ⁺ -type polysilicon films 17A and 17B are obtained as shown in FIG.

In this state, the surface of the polysilicon film 17 is thermally oxidized, and the silicon oxide film 18 having a thickness of 50 nm is formed.
Is formed, and the state shown in FIG. Then, for example, P
A ferroelectric film 15 made of ZT is formed, and a polysilicon film 16 serving as a gate electrode is formed on the ferroelectric film 15. Then, these films 15 and 16 are patterned by the photolithography technique to obtain the state shown in FIG. The ferroelectric film 15 can be formed by, for example, a sputtering method, a CVD method, or a SOL-GEL method. The thickness of this ferroelectric film 15 is, for example, 500 nm. The polysilicon film 16 is formed, for example, by a low pressure CVD method, and has a thickness of, for example, 500 nm.

Next, from the state shown in FIG. 5F, a silicon oxide film (BPSG) 19 is formed on the entire surface, and a reflow process is further performed to improve step coverage. In the silicon oxide film 19, the high concentration impurity region 13
A contact hole 20 is located at a position corresponding to the upper side of A, 13B.
A and 20B are formed. These contact holes 20A, 2
Reference numeral 0B denotes a metal 21A serving as a source electrode and a drain electrode electrically connected to the high-concentration impurity regions 13A and 13B via the polysilicon films 17A and 17B, respectively.
21B is formed. These metals 21A and 21B are
For example, it is made of aluminum metal. This metal 21
After the formation of A and 21B, a passivation film 22 is formed so as to cover the entire surface.
The device shown in (g) is completed.

FIG. 6 is an electric circuit diagram showing a circuit configuration of a nonvolatile memory device in which memory cells each having the above-mentioned field effect transistor are arranged in an array. Each memory cell includes the above-described field-effect transistor as a memory transistor MTr, and further includes a selection transistor STr for selecting each cell. On the other hand, the memory cell (m, n) aligned in the direction and (m, n + 1) or memory cells (m + 1, n) and (m + 1, n + 1 ) in the gate of the selection transistor STr word line W _m or word line W _{m +1} and is connected to each memory transistor MT
The gate of r are connected in common to the control gate line CGL _m or control gate line CGL m + _1. On the other hand, in the memory cells (m, n) and (m + 1, n) or the memory cells (m, n + 1) and (m + 1, n + 1) aligned in the direction intersecting the word lines W _m and W _{m + 1} ,
Drain of each selection transistor are commonly connected to the bit line BL _n or BL n _{+ 1,} further source and substrate of the memory transistor MTr source line SL
_n or SL _{n + 1} .

Table 2 below shows that the memory cell (m, n)
The selected and writing, when erasing and reading, the bit line BL _n, BL _{n + 1,} the source line S _n, S _{n + 1,} gate line W _n, W _{n + 1} and the control gate line CGL
_n and CGL _{n + 1} are collectively shown. In the following, referring to Table 2 and FIG.
Each operation of writing, erasing and reading information to and from memory cell (m, n) will be described. In Table 2,
The symbol "-" indicates that the signal line is opened or an arbitrary voltage is applied.

[0037]

[Table 2]

When writing is performed, a memory driving circuit (not shown)
Road is source line SL_nAnd word line WL_m,
WL_{m + 1}-1 / 2 ／ V_PControl gate line C
GL _m+ 1/2 · V_PIs applied. This allows the note
In the recell (m, n), the semiconductor substrate 11, the gate 16,
, The write voltage V at which the gate 16 is positive_PIs applied
It is. Thereby, the polarization direction in the ferroelectric film 15 is changed.
Aligned in the direction from the gate 16 to the substrate 11, the information
Is achieved. That is, in this state, the ferroelectric
The surface of the P-type silicon carbide layer 14 immediately below the body film 15
Carrier electrons are induced, which causes the channel to
Will be formed. As a result, the memory
The star MTr is in a state where the threshold value is low.
Your gate line CGL_mIs set to ground potential,
The memory transistor MTr is turned on.

It should be noted, write voltage V _P of the above strong minimum voltage it is possible to reverse the polarization direction of the dielectric film 15 relative to the coercive electric field is (in FIG. 2 B, the voltage at the point E), the following The value that satisfies the relationship of the expression is selected.

[0040]

(Equation 1)

[0041] During the write operation, the memory cell (m, n) in the control gate line CGL _m memory cells sharing the (m, n + 1), the source lines SL _{n + 1} is the ground potential. Therefore, in the memory transistor MTr of the cell (m, n + 1), since only half of the voltage 1/2 · V _P of the write voltage V _P is applied to the ferroelectric film 15, the arrangement of the polarization No change occurs, and writing to memory transistor MTr does not occur. Similarly, in the memory cell (m, n) and the memory cells sharing the source line _{SL n (m + 1, n} ), to the control gate line CGL m + ₁ is the ground potential, never write results . In the memory cell (m + 1, n + 1), no writing occurs because both the control gate line CGL _{m + 1} and the source line SL _{n + 1} are set to the ground potential.

The erasing operation is achieved by substantially the same operation as the writing operation. That is, the erasing operation is an operation of aligning the polarization direction in the ferroelectric film 15 of the memory transistor MTr of the selected memory cell (m, n) in the direction opposite to that in the writing state. the time performed by applying an opposite polarity voltage to the control gate line CGL _m and the source lines SL _n. In this erased state, the threshold value of the memory transistor MTr of the memory cell (m, n) is in a high state, and when the control gate line CGL is set to the ground potential, the memory transistor MTr is turned off.

At the time of reading information, the source line SL_n,
SL_{n + 1}And control gate line CGL_m, CGL_{m + 1}
Are set to the ground potential. Therefore, the write state
The memory transistor MTr of the cell conducts, but the
Transistor MTr and shut-off state of memory cell in active state
Becomes In this state, the memory cells (m, n), (m, n
+1) corresponding to the word line WL_mIn the selection tran
A voltage that allows the transistor STr to conduct (for example,
5V). Also, the bit line BL _n, BL
_{n + 1}, A predetermined sense voltage S is generated. And this
The bit line BL_n, BL_{n + 1}Of electric potential drop
It is monitored by an unillustrated configuration whether or not it fluctuates.

That is, if the memory cell (m, n) is in the write state, the memory transistor MTr of the memory cell (m, n) is in the conductive state, so that the bit line BL _n
Potential of drops being pulled to the ground potential which is the potential of the source line SL _n. When the memory cell (m, n) is in the erased state, the memory transistor MTr of the memory cell (m, n) is in the cut-off state, so that the potential drop does not occur. Therefore, by monitoring the drop in the potential of the bit line BL _n, so that the reading of information stored in the memory cell (m, n) is achieved.

Further, the memory cell (m, n) and a common word line WL _m memory cell connected to the (m, n + 1)
The same applies to. That is, bit line B
By providing a configuration for individually monitoring the potentials of L _n and BL _{n + 1} , each bit line BL _n and BL _{n + 1}
At the same time by generating the sense voltage S, it is possible to read information from a plurality of memory cells connected to the word line W _m in parallel.

[0046] Incidentally, the memory cell (m, n) and connected to a common bit line BL _n memory cells (m + 1, n)
Since the word line WL _{m + 1} is set to the ground potential,
No information reading occurs. In this manner, an arbitrary memory cell can be selected from a plurality of memory cells arranged in an array to write, erase, and read information. In this manner, a large-capacity electrically rewritable memory utilizing the hysteresis characteristic of the ferroelectric material with respect to the electric field is realized.

The present invention is not limited to the above embodiment. For example, in the above embodiment, PZT was taken as an example of a ferroelectric substance, but for example, PLZT (lead
(Pb) Lanthanum Zirconate Titanate), LiNbO
₃ , other ferroelectrics such as BaMgF ₄ may be applied. In this case, since the metal and oxygen in the ferroelectric film do not diffuse into the silicon carbide layer, good FET characteristics can be obtained. Can be.

Further, in the above embodiment, an N-channel field-effect transistor is taken as an example, but a P-channel transistor can be easily formed in the same manner. Further, in the above embodiment, a state where the transistor is conductive is defined as a write state, and a state where the transistor is turned off is defined as an erase state. However, any state is defined as a write state or an erase state. You may.

Various other changes can be made without changing the gist of the present invention.

[0050]

As described above, according to the present invention, a silicon carbide layer is formed on the surface of a semiconductor substrate, a ferroelectric film is laminated on the silicon carbide layer, and a channel is formed in the silicon carbide layer. I have to. Since metal and oxygen from the ferroelectric film hardly diffuse into this silicon carbide layer, a good F
ET characteristics can be achieved.

In addition, since a silicon substrate or the like in which the conductivity type can be easily controlled by impurity diffusion can be applied to the semiconductor substrate, it is easy to form a high-concentration impurity region serving as a source / drain region. There is no difficulty. In this way, a field effect transistor that can easily be put to practical use, in which the ferroelectric film is applied to the gate insulating film, is realized. As a result, by using the above-mentioned field effect transistor, the way to practical use of a non-volatile storage element or a storage device utilizing the property of a ferroelectric substance in which polarization has a hysteresis characteristic with respect to an electric field is opened.

[Brief description of the drawings]

FIG. 1 is a sectional view of a part of a nonvolatile memory device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a hysteresis characteristic of a polarization of a ferroelectric substance with respect to an electric field.

FIG. 3 is a conceptual diagram showing a principle configuration of a memory transistor of the nonvolatile memory device.

FIG. 4 is a cross-sectional view showing a step of manufacturing the nonvolatile memory device in the order of steps.

FIG. 5 is a cross-sectional view showing a step of manufacturing the nonvolatile memory device in the order of steps.

FIG. 6 is an electric circuit diagram showing a circuit configuration of the nonvolatile memory device in which memory cells are arranged in an array.

FIG. 7 is a conceptual diagram showing a basic configuration of the prior art.

FIG. 8 is an electric circuit diagram showing an equivalent circuit near a gate in a proposal example in which a silicon oxide film is interposed between a ferroelectric film and a silicon substrate.

[Explanation of symbols]

Reference Signs List 11 P-type semiconductor substrate 13A N ⁺ -type high concentration impurity region (source region) 13B N ⁺ -type high concentration impurity region (drain region) 14 P-type silicon carbide layer 15 ferroelectric film 16 gate electrode 21A metal (source electrode) 21B Metal (drain electrode)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/10 H01L 29/788 H01L 29/792

Claims (4)

(57) [Claims] 1. A semiconductor substrate formed with a certain concentration of high-concentration impurity regions serving as source / drain regions at intervals and formed on the surface of the semiconductor substrate so as to connect the high-concentration impurity regions. A silicon carbide layer having a conductivity type opposite to that of the high-concentration impurity region, a ferroelectric film formed by laminating the silicon carbide layer, and a gate electrode formed on the ferroelectric film. Characteristic field effect transistor. 2. The semiconductor device according to claim 1, wherein a high-concentration impurity region of a certain conductivity type serving as a source / drain region is formed on a surface of the semiconductor substrate.
Forming a silicon carbide layer having a conductivity type opposite to that of the high-concentration impurity region so as to connect between the regions where the high-concentration impurity region is to be formed; and forming the high-concentration impurity region; Forming a ferroelectric film on the silicon carbide layer; forming a gate electrode on the ferroelectric film; forming source / drain electrodes so as to be electrically connected to the high concentration impurity region A method of manufacturing a field effect transistor. 3. A field effect transistor according to claim 1, wherein an electric field in a predetermined direction is applied between said gate electrode and said semiconductor substrate to align the polarization direction of said ferroelectric film in a certain direction. Means for writing information by erasing, and applying an electric field in a direction opposite to the predetermined direction between the gate electrode and the semiconductor substrate to invert the polarization direction of the ferroelectric film to erase the information. And a means for reading information by examining the level of the threshold value of the field effect transistor. 4. A plurality of memory cells arranged in an array and each having the field effect transistor according to claim 1, means for selecting an arbitrary memory cell, the gate electrode of the selected memory cell and a semiconductor Means for applying an electric field in a predetermined direction between the substrate and the substrate to write information by aligning the polarization direction of the ferroelectric film in a certain direction; Means for erasing information by applying an electric field in a direction opposite to the predetermined direction to the substrate and aligning the polarization direction of the ferroelectric film in the opposite direction; Means for reading information by examining the level of the threshold value of the field effect transistor.