JP3064994B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.
The present invention relates to a fine MOS type semiconductor device for realizing a highly integrated semiconductor circuit and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, in order to improve the performance of a semiconductor circuit, high integration of a semiconductor element is required, and therefore, the element area must be reduced. It is generally said that an element region of a transistor is determined by an element isolation region made of an oxide film.

Conventionally, up to a transistor design rule of about 0.35 mm, an isolation region is formed by LOCOS (LOCal Oxidation of Si) using a thermal oxidation method.
licon) or modified LOCOS method.
However, in the method using the thermal oxidation method, a portion below the silicon nitride film that defines the element region is oxidized during the oxidation, resulting in a bird's beak, which hinders miniaturization of the element isolation region.

[0004] Therefore, a shallow trench isolation (Shallow Trenc
h Isolation) technology is becoming mainstream. The method of forming this shallow trench is described in 1997 Symposium on VL
SI Technology Digest of Technical Papers (1997 Symposium on VLSI Technology Digest of Te
7 (A) to 8 (G) based on the method shown on pages 125 to 126.

FIG. 7A shows a pad silicon oxide film 2 formed on a semiconductor substrate 1 made of silicon by a thermal oxidation method, and furthermore, a plasma chemical vapor (CVD) process.
FIG. 3 is a view showing a state where a silicon nitride film 3 is deposited by an eposition method. These film thicknesses are 10
20 nm, and the thickness of the silicon nitride film 3 is about 150-200 nm.

The film thickness of this silicon nitride is determined by chemical mechanical polishing (CMP) performed later.
The thickness is set to a thickness that can be a stopper film for polishing in the method g). Next, the resist 4 is patterned by photolithography, and the silicon nitride film and the silicon oxide film in a region to be an element isolation region are etched using the photoresist as a mask (FIG. 7B).

Further, a trench is formed by etching the silicon substrate in a region to be an element isolation region (FIG. 7).
(C)). The depth of the trench 5 is 300 to 400 n.
The etching is performed so as to give an inclination angle of 75 to 80 °. Next, after the photoresist 4 is peeled off, FIG.
As shown in (D), the photoresist 4 is formed of a P-type MOSFET.
Boron is ion-implanted so as to cover only the T region.

This ion implantation of boron is carried out by rotating ion implantation so that it is also implanted into the side wall of the trench groove 5, and an implantation angle is set so as not to be implanted into the region where the N-type transistor element is formed. To 10-40 °,
If the thickness of the silicon nitride film 3 serving as a stopper film in the CMP process is 150 to 200 nm by the rotation ion implantation at a rotation speed of about 1.5 rotations per second, the ion implantation acceleration energy is 20 keV and the implantation dose is Quantity 1 × 1
Ion implantation is performed at 0 ¹³ to 4 × 10 ¹³ cm ⁻² .

In this ion implantation, when the width of the element isolation becomes narrow, the threshold voltage of the MOSFET is lowered. The silicon atoms generated by the point defect combine with the impurity and pass through the trench isolation trench. Suppressing the so-called inverse narrow channel effect, in which the transition to the insulating film in the trench isolation groove portion lowers the impurity concentration of the transistor channel portion between the trench isolation trench portions to lower the threshold value of the transistor. This is what you do.

After this ion implantation step, the photoresist 4
And oxidation of the inner wall of the trench for rounding the corner portion 51 of the trench 5 is performed by about 10 nm. after,
500-700 n of silicon oxide film 6 by CVD
m, and bury the inside of the trench (FIG. 8E,
The oxide film on the inner wall is not shown in the figure because it is thin.)

Thereafter, the surface is planarized by CMP until the silicon nitride film 3 serving as a stopper appears (FIG. 8).
(F)). Thereafter, the silicon nitride film 3 serving as a stopper is etched with a phosphoric acid-based etchant, and the pad oxide film 2 is removed with a hydrofluoric acid-based etchant to form an isolation region (FIG. 8G).

Thereafter, impurities for the well and the channel region are introduced by ion implantation, a gate oxide film is formed by thermal oxidation, and a polysilicon film to be a gate electrode is formed by CVD. This is the same as the process for forming a normal MOS transistor.

[0013]

However, in recent years, in the process of forming a fine transistor element requiring a shallow impurity diffusion layer, a point defect generated when impurities are introduced into a source or drain region is caused. It has been pointed out that abnormal impurity diffusion phenomenon becomes a problem.

This is due to the fact that the introduction of impurities into the source and the drain uses an ion implantation method in a normal semiconductor manufacturing process. Then, during the ion implantation step, as described above, the impurities are implanted into the silicon substrate with acceleration energy. However, when the impurities having this energy collide with the silicon atoms constituting the substrate, the impurities in the substrate are damaged. The silicon atoms that constitute the crystal are displaced from the crystal structure position (this phenomenon is called knock-on), and the silicon atoms that are displaced from the crystal lattice position are point defects. Atom).

This interstitial silicon atom usually has some equilibrium.
Concentration, i.e., exists in the silicon substrate at a certain concentration
However, the concentration is 5 × 10 which is the atomic density of the silicon substrate.
^{twenty two}cm ^-3Compared to 10¹¹cm^-3Because it is about the amount
Usually this is rarely a problem. But Ion
The concentration of interstitial silicon generated during the implantation process
10^{twenty two}cm^-3It happens too much.

If the interstitial silicon is present at a high concentration, the diffusion of the impurity will be several to several thousand times faster than the normal diffusion (especially the N-type MOSFET).
Boron, which is an impurity that determines the threshold voltage, is likely to diffuse abnormally under the influence of the interstitial atoms.) The phenomenon that the diffusion of the impurity is accelerated is caused by the fact that the interstitial silicon and the impurity combine, and this diffuses abnormally faster than the case of only the impurity, and the interstitial silicon atoms are directed toward the silicon oxide film. For example, when high-concentration interstitial silicon atoms are present at the interface between silicon oxide and a silicon substrate, the distribution of impurities in the vicinity of the interface after the heat treatment is oxidized. Pile-up in which impurities accumulate at the polar interface between silicon and the silicon substrate and a phenomenon in which the impurity concentration is reduced in the silicon substrate region in the vicinity thereof occur.

Therefore, the impurity concentration in the silicon substrate, which determines the electrical performance of the transistor, in such a situation, where the element isolation regions are dense, where the fine isolation width region and the region where the element density is relatively low, are satisfied. Is different. Therefore, plotting the relationship between the transistor area width and the threshold voltage of the transistor is as shown in FIG.

That is, as the miniaturization progresses and the element isolation region becomes narrower and the transistor width becomes narrower, the threshold voltage becomes lower, that is, a so-called reverse narrow channel phenomenon occurs.
If such a phenomenon occurs, the electrical characteristics of the transistor will change if the size of the element region is different, making the design difficult, and the diffusion of impurities through such defects will determine the performance of the transistor. Therefore, the semiconductor device is susceptible to process fluctuations. For example, when the process temperature fluctuates, such as heat treatment conditions for activating the source / drain, the characteristics of the transistor device greatly fluctuate.

In particular, the reduction of the threshold voltage in the fine region has a great disadvantage to the integrated circuit system itself, such as an increase in transistor off-leakage and an increase in power consumption. In the conventional example shown in FIGS. 7 and 8 in which the inverse narrow channel effect is suppressed, a mask step by photolithography is increased so that boron ion implantation is not implanted into the P-type MOSFET region. There is a problem in that the implantation dose of the ion implantation must be changed, which places a heavy burden on circuit design and manufacturing processes.

As described above, the reverse narrow channel phenomenon is a remarkable phenomenon when a shallow trench isolation technique in which an element region is miniaturized is used, and becomes a serious problem rapidly from a fine device of 0.2 nm or less. It is getting. Japanese Patent Application Laid-Open No. 61-252645, which is shown as a prior art, discloses that impurities corresponding to the expected decrease in impurities around the trench isolation trench portion are previously ion-implanted. Japanese Patent Application Laid-Open No. 8-250583 discloses a technique in which an impurity is implanted in advance into the end of the trench groove for the purpose of controlling the conductivity of the end of the trench groove. It is not used for the purpose of preventing

Accordingly, an object of the present invention is to improve the above-mentioned disadvantages of the prior art, and in particular, to provide a semiconductor device using shallow trench isolation,
By suppressing the occurrence of the inverse narrow channel effect that changes the performance of the transistor from the design value without complicating the process, stable electrical characteristics can be obtained even if the transistor element region is miniaturized. A method for manufacturing a semiconductor device is provided.

[0022]

In order to achieve the above-mentioned object, the present invention employs the following basic technical structure. That is, as a first aspect according to the present invention, in a MOS type semiconductor device, in a trench isolation in an element isolation structure, the trench is embedded in the trench isolation.
An isolation silicon oxide film are provided between the silicon substrate
A semiconductor device in which a layer in which nitrogen is piled up is formed in an inner portion of the silicon substrate side in contact with the formed interface , and a second embodiment according to the present invention includes, for example,
A first step of forming first and second insulating film layers on the surface of the semiconductor substrate, a second step of forming a trench extending from the insulating film layer to the semiconductor substrate after the first step, A third step of implanting nitrogen into the trench groove, a fourth step of burying a third insulating film in the trench groove, and then a third step until the second insulating film appears on the surface. A semiconductor device manufacturing method including a fifth step of planarizing the surface of an insulating film by a mechanical polishing method, and a sixth step of peeling off the second and first insulating films.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor device and the method of manufacturing the same according to the present invention employ the above-mentioned technical configuration, and therefore, it is possible to effectively prevent the occurrence of the inverse narrow channel phenomenon. It becomes. That is, as described above, the cause of the reverse narrow channel phenomenon is that point defects such as interstitial silicon atoms generated during an ion implantation process such as formation of a source / drain diffuse toward the silicon oxide film and cause element isolation. The main reason is that the impurity concentration decreases at the interface between the silicon oxide film and the silicon substrate.

Therefore, it is necessary to suppress the flow of diffusion of interstitial silicon atoms into the silicon oxide film. For this reason, according to the present invention, a layer in which nitrogen is piled up after the trench etching for shallow trench isolation is performed. Another object is to form a silicon nitride film layer and block interstitial silicon atoms, thereby suppressing a decrease in concentration due to diffusion of impurities at the interface of the isolation region.

As a method of forming a silicon nitride film,
(1) heat treatment by ion implantation of nitrogen after forming the element isolation region; (2) nitriding in an atmosphere containing nitrogen or ammonia, NO, N ₂ O, etc. after forming the trench groove. . That is, in the present invention,
Even in a semiconductor element in an integrated circuit having a fine element isolation region, a stable semiconductor element whose electrical characteristics do not depend on the element isolation region can be realized by suppressing a decrease in impurities that occurs near the element isolation region.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific examples of a semiconductor device and a method of manufacturing the semiconductor device according to the present invention will be described in detail with reference to the drawings. FIGS. 1A to 2G are cross-sectional views illustrating a configuration of a specific example of a semiconductor device according to the present invention and an example of a manufacturing method thereof. In a MOS type semiconductor device, an element isolation silicon oxide film 6 and a silicon substrate 1 in a trench isolation element isolation structure 5 are formed.
A semiconductor device 20 in which a layer 31 in which nitrogen is piled up is formed on the side of the silicon substrate 1 at the interface with the semiconductor device 20 is shown.

In the present invention, the nitrogen-containing layer 31 may be a nitride film layer, or the nitrogen-containing layer may be a nitrogen-containing oxide film layer. Further, in the semiconductor device according to the present invention, the nitrogen-containing oxide film layer may be an oxynitride film. In such a case, the oxynitride film may be a silicon oxide film containing a nitrogen component.

That is, the semiconductor device 2 according to the present invention
It is preferable that the layer 31 in which the nitrogen is piled up is a layer in which a silicon component, an oxygen component, and a nitrogen component are mixed. Hereinafter, specific examples of the respective manufacturing methods of the semiconductor device 20 according to the present invention will be described individually with reference to the drawings.

FIGS. 1A to 2 show a first embodiment of the present invention.
This will be described with reference to FIG. FIG. 1A shows that a pad silicon oxide film 2 is formed on a semiconductor substrate 1 by a thermal oxidation method, and furthermore, a plasma chemical vapor deposition (CVD).
2 shows a state where the silicon nitride film 3 is deposited by the (ion) method. These film thicknesses are 10 to 2 for the silicon oxide film 2.
0 nm, and the silicon nitride film 3 has a thickness of about 150 to 200 nm.

The film thickness of this silicon nitride is determined by chemical mechanical polishing (CMP) performed later.
The thickness is set to a thickness that can be a stopper film for polishing in the method g). Next, the resist 4 is patterned by photolithography, and the silicon nitride film and the silicon oxide film in a region to be an element isolation region are etched using the photoresist as a mask (FIG. 1B).

Further, a trench groove 5 is formed by etching the silicon substrate in a region to be an element isolation region.
(C)). The depth of the trench 5 is 300 to 400 n.
The etching is performed so as to give an inclination angle of 75 to 80 °. Next, after the photoresist 4 is peeled off, FIG.
As shown in (D), nitrogen is ion-implanted into the entire substrate. Nitrogen ion implantation is performed at an implantation energy of about 20 keV and a dose of 1 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ⁻² .

After this ion implantation step, the photoresist 4
And oxidation of the inner wall of the trench for rounding the corner portion 51 of the trench 5 is performed by about 10 nm. During the oxidation of the inner wall, pile-up occurs at the interface between the oxide film and the silicon substrate, and the silicon nitride film 31 is formed. This silicon nitride film layer suppresses the diffusion of interstitial silicon into the oxide film that occurs in a later step (generated by ion implantation for forming the source and drain) and reduces impurities near the oxide film / silicon interface for element isolation. It has the function of suppressing, and consequently, the inverse narrow channel effect.

It is considered that the composition is a film containing more nitrogen than the thermal silicon nitride film. After that, CV
A silicon oxide film 6 is deposited to a thickness of 500 to 700 nm by the method D to bury the inside of the trench (FIG. 2 (E), which is not shown in the figure because the oxide film on the inner wall is thin). Thereafter, the surface is planarized by CMP until the silicon nitride film 3 serving as a stopper appears (FIG. 2F).

Thereafter, the silicon nitride film 3 serving as a stopper is etched with a phosphoric acid-based etchant, and the pad oxide film 2 is removed with a hydrofluoric acid-based etchant to form an isolation region (FIG. 2G). ). After that, the impurity for the well and the channel region is introduced by the ion implantation method, the gate oxide film is further formed by the thermal oxidation method, and the polysilicon film to be the gate electrode is formed by the CVD method. This is the same as the process for forming a normal MOS transistor.

In the present invention, in this process, even if the element isolation region is reduced, the reduction of impurities near the interface of the element isolation region is suppressed, so that the variation in the threshold voltage of the MOSFET is reduced. Disappears. FIG. 10 shows the dependence of the threshold voltage of the N-type MOSFET on the element isolation region width for explaining this effect.

● indicates the case where nitrogen was not ion-implanted. ○ indicates that nitrogen was implanted at an acceleration energy of 2 according to the previous embodiment.
This is a characteristic of a sample implanted with ions at 0 keV and an ion implantation dose of 2 × 10 ¹⁴ cm ⁻² . As can be seen from the figure, when nitrogen ion implantation was not performed, the fluctuation amount increased as the element isolation region became smaller, whereas when nitrogen ion implantation was performed, the element isolation region was reduced to 0.3 mm. It turns out that there is almost no change.

As described above, it can be understood that suppressing the diffusion of interstitial silicon atoms in the vicinity of an oxide film for element isolation by nitrogen ion implantation is very effective for stabilizing the electrical characteristics of a transistor element. . In this embodiment, the ion implantation of nitrogen is performed immediately after the trench groove is formed. However, even if nitrogen ion implantation is performed after the trench groove is buried with a CVD oxide film and the CMP process is performed, a normal MOS transistor may be used.
In the FET manufacturing process, a thermal oxidation process for forming a through oxide film is performed before ion implantation in order to introduce impurities into the well and the channel region. Pile-up occurs at the interface, and an oxide film containing nitrogen is formed, so that a similar effect can be obtained.

Next, a second embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIGS. FIG. 3A shows a pad silicon oxide film 2 formed on a semiconductor substrate 1 by a thermal oxidation method.
To form a plasma chemical vapor phase (CVD: Chemical V).
2 shows a state where the silicon nitride film 3 is deposited by the apor deposition method.

The thickness of the silicon oxide film 2 is 10 to
The thickness of the silicon nitride film 3 is set to about 150 to 200 nm. The thickness of the silicon nitride is set to a thickness that can be used as a stopper film for polishing in a later-described chemical mechanical polishing (CMP) method.

Next, the resist 4 is patterned by photolithography, and the silicon nitride film and the silicon oxide film in a region to be an element isolation region are etched using the photoresist as a mask (FIG. 3B). Further, the silicon substrate in a region to be an element isolation region is etched to form a trench 5 (FIG. 3C).

The depth of the trench 5 is 300 to 400.
Etching is performed so as to give a tilt angle of 75 to 80 °. Next, after the photoresist 4 is peeled off, as shown in FIG.
Oxynitridation is performed in an atmosphere of ₂ O or a gas diluted with nitrogen.

This oxynitrided film 32 is a silicon oxide layer containing a large amount of nitrogen, and has a function of blocking the flow of diffusion of interstitial silicon atoms, as in the first embodiment, and is therefore generated in a later step ( Suppress diffusion of interstitial silicon into oxide film (produced by ion implantation for source / drain formation), suppress reduction of impurities near oxide / silicon interface for element isolation, and consequently, reverse narrow channel effect It has the function of doing.

After this step, the process is the same as that of the first embodiment.
Oxidation of the inner wall of the trench for rounding 1 is performed to about 10 nm. After that, the silicon oxide film 6 is deposited by the CVD
0 to 700 nm is deposited to bury the inside of the trench (FIG. 4)
(E), the oxide film on the inner wall portion is not shown in the figure because it is thin).

Thereafter, the surface is planarized by CMP until the silicon nitride film 3 serving as a stopper appears (FIG. 4).
(F)). Thereafter, the silicon nitride film 3 serving as a stopper is etched with a phosphoric acid-based etchant, and the pad oxide film 2 is further removed with a hydrofluoric acid-based etchant to form an isolation region (FIG. 4G). After that, the impurity for the well and the channel region is introduced by the ion implantation method, the gate oxide film is further formed by the thermal oxidation method, and the polysilicon film to be the gate electrode is formed by the CVD method. This is the same as the process for forming a normal MOS transistor.

Next, a third specific example of the present invention will be described with reference to FIG.
This will be described with reference to FIGS. FIG. 5A shows a pad silicon oxide film 2 formed on a semiconductor substrate 1 by a thermal oxidation method.
To form a plasma chemical vapor phase (CVD: Chemical V).
2 shows a state where the silicon nitride film 3 is deposited by the apor deposition method.

The thickness of the silicon oxide film 2 is 10 to
The thickness of the silicon nitride film 3 is set to about 150 to 200 nm. The thickness of the silicon nitride is set to a thickness that can be used as a stopper film for polishing in a later-described chemical mechanical polishing (CMP) method.

Next, the resist 4 is patterned by photolithography, and using the photoresist as a mask, the silicon nitride film and the silicon oxide film in a region to be an element isolation region are etched (FIG. 5B). Further, the silicon substrate in a region to be an element isolation region is etched to form a trench 5 (FIG. 5C).

The depth of the trench 5 is 300 to 400.
Etching is performed so as to give a tilt angle of 75 to 80 °. Next, after removing the photoresist 4, 5 (D), the whole substrate N ₂ or NH ₃
Nitriding in atmosphere. Furthermore, if the temperature of this nitriding is, for example, NH ₃ , the pressure is 900 to 1000 ° C. at normal pressure.
For 10 to 30 seconds.

By this nitridation, a silicon nitride film 33 is formed with a thickness of about 3 to 5 nm. Thereafter, 1050-11
The oxidation step is performed at 00 ° C. in an oxidizing atmosphere, for example, an H ₂ O, H ₂ diluted O ₂ atmosphere. This is because the interface between the silicon nitride 33 formed by nitriding and the silicon substrate has many levels, and it is necessary to oxidize the interface to reduce the interface level.

The reoxidized film 34 is a silicon oxide layer containing a large amount of nitrogen, as in the first and second embodiments, and has a function of blocking the flow of diffusion of interstitial silicon atoms. It suppresses the diffusion of interstitial silicon into the oxide film that occurs in the subsequent process (generated by ion implantation for forming the source / drain), and suppresses the reduction of impurities near the oxide film / silicon interface for element isolation. It works to suppress the narrow channel effect.

After this step, the process is the same as that of the first embodiment.
Oxidation of the inner wall of the trench for rounding 1 is performed to about 10 nm. After that, the silicon oxide film 6 is deposited by the CVD
Deposit 0 to 700 nm to bury the inside of the trench (FIG. 6)
(F), the oxide film on the inner wall portion is not shown in the figure because it is thin).

Thereafter, the surface is planarized by CMP until the silicon nitride film 3 serving as a stopper appears (FIG. 6).
(G)). Thereafter, the silicon nitride film 3 serving as a stopper is etched with a phosphoric acid-based etchant, and the pad oxide film 2 is further removed with a hydrofluoric acid-based etchant to form an isolation region (FIG. 6H). Thereafter, it is usual to introduce impurities for the well and channel regions by ion implantation, further form a gate oxide film by thermal oxidation, and form a polysilicon film to be a gate electrode by CVD. This is the same as the step of forming the MOS transistor.

According to the above-mentioned invention, the conductivity type of the transistor to be formed, that is, the N-type MOSFET and the P-type MOSFET are separated from each other, that is, the silicon oxide film for element isolation and the silicon substrate can be formed without adding a mask step. An oxide film layer containing nitrogen can be formed at the interface of the silicon oxide film. Further, in each of these embodiments, the diffusion of interstitial silicon atoms into the silicon oxide film in element isolation is suppressed, and the reduction of impurities near the element isolation region is suppressed. Thus, the effect of suppressing and stabilizing the electrical characteristics of the transistor element can be obtained.

As is apparent from the above description, the method for manufacturing the semiconductor device according to the present invention is, in a first aspect, a first method for forming a first and a second insulating film layer on the surface of a semiconductor substrate. A second step of forming a trench extending from the insulating film layer to the semiconductor substrate after the first step; a third step of ion-implanting nitrogen into the trench; A fourth step of embedding a third insulating film therein, and thereafter, a fifth step of flattening the surface of the third insulating film by a mechanical polishing method until the second insulating film appears on the surface, Further, the present invention provides a method for manufacturing a semiconductor device, comprising: a sixth step of removing the second and first insulating films. In this case, the ion implantation of nitrogen in the third step is performed at an acceleration energy of 15 to 30 keV, The dose is 1
It is desirable to perform the process at × 10 ¹⁴ to 1 × 10 ¹⁵ .

As a second aspect of the method of manufacturing a semiconductor device according to the present invention, a first step of forming first and second insulating film layers on a surface of a semiconductor substrate; A second step of forming a trench groove extending from the insulating film layer to the semiconductor substrate, a third step of thermally oxynitriding the entire substrate, and a third step of embedding a third insulating film in the trench groove. Step 4, after that, a fifth step of flattening the surface of the third insulating film by a mechanical polishing method until the above-mentioned second insulating film appears on the surface, and further, the second and first insulating films And a sixth step of separating the semiconductor device. The thermal oxynitriding in the third step is performed in an NO or N ₂ O atmosphere at a substrate temperature of 750.
It is desirable to carry out at 950 ° C.

Further, as a third aspect related to the method of manufacturing a semiconductor device according to the present invention, the first aspect is that the first
And a first step of forming a second insulating film layer; a second step of forming a trench extending from the insulating film layer to the semiconductor substrate after the first step; and a second step of nitriding the entire substrate. Step 3, followed by a fourth step of oxidizing the entire substrate, a fifth step of embedding a third insulating film in the trench, and thereafter, until the above-mentioned second insulating film appears on the surface. A sixth step of flattening the surface of the third insulating film by a mechanical polishing method; and a seventh step of peeling off the second and first insulating films. The nitriding treatment step in the third step is preferably performed in a nitrogen atmosphere or an NH ₃ atmosphere, and the substrate temperature at that time is preferably 900 to 1050 ° C.

Further, in the above embodiment, the oxidation treatment step after the nitridation treatment in the fourth step is performed in an oxidizing atmosphere such as oxygen, steam, or hydrogen-diluted oxygen. The temperature is desirably set at 750 to 950 ° C. In another aspect of the present invention, after forming first and second insulators on the surface of the semiconductor substrate, a groove reaching the semiconductor substrate is formed, and a third groove is formed in the groove.
After embedding the first insulating film, the surface of the third insulating film is planarized by a mechanical polishing method until the second insulating film appears on the surface, and further, after the second and first insulating films are separated, the semiconductor device is removed. Before performing ion implantation of impurities that determine the electrical characteristics of the substrate, and before forming a through oxide film therefor,
It is also possible to adopt a method such as ion implantation of nitrogen.

In the present invention, since the above-described structure is employed, a buried oxide film having a low etching rate is formed without complicating the process, so that the transistor region and the device region are completely flat. Therefore, high integration and stabilization of transistor characteristics can be achieved at the same time.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a first specific example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view illustrating a first specific example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a cross-sectional view illustrating a second specific example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a cross-sectional view illustrating a second specific example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a cross-sectional view illustrating a third specific example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a cross-sectional view illustrating a third specific example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 7 is a cross-sectional view illustrating an example of a conventional method for manufacturing a semiconductor device.

FIG. 8 is a sectional view illustrating an example of a conventional method for manufacturing a semiconductor device.

FIG. 9 is a diagram illustrating an inverse narrow channel effect.

FIG. 10 is a diagram illustrating an effect of reducing an inverse narrow channel effect according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Pad silicon oxide film 3 ... Silicon nitride film 32 ... Thermal oxynitride film 33 ... Silicon nitride film by nitridation 34 ... Oxidized silicon nitride film 4 ... Photoresist 5 ... Trench groove 51 ... Corner of trench 6. CVD silicon oxide film

Claims (16)

(57) [Claims] In a MOS type semiconductor device, in a trench isolation element isolation structure, the trench is embedded in the trench isolation.
The silicon substrate side in contact with the interface formed between the embedded element isolation silicon oxide film and the silicon substrate
Wherein a layer in which nitrogen is piled up is formed in an inner portion of the semiconductor device. 2. The semiconductor device according to claim 1, wherein said nitrogen-containing layer is a nitride film layer. 3. The semiconductor device according to claim 1, wherein the layer containing nitrogen is an oxide film layer containing nitrogen. 4. The semiconductor device according to claim 3, wherein said oxide film layer containing nitrogen is an oxynitride film. 5. The oxynitride film according to claim 4, wherein the silicon oxide film contains a nitrogen component.
13. The semiconductor device according to claim 1. 6. The semiconductor device according to claim 1, wherein the layer in which nitrogen is piled up is a layer in which a silicon component, an oxygen component, and a nitrogen component are mixed. 7. A first step of forming first and second insulating film layers on a surface of a semiconductor substrate, and a second step of forming a trench extending from the insulating film layer to the semiconductor substrate after the first step. Step, then a third step of implanting nitrogen into the trench groove, a fourth step of burying a third insulating film in the trench groove, and then the second insulating film A fifth step of flattening the surface of the third insulating film by a mechanical polishing method until it appears,
And a sixth step of removing the insulating film. 8. The ion implantation of nitrogen in the third step has an acceleration energy of 15 to 30 keV and a dose of 1
8. The method for manufacturing a semiconductor device according to claim 7, wherein the method is performed at a rate of from x10 < ¹⁴ > to 1 * 10 < ¹⁵ >. 9. The method according to claim 7, wherein the first and third insulating films are silicon oxide films, and the second insulating film is a silicon nitride film. 10. A first step of forming first and second insulating film layers on a surface of a semiconductor substrate, and a second step of forming a trench extending from the insulating film layer to the semiconductor substrate after the first step. And then a third step of thermally oxynitriding the entire substrate, a fourth step of embedding a third insulating film in the trench, and then a third step until the second insulating film appears on the surface. 3. A method of manufacturing a semiconductor device, comprising: a fifth step of flattening the surface of an insulating film by a mechanical polishing method, and a sixth step of peeling off the second and first insulating films. . 11. The thermal oxynitriding process in the third step is performed in a NO or N ₂ O atmosphere at a substrate temperature of 75 ° C.
2. The method according to claim 1, wherein the heating is performed at 0 to 950.degree.
0. A method for manufacturing a semiconductor device according to item 0. 12. The method according to claim 11, wherein the first and third insulating films are silicon oxide films, and the second insulating film is a silicon nitride film. 13. A first step of forming first and second insulating film layers on a surface of a semiconductor substrate, and a second step of forming a trench extending from the insulating film layer to the semiconductor substrate after the first step. A third step of nitriding the entire substrate, followed by a fourth step of oxidizing the entire substrate,
A fifth step of embedding a third insulating film in the trench, and then a sixth step of planarizing the surface of the third insulating film by a mechanical polishing method until the second insulating film appears on the surface; And a seventh step of peeling off the second and first insulating films. 14. A method according to claim 3, wherein the nitriding step in the third step is performed in a nitrogen atmosphere or an NH ₃ atmosphere, and the substrate temperature at that time is 900 to 1050 ° C. Item 14. The method for manufacturing a semiconductor device according to item 13. 15. An oxidation treatment step after the nitridation treatment in the fourth step is performed in an oxidizing atmosphere such as oxygen, water vapor, or oxygen diluted with hydrogen, and the substrate temperature at that time is 750 to 950. 14. The method for manufacturing a semiconductor device according to claim 13, wherein the method is performed at a temperature of ° C. 16. The method according to claim 13, wherein the first and third insulating films are silicon oxide films, and the second insulating film is a silicon nitride film.