JP3064561B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device (hereinafter referred to as "dynamic RAM"), and more particularly, to a connection between a sense amplifier and an internal data line.

[0002]

2. Description of the Related Art A typical example of a conventional sense amplifier for a dynamic RAM of this type is shown in FIGS. Reference numeral 1 denotes a sense amplifier, and four transistors Q61, Q62, Q71, Q
It uses a flip-flop composed of 72. D
L and D (overline) are digit line pairs, 3 and 4 are dynamic memory cells, WL1 and WL2 are word lines, I / O and I
/ O (over line) is an internal data line, φSEP and φSEN are sense amplifier activation signals, φY is a column selection signal, Q11 and Q12
Is a transfer transistor of a column selector composed of N-channel MOS transistors.

FIGS. 7 and 8 are signal waveform diagrams showing the operation of the conventional example. The operation will be described below with reference to FIGS. Assuming that VCC is a power supply voltage, a digit line pair D, DL
The state before and after the operation of the (overline) is at 1/2 VCC level, and the internal data line pair I / O, I / O (overline) is at VCC level. An actual semiconductor memory device includes a plurality of sense amplifiers 1 shown in FIG. First, the read operation will be described. FIG. 7 shows a signal waveform diagram of each part during the read operation. Now, at time t1, the word line WL1 changes from the low level to the high level, and the data of the memory cell is transferred from the selected memory cell 3 to the digit line DL. Assuming that the capacity of the digit line DL is CD and the capacity of the memory cell is Cs,
Normally, CD / Cs is about 10, and assuming that the memory cell 3 contains a high-level data bit (close to VCC), the level of the digit line DL is 1/1 of the voltage before operation by a slight voltage corresponding to CD / Cs. When the memory cell 3 contains a low-level data bit (a level close to 0 V), the voltage slightly drops below 1/2 VCC. The level of the other digit line DL (over line) connected to the sense amplifier 1 remains at 1/2 VCC, and the level of the digit line DL (over line) is used as a reference, and the sense amplifier 1 uses the digit line pair DL, It amplifies a slight voltage difference of DL (over line).

In the operation of the sense amplifier 1, first, the activation signal φSEN is changed from 1 / VCC to 0V (time t2), and amplification is performed by a flip-flop constituted by N-channel MOS transistors Q61 and Q62. At this time, it is necessary that a sufficient time has passed since the word line WL1 became high level and a sufficient voltage difference has occurred between the digit lines DL and DL (overhead line). FIG. 7 shows a digit line on the lower side of the voltage level of one of digit line pairs DL and DL (over line).
Then, as φ (SEN) decreases to DL (over line) to 0V, it decreases.

After that, the other digit line, DL (overhead line) in FIG. 7, turns the activation signal φSEP to 1/2 V at time t3.
When the level is changed from CC to a high level (VCC), the flip-flop constituted by the P-channel MOS transistors Q71 and Q72 is activated and rises to VCC. Thus, amplification is performed by the sense amplifier 1. A similar operation is performed in other plurality of sense amplifiers in the semiconductor memory device.

The amplified data is obtained by changing the specific column selection signal φY from 0V to a high level (VCC or more).
Turn on the transfer transistors Q11 and Q12,
The amplified data is transferred to internal data lines I / O, I / O (overline), which are amplified by an internal data amplifier and output to the outside.

Next, a write operation will be described with reference to FIG. As in the case of reading, the memory cell is selected by setting the word line WL1 to the high level at time t11. The word line WL1 selects the memory cell 3. The externally input data is written to the internal data line I /
Transfer to O, I / O (over line). Here, the internal data line I / O is set to 0 V, and the internal data line I / O (overhead line) is set to VCC.
In this case, the reading operation is performed in the reverse order. Therefore, by setting the column selection signal φY to a high level, the transfer transistors Q11 and Q12 are turned on (time t12), and the data on the internal data lines I / O and I / O (overline) are converted into digit lines DL and DL. (Over line), and writes data to the selected memory cell 3.

At this time, in order to supply the memory cell 3 with a sufficiently high level, especially the VCC level, the word line WL1
Must be higher than VCC (VCC + VT or higher), and the column selection signal φY must be higher than VCC. In addition, in order to ensure consistency between read and write, even during a write operation, a read operation is performed once and then a write is performed.

[0009]

In this conventional semiconductor memory device, there is a problem that the capacity of the digit line is large and the transistor size of the sense amplifier must be increased in order to increase the speed of the sense amplifier. .

At the time of reading, there is a problem that the column selection internal signal must be activated after the sense amplifier has completed the amplification operation, and the operation time is long.

[0011]

The gist of the present invention is to provide a plurality of memory cells, a pair of internal data lines for data input / output, a pair of digit lines connected to the memory cells, and A column selection circuit provided between the line pair and the internal data line pair; and a digit section connected to the first section connected to the memory cell and a second section connected to the column selection circuit and the sense amplifier. A transfer gate connected between the first section and the second section; and the column selection circuit is gate-controlled in the second section and has a voltage difference on the internal data line pair. In a semiconductor memory device including a pair of first transfer transistors for generating the first transfer transistor and an activation transistor for activating the first transfer transistor in response to a column read selection signal, another sense amplifier is also provided in the first section. And the above column selection circuit Internal data in response to the ram write select signal - to transfer a voltage difference on the data line pair in the first section a pair of second transfer gates - is further comprising a phototransistor.

[0012]

When data is read, data read from the memory cell is transmitted from the first section to the second section, and when the first transfer transistor is activated,
The voltage difference in the second section is transmitted to the internal data line pair.

[0013]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a dynamic RA according to an embodiment of the present invention.
FIG. 4 is a circuit diagram showing M. 1 and 2 are sense amplifiers,
Each of the sense amplifiers 1 and 2 has the same configuration as the conventional example shown in FIG. The sense amplifier 2 has a plurality of memory cells 3, 4
Are connected to a digit line pair DL, DL (overhead line), and internal data lines I / O,
Digit line pair D connected to I / O (over-line) connection
LR, DLR (over line) are connected. Digit pair DL, DL (over line) and digit line pair DLR, DLR
N-channel MOS transistors Q31 and Q32 to which a digit line latch signal φTG has been input are connected to the gate electrode between them (over line). The column selection circuit 100 has an internal data line pair I / O, I / O (over line), a drain electrode connected to a gate electrode and a DLR, DLR (over line) connected thereto.
The source electrodes of the channel MOS transistors Q41 and Q42, the source electrodes of the N-channel MOS transistors Q41 and Q42 are drain electrodes, the source electrode is a ground power supply, and the gate electrodes of the N-channel MOS transistors Q51 to which the column read selection signal φYR are input. When reading data from the memory cells 3 and 4, the digit line pair DLR, DLR (over-line), the internal data line pair and I / O, I / O (over-line) are directly connected. It has a structure that does not connect. The column selection circuit 100 further includes N-channel MOS transistors Q21 and Q22. When writing, the internal data line pair I / O, I / O (overline) and the digit line pair DL, DL (overline) are connected. It has a direct connection structure.

FIG. 4 is a waveform diagram showing the internal signal waveform of the present embodiment during a read operation, FIG. 5 is a write operation, and FIG. 6 is a read / write operation (read-modify-write operation). . The operation of the embodiment will be described below with reference to these drawings.

First, in the read operation shown in FIG. 4, when the word line WL1 is selectively activated (high level) at time t21, the data in the memory cell 3 is transmitted to the digit line pair DL, DL (over line) and DLR, DLR. (Overline).
At this time, the digit line latch signal φTG is at a high level of VCC + VT or more, and the digit lines DL and DLR are connected to the digit lines DL (over line) and DLR (over line) with sufficiently low resistance. When a sufficient difference voltage is generated between the digit line pair DL, DL (over line) and DLR, DLR (over line), the digit line latch signal φTG is changed from high level to 0V.
(Time t21), the digit line pair DL, DL (overline) is separated from DLR, DLR (overline), the sense amplifier 1 is activated, and the potential difference between the digit line pair DLR, DLR (overline) is reduced. Amplify. Since sense amplifier 1 is separated from digit line pairs DL and DL (overhead lines) connected to a plurality of memory cells 3 and 4, digit line pairs DLR and D
The parasitic capacitance of LR (over-line) is small, and the digit line pair DL
Amplification of the potential difference between R and DLR (over line) becomes faster. Here, digit lines DL, DL (overhead line), DLR,
It is assumed that the state before and after the operation of the DLR (overline) and the internal data line pair I / O, I / O (overline) is at 1/2 VCC level.

As described above, digit line pair DLR, DLR
(Overhaul line) and I / O, I / O (Overhaul line)
Since they are connected by the channel MOS transistors Q41 and Q42 and are not electrically connected directly, the column read selection signal φYR is set to a high level before the activation of the sense amplifier 1, and the digit line pairs DLR and DLR (over-line) And data can be transmitted to the internal data line pair I / O, I / O (overhead line).
After the difference potential on the R and DLR (over line) is sufficiently amplified, the column read selection signal φYR is activated (time t2
3). A column read select signal φYR receives a signal from a column decoder (not shown) and selectively connects a specific digit line pair to an internal data line pair I / O, I / O (overline) only at the time of reading. Signal. When the column read selection signal φYR goes high, the N-channel MOS
Transistors Q51 and Q52 are turned on, and N-channel MOS transistors Q41 and Q42 are connected to digit line pair DL.
The voltage on the internal data line pair I / O, I / O (overline) is determined in response to the difference voltage between R and DLR (overline). Among the digit line pairs DLR, DLR (over line), the internal data line pair I / O, I / O (over line) to which the high level side is connected becomes low level. In FIG. 4, since the digit line DLR is at a high level and the digit line DLR (overhead line) is at a low level,
The internal data line I / O (overline) is low. Thereafter, the read data is stored in the internal data line pair I /
Amplified by a data line amplifier connected to O, I / O (over line), the internal data line pair I / O, I / O (over line)
CC, up to the level of 0V.

Note that a current amplification type amplifier is connected to the internal data line pair I / O, I / O (over line), and the current of the internal data line pair I / O, I / O (over line) is changed. When the data is amplified, it is not necessary to change the internal data line pair I / O, I / O (overline) to the level of VCC / 0 V, and the data of the data line pair can be amplified at a higher speed. It is also possible to activate the column read selection signal φYR at the same time as the activation of the word line.

Internal data line pair I / O, I / O (overline)
The above data is output to the outside via the data line amplifier and the data output buffer, and the read operation is completed.

On the other hand, the digit line pair DL, DL (over line) separated by the digit line latch signal φTG becoming low level activates the sense amplifier 2 slightly later than the activation of the sense amplifier 1. To amplify the difference voltage to make the voltage of the digit line pair DL, DL (over line) up to VCC, 0 V, and resupply a sufficient voltage level to the memory cell.

Activation of sense amplifier 1 and sense amplifier 2
May be activated at the same time, and the sense amplifier 1 is used for the read operation. Therefore, even if the amplification by the sense amplifier 2 is slightly delayed, it does not greatly affect the high-speed operation of the semiconductor memory device.

Next, the write operation will be described with reference to FIG. At the time of the write operation, the column read select signal φYR is set to the low level, the column write select signal φYW is set to the high level, and the data input from the outside is transferred from the internal data lines I / O, I / O (overline) to the N-channel MOS transistor Q21. , Q22 via a digit line pair DL, DL
(Overline) and write to the memory cell selected by activating the word line.

However, in this type of semiconductor memory device, a plurality of digit line pairs can be connected to the internal data line pair I / O, I / O (overline), and when the word line is activated. There are memory cells selected at the same time by the number of digit line pairs. Therefore, for a selected memory cell other than the memory cell to which data is to be written, a read operation, particularly an operation of amplifying by the sense amplifier 2 and then writing data again, is necessary. Therefore, it is performed at the time of read operation as well as write operation. Digit line pair DLR, DLR (over line) and digit line pair DL, D by setting digit line latch signal φTG to low level.
L (over line) is activated, and the sense amplifiers 1 and 2 are activated. In particular, when the data written in the memory cell is different from the data to be written, the internal data line pair I
Since / O, I / O (over line) and digit line pair DL, DL (over line) have opposite phases, digit line pair DL, DL (over line) is connected to internal data line pair I / O, I / O. There is a possibility that the sense amplifier which is activated before the state becomes the same as O (over line) becomes an obstacle and it takes time. However, in this embodiment, by setting the digit line latch signal φTG to low level, the digit lines DLR, DLR (over line) and the digit lines DL, DL (over line) are separated, and the internal data line pair I / O, Since only the sense amplifier 2 is required from the I / O (overline) side, the sense amplifier 2 is not required to have a high amplification speed, so that the transistor size can be reduced. Can also be reduced.

FIG. 6 shows the movement of each signal of this embodiment when the read / write operation is performed in the same cycle. In the conventional example, both the read and write operations are supported by the column selection signal φY, whereas in the present embodiment, the read operation is φYR, the write operation is φYW, and the internal data line pair I / O, I / O is used. (Over line) and digit line DLR, DL
Since R (over line) or DL, DL (over line) is connected, when reading is completed and writing is started, the column read selection signal φYR is changed from high level to low level,
It is necessary to switch the column write selection signal φYW from low level to high level. The read operation and the write operation shown in FIG. 6 are the same as the respective operations of the above-described embodiment, and the detailed description will be omitted.

[0024]

According to the present invention, the column selection circuit controls the gate of the first transfer gate transistor based on the voltage difference in the second section to generate a voltage difference on the internal data line pair. Before sufficiently amplifying the voltage difference in the second section, the first transfer gate transistor can be activated, and the effect of increasing the speed can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional example.

FIG. 3 is a circuit diagram showing a sense amplifier.

FIG. 4 is a waveform chart showing a read operation of one embodiment.

FIG. 5 is a waveform chart showing a write operation of one embodiment.

FIG. 6 is a waveform diagram showing a read / write cycle of one embodiment.

FIG. 7 is a waveform diagram showing a read operation of a conventional example.

FIG. 8 is a waveform chart showing a write operation of a conventional example.

[Explanation of symbols]

1, 2 sense amplifier 3, 4 memory cell 100 column selection circuit φSEN, φSEP, φSEN1, φSEP1 Sense amplifier drive signal I / O, I / O (overline) Internal data line DL, DL (overline), DLR, DLR (Over line) Digit line WL1, WL2 Word line φY Column selection internal signal φYR Column read selection signal φYW Column write selection signal φTG Digit line data latch signal Q11, Q12, Q31, Q32, Q61, Q42 N channel M
OS transistor Q71, Q72 P-channel MOS transistor Q41, Q42 N-channel MOS transistor (first transfer gate transistor) Q51, Q52 N-channel MOS transistor (activation transistor) Q21, Q22 N-channel MOS transistor (second transfer gate transistor)

Claims (1)

(57) [Claims] A plurality of memory cells; a pair of internal data lines for inputting and outputting data; a pair of digit lines connected to the memory cells; a pair of digit lines and a pair of internal data lines; And a column selection circuit provided between the first and second sections by dividing the digit line pair into a first section connected to the memory cell and a second section connected to the column selection circuit and the sense amplifier. And a transfer gate connected between the first transfer transistor and a pair of first transfer transistors which are gate-controlled in the second section and generate a voltage difference on the internal data line pair. And an activation transistor activating a first transfer transistor in response to a column read selection signal, wherein another sense amplifier is also connected to the first section, and the column selection circuit performs column writing. In response to the selection signal A semiconductor memory device further comprising a pair of second transfer gate transistors for transferring a voltage difference on a pair of internal data lines to a first section.