JP2962586B2 - Semiconductor device, method of manufacturing the same, and joined body used therefor - Google Patents
Semiconductor device, method of manufacturing the same, and joined body used thereforInfo
- Publication number
- JP2962586B2 JP2962586B2 JP6398891A JP6398891A JP2962586B2 JP 2962586 B2 JP2962586 B2 JP 2962586B2 JP 6398891 A JP6398891 A JP 6398891A JP 6398891 A JP6398891 A JP 6398891A JP 2962586 B2 JP2962586 B2 JP 2962586B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- lead frame
- conductor pattern
- pattern portion
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置とその製造方
法及び半導体装置の製造に用いる接合体に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a method for manufacturing the same, and a joined body used for manufacturing the semiconductor device.
【０００２】[0002]
【従来の技術】半導体チップを搭載するリードフレーム
は半導体チップの高集積化とともに、ますます高密度化
が進んでいる。プレス加工あるいはエッチング加工によ
ってリードフレームを製造する場合は、使用するリード
フレームの材厚によってリードフレームピッチの加工限
界が規定されるから、ファインピッチのリードフレーム
を製造する場合にはより薄厚の材料を使わなければなら
ない。最近では0.1mm 程度の材厚の材料も用いられるよ
うになっている。2. Description of the Related Art Lead frames on which semiconductor chips are mounted are becoming more and more dense as semiconductor chips become more highly integrated. When manufacturing a lead frame by pressing or etching, the processing limit of the lead frame pitch is determined by the thickness of the lead frame used.When manufacturing a fine pitch lead frame, a thinner material is used. Must use. Recently, materials with a thickness of about 0.1 mm have been used.
【０００３】ところで、材厚が薄くなるとそれに伴って
リードの強度が低下するから、加工後の取り扱い時にリ
ードの変形が生じたりしやすくなるといった問題点があ
る。そこで、ファインピッチを可能とするため薄厚の導
体材料として銅箔を用い、この銅箔を剥離性の接着剤で
キャリアフィルムに貼着し、その後、エッチング加工し
てリードを形成している。[0003] By the way, when the material thickness is reduced, the strength of the lead is reduced, which causes a problem that the lead is easily deformed during handling after processing. Therefore, a copper foil is used as a thin conductor material to enable fine pitch, and this copper foil is adhered to a carrier film with a peelable adhesive, and then etched to form leads.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、上記の
従来方法では薄厚の銅箔をキャリアフィルムで支持した
接合体に対してエッチング等の処理を施さなければなら
ず、ワイヤボンディング性を向上させるためにボンディ
ング部にめっきを施したりする場合もこの接合体に対し
てめっき処理をしなければならず、製造工程が厄介であ
るという問題点がある。上記のキャリアフィルム上に導
体パターンを形成した接合体は、図１(e) に示すような
半導体装置（樹脂封止部２の半導体チップ３０搭載側の
外面に接続端子４をグリッド状に配置したもの）の製造
に利用できるが、このような半導体装置を製造する場合
も、樹脂封止を行った後、キャリアフィルムで接続端子
を形成する部位をエッチングし、次に、接続端子を形成
する部位にめっき処理を施したりしなければならず、製
造工程がやはり厄介であるという問題点があった。However, in the above-mentioned conventional method, a process such as etching must be applied to a joined body in which a thin copper foil is supported by a carrier film. Even when plating is performed on the bonding portion, plating must be performed on the joined body, and there is a problem that the manufacturing process is troublesome. The joined body in which the conductor pattern is formed on the carrier film is a semiconductor device (connection terminals 4 are arranged in a grid shape on the outer surface of the resin sealing portion 2 on the semiconductor chip 30 mounting side) as shown in FIG. In the case where such a semiconductor device is manufactured , after sealing with resin , a portion for forming a connection terminal is etched with a carrier film, and then a portion for forming a connection terminal. And the plating process must be performed, and the manufacturing process is still troublesome.
【０００５】なお、上記の図１(e) に示す半導体装置
は、半導体チップ３０を樹脂封止した樹脂封止部２の片
面側に接続端子４を配置したものであり、このような樹
脂封止部２の外面に接続端子４を設けた半導体装置は高
密度実装にきわめて有効である。本発明はこのような樹
脂封止部に導体パターンが埋没して封止され、樹脂封止
部の外面側に接続端子が配置される形態の半導体装置及
び半導体装置の製造方法等に関するものであり、リード
パターンが高密度に形成でき、かつ、上記の半導体装置
の製造にあたって製造が容易にでき、それによって製造
コストを効果的に下げることができる半導体装置とその
製造方法及び半導体装置の製造に好適に用いられる接合
体を提供することを目的とする。In the semiconductor device shown in FIG. 1E, the semiconductor chip 30 is sealed with a resin.
The connection terminals 4 are arranged on the surface side.
The semiconductor device in which the connection terminals 4 are provided on the outer surface of the grease sealing portion 2 is extremely effective for high-density mounting. The present invention relates to a semiconductor device in which a conductor pattern is embedded and sealed in such a resin sealing portion, and connection terminals are arranged on an outer surface side of the resin sealing portion.
And a process for producing such a fine semiconductor device, the lead pattern can be formed at a high density, and can be produced when the easy production of the semiconductor device, a semiconductor device can thereby lowering the production cost effectively And method for manufacturing the same and bonding preferably used for manufacturing a semiconductor device
The purpose is to provide the body .
【０００６】[0006]
【課題を解決するための手段】本発明は上記目的を達成
するため次の構成を備える。すなわち、半導体装置にお
いて、リードフレームに設けられた導体パターン部と半
導体チップとが電気的に接続され、前記リードフレーム
の半導体チップが搭載された片面側が、前記半導体チッ
プおよび前記導体パターン部を含めて樹脂封止され、該
樹脂封止された封止範囲に対応する前記リードフレーム
の他面側が、絶縁性フィルムにより被覆され、該絶縁性
フィルムに前記導体パターン部の接続端子を形成する部
位が底面に露出する透孔が形成され、該透孔内に、導体
パターン部と電気的に接続して先端が前記絶縁性フィル
ムの表面から突出する接続端子が形成されていることを
特徴とする。また、リードフレームに設けられた導体パ
ターン部と半導体チップとが電気的に接続され、前記リ
ードフレームの半導体チップが搭載された片面側が、前
記半導体チップおよび前記導体パターン部を含めて樹脂
封止され、該樹脂封止された封止範囲に対応する前記リ
ードフレームの他面側が、保護コーティングにより被覆
され、該保護コーティングに前記導体パターン部の接続
端子を形成する部位が底面に露出する透孔が形成され、
該透孔内に、前記導体パターン部と電気的に接続して先
端が前記保護コーティングの表面から突出する接続端子
が形成されていることを特徴とする。また、前記接続端
子がはんだバンプであることを特徴とする。また、半導
体装置の製造方法において、パッド部および導体パター
ン部が設けられたリードフレームの前記導体パターン部
の外部接続用の接続端子を形成する部位にめっきを施
し、該リードフレームの半導体チップが搭載されて樹脂
封止される片面側とは反対側の他面側に、前記接続端子
を形成する部位にあらかじめ透孔を形成した絶縁性フィ
ルムを、少なくとも前記片面側の樹脂封止される範囲と
対応する範囲にわたり貼着してリードフレームと絶縁性
フィルムとの接合体を形成し、該接合体の前記パッド部
に半導体チップを搭載して該半導体チップと前記導体パ
ターン部とを電気的に接続し、前記接合体の半導体チッ
プを搭載した片面側を前記半導体チップおよび前記導体
パターン部を含めて樹脂封止した後、前記絶縁性フィル
ムを貼着した他面側の前記導体パターン部が底面に露出
する前記透孔内に、前記導体パターン部と電気的に接続
して先端が前記絶縁性フィルムの表面から突出する接続
端子を形成することを特徴とする。また、パッド部およ
び導体パターン部が設けられたリードフレームの前記導
体パターン部の外部接続用の接続端子を形成する部位に
めっきを施し、該リードフレームの半導体チップが搭載
されて樹脂封止される片面側とは反対側の他面側に、少
なくとも前記片面側の樹脂封止される範囲と対応する範
囲にわたり絶縁性フィルムを貼着してリードフレームと
絶縁性フィルムとの接合体を形成し、該接合体の前記パ
ッド部に半導体チップを搭載して該半導体チップと前記
導体パターン部とを電気的に接続し、前記接合体の半導
体チップを搭載した片面側を前記半導体チップおよび前
記導体パターン部を含めて樹脂封止した後、前記絶縁性
フィルムに導体パターン部の接続端子を形成する部位が
底面に露出する透孔を形成し、該透孔内に、前記導体パ
ターン部と電気的に接続して先端が前記絶縁性フィルム
の表面から突出する接続端子を形成することを特徴とす
る。また、パッド部および導体パターン部が設けられた
リードフレームの前記導体パターン部の外部接続用の接
続端子を形成する部位にめっきを施し、該リードフレー
ムの半導体チップが搭載されて樹脂封止される片面側と
は反対側の他面側に、少なくとも前記片面側の樹脂封止
される範囲と対応する範囲にわたり電気的絶縁性を有す
る転写フィルムを貼着してリードフレームと転写フィル
ムとの接合体を形成し、該接合体の前記パッド部に半導
体チップを搭載して該半導体チップと前記導体パターン
部とを電気的に接続し、前記接合体の半導体チップを搭
載した片面側を前記半導体チップおよび前記導体パター
ン部を含めて樹脂封止し、前記転写フィルムを剥離除去
した後、前記リードフレームの転写フィルムが貼着され
ていた範囲にわたり、導体パターン部の接続端子を形成
する部位を除き保護コーティングを施し、該保護コーテ
ィングを施したリードフレームの他面側に露出した前記
導体パターン部の接続端子を形成する部位に、前記導体
パターン部と電気的に接続して先端が前記保護コーティ
ングの表面から突出する接続端子を形成することを特徴
とする。また、パッド部および導体パターン部が設けら
れたリードフレームの前記導体 パターン部のアウターリ
ードにめっきを施し、該リードフレームの半導体チップ
が搭載されて樹脂封止される片面側とは反対側の他面側
に、少なくとも前記片面側の樹脂封止される範囲と対応
する範囲にわたり電気的絶縁性を有する転写フィルムを
貼着してリードフレームと転写フィルムとの接合体を形
成し、該接合体の前記パッド部に半導体チップを搭載し
て該半導体チップと前記導体パターン部とを電気的に接
続し、前記接合体の半導体チップを搭載した片面側を、
樹脂封止される範囲の外方に前記アウターリードを延出
させて前記半導体チップおよび前記導体パターン部を含
めて樹脂封止し、前記転写フィルムを剥離除去した後、
樹脂封止された範囲と対応するリードフレームの他面側
の範囲に保護コーティングを施すことを特徴とする。ま
た、リードフレームと絶縁性フィルムとの接合体におい
て、パッド部および導体パターン部が設けられるととも
に、前記導体パターン部の外部接続用の接続端子を形成
する部位にめっきが施されたリードフレームの、半導体
チップが搭載されて樹脂封止される片面側とは反対側の
他面側に、少なくとも前記片面側の樹脂封止される範囲
と対応する範囲にわたり、前記導体パターン部の接続端
子を形成する部位が底面に露出する透孔が形成された絶
縁性フィルムが貼着されていることを特徴とする。The present invention has the following arrangement to achieve the above object. In other words, semiconductor devices
There are, the conductor pattern portion and the semiconductor chip in the lead frame are electrically connected, one side of the semiconductor chip is mounted in the lead frame, tree Aburafutome including the semiconductor chip and the conductor pattern portions is, the
The other surface side of the lead frame corresponding to the resin-sealed sealing range, are covered by the insulation film, forming a connecting terminal of the conductive pattern portions in the insulating film parts
A through hole is formed at the bottom surface, and a conductor is formed in the through hole .
It is electrically connected to the pattern part and the tip is
Connection terminals projecting from the surface of the beam is formed, characterized in Tei Rukoto. Further, the conductor pattern portion and the semiconductor chip in the lead frame are electrically connected, one side of the semiconductor chip is mounted in the lead frame, tree Aburafutome including the semiconductor chip and the conductor pattern portions is, the other side of the lead frame corresponding to the sealing range hermetically the resin sealing is coated by protection coating, connection of the conductor pattern portion to the protective coating
A through hole is formed that exposes the terminal forming part on the bottom ,
Electrically connected to the conductor pattern portion in the through hole ,
End and wherein Tei Rukoto connection terminal is formed to protrude from the surface of the protective coating. Further, the connection terminal is a solder bump. Further, in the method for manufacturing a semiconductor device, the conductor pattern portion of the lead frame provided with the pad portion and the conductor pattern portion
Plating on the area where the connection terminals for external connection
And, the lead frame of the semiconductor chip is mounted resins
On the other side opposite to the one side of Ru sealed, the connecting terminal
Insulating filter with through holes
The Lum, a range that is a resin sealing of at least the one side
And rehearsal wear cotton in the corresponding range to form a joined body of the insulating film and the lead frame, electrically and said conductive pattern section with the semiconductor chip by mounting a semiconductor chip to the pad portion of the conjugate connected to the after equipped with the one surface of the bonded body of the semiconductor chip was sealed the semiconductor chip and the resin sealing including the conductor pattern portions, wherein the insulating film is adhered to the other side the conductor pattern portions Is exposed on the bottom
Electrically connected to the conductor pattern portion in the through hole
And forming a connection terminal whose tip protrudes from the surface of the insulating film . Also, the pad and
And a lead frame provided with a conductive pattern portion.
In the part of the body pattern part where the connection terminal for external connection is formed
Plating alms, range <br/> the one side of the semiconductor chip of the lead frame is sealed is mounted with resin on the other surface of the opposite side, corresponding to the range to be resin sealing of at least the one side A bonded body of the lead frame and the insulating film is formed by attaching an insulating film over the surroundings, a semiconductor chip is mounted on the pad portion of the bonded body, and the semiconductor chip and the conductive pattern portion are electrically connected to each other. After sealing the semiconductor chip and the conductor pattern portion of one side of the bonded body including the semiconductor chip with the resin ,
The part where the connection terminal of the conductor pattern part is formed on the film
A through hole exposed at the bottom is formed, and the conductor path is formed in the through hole.
It is electrically connected to the turn part and the tip is the insulating film.
Forming connection terminals protruding from the surface of the
You . Also, a contact for external connection of the conductor pattern portion of the lead frame provided with the pad portion and the conductor pattern portion is provided.
Plating is applied to the portion where the connection terminal is to be formed, and the lead frame
At least one surface of the semiconductor chip is mounted on the other surface opposite to the one surface on which the semiconductor chip is mounted and resin-sealed.
Transfer film was bonded wear to form a joined body of the transfer film and the lead frame, the semiconductor by mounting a semiconductor chip to the pad portion of the conjugate having an electrical insulating property over a range corresponding to a range to be After the chip and the conductor pattern portion are electrically connected, one side of the joined body on which the semiconductor chip is mounted is resin-sealed including the semiconductor chip and the conductor pattern portion, and the transfer film is peeled and removed. Forming the connection terminals of the conductor pattern portion over the area where the transfer film of the lead frame was adhered.
The protective coating is applied except for the part to be covered, and the lead coating exposed on the other side of the lead frame to which the protective coating is applied.
A portion of the conductor pattern portion where the connection terminal is to be formed is electrically connected to the conductor pattern portion and the tip is formed of the protective coating.
A connection terminal projecting from a surface of the ring . Further, the outer pattern of the conductor pattern portion of the lead frame provided with the pad portion and the conductor pattern portion is provided.
Plated in over de, on the other side opposite to the one side of the semiconductor chip of the lead frame Ru resin-sealed is mounted, corresponds to the range that is a resin sealing of at least the one side
The transfer film having an electrical insulating property over a range of
Bonded wear to form a joined body of the transfer film and the lead frame, and electrically connecting the said semiconductor chip the conductor pattern portions by mounting a semiconductor chip to the pad portion of the conjugate, the conjugate equipped with a single-sided side of the semiconductor chip,
By extending the outer leads outside the range that is tree Aburafutome resin sealing including the semiconductor chip and the conductive pattern section, after the transfer film was peeled off,
The other side of the lead frame corresponding to the area sealed with resin
And characterized by applying protection coatings in the range of. Further, in the bonding of the insulating film and the lead frame, the pad section and the conductor pattern portion provided Rutotomo
Forming a connection terminal for external connection of the conductor pattern portion
The lead frame plated on site, the range on the other side opposite to the one side where the semiconductor chip is sealed with resin is mounted, which is resin-sealed at least said one side
And the connection end of the conductor pattern portion
An insulating film having a through hole through which a portion for forming a child is exposed on the bottom surface is attached.
【０００７】[0007]
【実施例】以下、本発明の好適な実施例を添付図面に基
づいて詳細に説明する。本発明に係る半導体装置の製造
方法は、半導体チップを接合するパッド部や導体パター
ン部が形成される導体部とこの導体部を支持する電気的
絶縁性を有するキャリアフィルムとをあらかじめ別体で
形成した後、たがいに貼着して樹脂封止等の加工を施す
ことを特徴とする。図１は半導体装置の製造方法の第１
の実施例を示す。本実施例ではまず、図１(a) に示すよ
うに、薄厚の導体材料にエッチング加工あるいはプレス
加工を施して所定パターンを有するリードフレーム１０
を形成すると共に、リードフレーム１０と別体にリード
フレーム１０に貼着するための絶縁性フィルムであるキ
ャリアフィルム２０を形成する。リードフレーム１０に
は半導体チップを接合するためのパッド部１２および導
体パターン部１４等の所定パターンを形成する。また、
リードフレーム１０にはワイヤボンディングの際にボン
ディング部となる部位に金めっき等を施したり、接続端
子としてバンプを形成する部位にめっき等の所要の表面
処理を施す。また、キャリアフィルム２０には接続端子
を形成する部位にあらかじめ透孔２２を形成しておく。DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. A method of manufacturing a semiconductor device according to the present invention is directed to a method of manufacturing a semiconductor device, comprising: a conductor for forming a pad portion and a conductor pattern portion for joining a semiconductor chip ;
It is characterized in that a carrier film having an insulating property is formed as a separate body in advance, and then the two are adhered to each other and subjected to processing such as resin sealing. FIG. 1 shows a first method of manufacturing a semiconductor device.
The following shows an example. In this embodiment, first, as shown in FIG. 1A, a lead frame 10 having a predetermined pattern is formed by etching or pressing a thin conductor material.
And a carrier film 20 that is an insulating film to be attached to the lead frame 10 separately from the lead frame 10. A predetermined pattern such as a pad portion 12 and a conductor pattern portion 14 for joining a semiconductor chip is formed on the lead frame 10. Also,
The lead frame 10 is provided with gold plating or the like at a portion to be a bonding portion at the time of wire bonding, or with a required surface treatment such as plating at a portion where a bump is formed as a connection terminal. In addition, through holes 22 are formed in advance on the carrier film 20 at portions where connection terminals are to be formed.
【０００８】次に、上記のリードフレーム１０とキャリ
アフィルム２０とを位置合わせして接着する（図１(b)
）。この接合体に対し、上記パッド部１２に半導体チ
ップ３０を接合し、ワイヤボンディングによって半導体
チップ３０と導体パターン部１４とを接続する（図１
(c) ）。次いで、半導体チップ３０を樹脂封止する（図
１(d))。このときの樹脂封止は上記の接合体で半導体チ
ップ３０を搭載する片面側のみ樹脂封止するもので、キ
ャリアフィルム２０は樹脂封止部２の外面に露出するよ
うにする。キャリアフィルム２０にはあらかじめ透孔２
２が形成されているから、透孔２２部分の内底面に導体
パターン部１４が露出する。導体パターン部１４の透孔
２２部分にはあらかじめ表面処理が施してあり、そのま
まはんだを盛ることによってバンプ状の接続端子４を形
成することができる（図１(e))。Next, the lead frame 10 and the carrier film 20 are aligned and adhered (FIG. 1B).
). A semiconductor chip 30 is bonded to the pad portion 12 with this bonded body, and the semiconductor chip 30 and the conductor pattern portion 14 are connected by wire bonding (FIG. 1).
(c)). Next, the semiconductor chip 30 is sealed with a resin (FIG.
1 (d)) . The resin sealing at this time is to seal the resin chip only on one side on which the semiconductor chip 30 is mounted with the above-described bonded body, and the carrier film 20 is exposed on the outer surface of the resin sealing portion 2. The carrier film 20 has through holes 2 in advance.
2, the conductor pattern portion 14 is exposed on the inner bottom surface of the through hole 22 portion. The through hole 22 portion of the conductor pattern portion 14 Ri Ah advance surface treatment performed, it is possible to form the bump-like connecting terminal 4 by directly mole solder (FIG. 1 (e)).
【０００９】上記実施例の半導体装置の製造方法は、リ
ードフレーム１０に導体パターン部１４等の所要のパタ
ーンを形成するとともに、必要な表面処理をあらかじめ
施した後にキャリアフィルム２０を貼着するから、後工
程で表面処理を施したりする必要がなく、後工程側での
処理が非常に簡単になるという利点がある。また、リー
ドフレーム１０の製造にあたっては、従来のエッチング
加工等の製造方法やめっき等の表面処理方法がそのまま
利用できるから製造も容易である。そして、リードフレ
ーム１０の取り扱いにおいてはキャリアフィルム２０を
リードフレーム１０に貼着して導体パターン部１４等を
支持することで、より薄厚の導体材料を用いることがで
き導体パターンの高密度化にも有効に対処することがで
きるという利点がある。In the method of manufacturing a semiconductor device according to the above embodiment, the required pattern such as the conductor pattern portion 14 is formed on the lead frame 10 and the carrier film 20 is adhered after performing necessary surface treatment in advance. There is no need to perform a surface treatment in the post-process, and there is an advantage that the process in the post-process is very simple. In manufacturing the lead frame 10, the manufacturing method is easy because conventional manufacturing methods such as etching and surface treatment methods such as plating can be used as they are. When the lead frame 10 is handled, the carrier film 20 is attached to the lead frame 10 to support the conductor pattern portion 14 and the like, so that a thinner conductor material can be used, and the density of the conductor pattern can be increased. There is an advantage that it can be dealt with effectively.
【００１０】上記実施例においては、リードフレーム１
０に貼着するキャリアフィルム２０としてあらかじめ透
孔２２等の加工を施したフィルムを用いたが、リードフ
レーム１０に貼着する際には単にシート状のキャリアフ
ィルムを用い、樹脂封止後にキャリアフィルム２０にエ
ッチング等の処理を施して透孔２２等を形成するように
してもよい。上記例ではキャリアフィルム２０に透孔２
２を形成して透孔２２部分に接続端子としてバンプを形
成したが、外部接続用として導体パターン部１４から樹
脂封止部２の外方にアウターリードを延設するようにし
てもよい。この場合はキャリアフィルム２０に透孔２２
を形成する必要はなく、樹脂封止後にアウターリードの
カットおよびフォーミング加工を行う。図１(a) でのリ
ードフレーム１０を形成する際にアウターリードに所要
の表面処理を施しておくことによって後工程で表面処理
を行う必要がなくなり、そのまま実装可能となる。In the above embodiment, the lead frame 1
As the carrier film 20 to be attached to the lead frame 10, a film which has been subjected to processing such as through-holes 22 is used. However, when the carrier film 20 is attached to the lead frame 10, only a sheet-shaped carrier film is used. 20 may be subjected to a process such as etching to form the through-holes 22 and the like. In the above example, the through holes 2 are formed in the carrier film 20.
2, the bump is formed as a connection terminal at the through hole 22. However, the outer lead may be extended from the conductor pattern portion 14 to the outside of the resin sealing portion 2 for external connection. In this case, through holes 22 are formed in
Need not be formed, and the outer leads are cut and formed after resin sealing. By forming a required surface treatment on the outer leads when forming the lead frame 10 in FIG. 1A, there is no need to perform a surface treatment in a later step, and mounting can be performed as it is.
【００１１】図２は上記の半導体装置の製造方法の他の
実施例として、剥離性の接着剤を塗布した転写フィルム
を用いた製造方法を示す説明図である。本実施例では、
まずリードフレーム１０に前記転写フィルム４０を接着
した接合体を形成する。リードフレーム１０は上記実施
例と同様にパッド部１２および導体パターン部１４を形
成すると共に必要な表面処理を施したものである（図２
(a) ）。次に、この接合体に半導体チップ３０を接合
し、ワイヤボンディングによって半導体チップ３０と導
体パターン部１４とを接続する（図２(b) ）。次いで、
半導体チップ３０を樹脂封止する。この樹脂封止も図２
(c) に示すように片面の樹脂封止である。次に、樹脂封
止部２から上記の転写フィルム４０を剥離除去する。転
写フィルム４０は剥離性接着剤によって接着されている
から簡単に剥離できる。図２(d)は転写フィルム４０を
剥離した状態である。転写フィルム４０を剥離すること
によって導体パターン部１４が露出するから、導体パタ
ーン部１４を保護するための保護コーティング５０を施
す。保護コーティング５０はスクリーン印刷法でソルダ
ーレジストを塗布する方法等が利用できる。バンプで接
続端子を形成する場合は接続端子を形成する部位を除い
て保護コーティング５０を施すようにする。保護コーテ
ィング５０を施したら、はんだバンプ等によって接続端
子４を形成する。図２(e) は保護コーティング５０を施
して接続端子４を形成した状態を示している。FIG. 2 is an explanatory view showing, as another embodiment of the method of manufacturing the above-mentioned semiconductor device, a manufacturing method using a transfer film coated with a peelable adhesive. In this embodiment,
First, a joined body in which the transfer film 40 is adhered to the lead frame 10 is formed. The lead frame 10 has the pad portion 12 and the conductor pattern portion 14 formed thereon and has been subjected to necessary surface treatment as in the above embodiment (FIG. 2).
(a)). Next, the semiconductor chip 30 is joined to the joined body, and the semiconductor chip 30 and the conductor pattern portion 14 are connected by wire bonding (FIG. 2B). Then
The semiconductor chip 30 is sealed with resin. Fig. 2
(c) As shown in FIG. Next, the transfer film 40 is peeled off from the resin sealing portion 2. Since the transfer film 40 is adhered by the peelable adhesive, it can be easily peeled off. FIG. 2D shows a state in which the transfer film 40 has been peeled off. Since the conductive pattern portion 14 is exposed by peeling the transfer film 40, a protective coating 50 for protecting the conductive pattern portion 14 is applied. For the protective coating 50, a method of applying a solder resist by a screen printing method or the like can be used. When the connection terminals are formed by bumps, the protective coating 50 is applied except for portions where the connection terminals are formed. After the protective coating 50 is applied, the connection terminals 4 are formed by solder bumps or the like. FIG. 2E shows a state in which the connection terminal 4 is formed by applying the protective coating 50.
【００１２】本実施例の半導体装置の製造方法の場合も
転写フィルム４０に接着するリードフレーム１０に導体
パターン部１４等の所要パターンを形成するとともに、
あらかじめ所要の表面処理を施すから、後工程において
リードの表面処理等を行う必要がなくなり、製造工程に
おける困難さが解消でき容易に製造することが可能にな
る。また、これらの表面処理等は従来のリードフレーム
の製造工程において従来行っている処理内容であり、従
来方法がそのまま利用できて確実な製造が可能であり、
かつ製造コストを低減させることができる。In the method of manufacturing a semiconductor device according to the present embodiment, a required pattern such as the conductor pattern portion 14 is formed on the lead frame 10 adhered to the transfer film 40.
Since the required surface treatment is performed in advance, it is not necessary to perform lead surface treatment or the like in a later process, and the difficulty in the manufacturing process can be eliminated and the manufacturing can be easily performed. In addition, these surface treatments and the like are the processing contents conventionally performed in the conventional lead frame manufacturing process, and the conventional method can be used as it is, and reliable manufacturing is possible.
In addition, manufacturing costs can be reduced.
【００１３】なお、上記実施例においては半導体チップ
３０と導体パターン部１４とはワイヤボンディングによ
って接続したが、半導体チップ３０の接続方法はとくに
問わない。バンプによって半導体チップをじかに導体パ
ターン部に接続する方法であってもかまわない。また、
外部接続用の接続端子の配置なども装置に応じて適宜設
定することができる。In the above embodiment, the semiconductor chip 30 and the conductor pattern portion 14 are connected by wire bonding, but the connection method of the semiconductor chip 30 is not particularly limited. A method in which the semiconductor chip is directly connected to the conductor pattern portion by a bump may be used. Also,
The arrangement of connection terminals for external connection and the like can also be appropriately set according to the device.
【００１４】[0014]
【発明の効果】本発明に係る半導体装置とその製造方法
によれば、上述したように、高密度にリードパターンを
形成することができて多ピン化に好適に対応することが
できるとともに、従来のリードフレームの製造方法を利
用することにより製造コストを下げることができる。ま
た、絶縁性フィルムまたは保護コーティングに設けた透
孔の底面に導体パターン部が露出することから、導体パ
ターン部に直接、外部接続用の接続端子を接合して導体
パターン部と接続端子とを電気的に接続することが可能
になる。また、本発明に係る接合体を使用することによ
って、樹脂封止部の範囲内に接続端子を設けた半導体装
置を容易に製造することができる等の著効を奏する。According the present invention a semiconductor device according to and its manufacturing method, as described above, it is possible to suitably correspond to the high density multi-pin structure and it is possible to form the lead pattern, the conventional interest a method of manufacturing a lead frame
By using this, the manufacturing cost can be reduced. Ma
The transparent film provided on the insulating film or protective coating.
Since the conductor pattern is exposed at the bottom of the hole, the conductor pattern is exposed.
Connect the connection terminal for external connection directly to the turn
It is possible to electrically connect the pattern section and connection terminals
become. Further, by using the joined body according to the present invention, it is possible to easily produce a semiconductor device provided with a connection terminal within a range of a resin sealing portion, and the like, and the remarkable effect is obtained.
【図１】半導体装置の製造方法の一実施例を示す説明図
である。FIG. 1 is an explanatory view showing one embodiment of a method for manufacturing a semiconductor device.
【図２】半導体装置の製造方法の他の実施例を示す説明
図である。FIG. 2 is an explanatory view showing another embodiment of a method of manufacturing a semiconductor device.
２ 樹脂封止部 ４ 接続端子 １０ リードフレーム １２ パッド部 １４ 導体パターン部 ２０ キャリアフィルム ２２ 透孔 ３０ 半導体チップ ４０ 転写フィルム ５０ 保護コーティング 2 Resin sealing portion 4 Connection terminal 10 Lead frame 12 Pad portion 14 Conductive pattern portion 20 Carrier film 22 Through hole 30 Semiconductor chip 40 Transfer film 50 Protective coating
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭63−146453（ＪＰ，Ａ) 特開 平３−11641（ＪＰ，Ａ) 特開 平３−99456（ＪＰ，Ａ) 特開 昭63−280477（ＪＰ，Ａ) 特開 平３−94430（ＪＰ，Ａ) 実開 昭62−78751（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60 301 H01L 23/50 ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-63-146453 (JP, A) JP-A-3-11641 (JP, A) JP-A-3-99456 (JP, A) JP-A-63-146453 280477 (JP, A) JP-A-3-94430 (JP, A) Japanese Utility Model Application Sho 62-78751 (JP, U) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 21/60 301 H01L 23/50
Claims (8)
ン部と半導体チップとが電気的に接続され、前記リード
フレームの半導体チップが搭載された片面側が、前記半
導体チップおよび前記導体パターン部を含めて樹脂封止
され、該樹脂封止された封止範囲に対応する 前記リードフレー
ムの他面側が、絶縁性フィルムにより被覆され、 該絶縁性フィルムに前記導体パターン部の接続端子を形
成する部位が底面に露出する透孔が形成され、 該透孔内に、導体パターン部と電気的に接続して先端が
前記絶縁性フィルムの表面から突出する接続端子が形成
されていることを特徴とする半導体装置。A conductive pattern portion provided on the lead frame and the semiconductor chip are electrically connected to each other, and one side of the lead frame on which the semiconductor chip is mounted includes a tree including the semiconductor chip and the conductive pattern portion. locked Aburafu, the other surface side of the lead frame corresponding to the sealing range hermetically the resin sealing is coated by insulation film, form the connection terminals of the conductive pattern portions in the insulating film
A through hole is formed so that a formed part is exposed at the bottom surface. In the through hole , the tip is electrically connected to the conductor pattern portion.
Wherein a Tei Rukoto connected terminals formed to protrude from the surface of the insulating film.
ン部と半導体チップとが電気的に接続され、前記リード
フレームの半導体チップが搭載された片面側が、前記半
導体チップおよび前記導体パターン部を含めて樹脂封止
され、該樹脂封止された封止範囲に対応する 前記リードフレー
ムの他面側が、保護コーティングにより被覆され、 該保護コーティングに前記導体パターン部の接続端子を
形成する部位が底面に露出する透孔が形成され、 該透孔内に、前記導体パターン部と電気的に接続して先
端が前記保護コーティングの表面から突出する接続端子
が形成されていることを特徴とする半導体装置。2. A conductor pattern portion provided on a lead frame and a semiconductor chip are electrically connected to each other, and one side of the lead frame on which the semiconductor chip is mounted includes a tree including the semiconductor chip and the conductor pattern portion. It locked Aburafu, the other surface side of the lead frame corresponding to the sealing range hermetically the resin sealing is coated by protection coating, the connection terminals of the conductive pattern section to the protective coating
A through hole is formed so that a portion to be formed is exposed on the bottom surface. In the through hole , a portion electrically connected to the conductor pattern portion is formed.
End wherein a is Tei Rukoto connection terminal is formed to protrude from the surface of the protective coating.
を特徴とする請求項１または２記載の半導体装置。3. The semiconductor device according to claim 1, wherein said connection terminals are solder bumps.
れたリードフレームの前記導体パターン部の外部接続用
の接続端子を形成する部位にめっきを施し、 該リードフレームの 半導体チップが搭載されて樹脂封止
される片面側とは反対側の他面側に、前記接続端子を形
成する部位にあらかじめ透孔を形成した絶縁性フィルム
を、少なくとも前記片面側の樹脂封止される範囲と対応
する範囲にわたり貼着してリードフレームと絶縁性フィ
ルムとの接合体を形成し、 該接合体の前記パッド部に半導体チップを搭載して該半
導体チップと前記導体パターン部とを電気的に接続し、 前記接合体の半導体チップを搭載した片面側を前記半導
体チップおよび前記導体パターン部を含めて樹脂封止し
た後、 前記絶縁性フィルムを貼着した他面側の前記導体パター
ン部が底面に露出する前記透孔内に、前記導体パターン
部と電気的に接続して先端が前記絶縁性フィルムの表面
から突出する接続端子を形成することを特徴とする半導
体装置の製造方法。 4. An external connection of the conductor pattern portion of a lead frame provided with a pad portion and a conductor pattern portion .
Plating is applied to the part where the connection terminal is formed, and the semiconductor chip of the lead frame is mounted and resin-sealed.
Form the other surface of the opposite side, the connection terminals and one side that is Ru is
Insulating film with pre-formed holes in the parts to be formed
And corresponds to the range that is a resin sealing of at least the one side
And rehabilitation wear cotton in a range of forming a conjugate between the lead frame and the insulating film, and electrically said the pad portion by mounting a semiconductor chip the semiconductor chip and the conductor pattern portions of the conjugate One side of the joined body on which the semiconductor chip is mounted is resin-sealed including the semiconductor chip and the conductor pattern portion.
After that , the conductor pattern on the other side to which the insulating film is attached
The electrically conductive portion is electrically connected to the conductive pattern portion in the through-hole where the conductive portion is exposed on the bottom surface, and the tip is the surface of the insulating film.
Forming a connection terminal protruding from the semiconductor device.
れたリードフレームの前記導体パターン部の外部接続用
の接続端子を形成する部位にめっきを施し、 該リードフレームの 半導体チップが搭載されて樹脂封止
される片面側とは反対側の他面側に、少なくとも前記片
面側の樹脂封止される範囲と対応する範囲にわたり絶縁
性フィルムを貼着してリードフレームと絶縁性フィルム
との接合体を形成し、 該接合体の前記パッド部に半導体チップを搭載して該半
導体チップと前記導体パターン部とを電気的に接続し、 前記接合体の半導体チップを搭載した片面側を前記半導
体チップおよび前記導体パターン部を含めて樹脂封止し
た後、前記絶縁性フィルムに導体パターン部の接続端子を形成
する部位が底面に露出する透孔を形成し、 該透孔内に、前記導体パターン部と電気的に接続して先
端が前記絶縁性フィルムの表面から突出する接続端子を
形成することを特徴とする 半導体装置の製造方法。5. A semiconductor device comprising a pad portion and a conductor pattern portion.
For external connection of the conductor pattern part of the lead frame
Plating is applied to the part where the connection terminal is formed, and the semiconductor chip of the lead frame is mounted and resin-sealed.
On the other side opposite to the one side is at least the piece
Over the range corresponding to the range to be resin sealing surface side by sticking an insulating film to form a joined body of the insulating film and the lead frame, by mounting a semiconductor chip to the pad portion of the conjugate The semiconductor chip and the conductor pattern portion are electrically connected, and one side of the bonded body on which the semiconductor chip is mounted is resin-sealed including the semiconductor chip and the conductor pattern portion.
After that , the connection terminal of the conductor pattern portion is formed on the insulating film.
A through hole is formed at the bottom of the conductive pattern portion, and is electrically connected to the conductor pattern portion in the through hole.
A connection terminal whose end protrudes from the surface of the insulating film
A method for manufacturing a semiconductor device, comprising:
れたリードフレームの前記導体パターン部の外部接続用
の接続端子を形成する部位にめっきを施し、 該リードフレーム の半導体チップが搭載されて樹脂封止
される片面側とは反対側の他面側に、少なくとも前記片
面側の樹脂封止される範囲と対応する範囲にわたり電気
的絶縁性を有する転写フィルムを貼着してリードフレー
ムと転写フィルムとの接合体を形成し、 該接合体の前記パッド部に半導体チップを搭載して該半
導体チップと前記導体パターン部とを電気的に接続し、 前記接合体の半導体チップを搭載した片面側を前記半導
体チップおよび前記導体パターン部を含めて樹脂封止
し、 前記転写フィルムを剥離除去した後、前記リードフレー
ムの転写フィルムが貼着されていた範囲にわたり、導体
パターン部の接続端子を形成する部位を除き保護コーテ
ィングを施し、 該保護コーティングを施したリードフレームの他面側に
露出した前記導体パターン部の接続端子を形成する部位
に、前記導体パターン部と電気的に接続して先端が前記
保護コーティングの表面から突出する接続端子を形成す
ることを特徴とする半導体装置の製造方法。 6. A lead frame provided with a pad portion and a conductor pattern portion for external connection of the conductor pattern portion.
Plating is applied to the part where the connection terminal is formed, and the semiconductor chip of the lead frame is mounted and resin-sealed.
On the other side opposite to the one side is at least the piece
By wearing pasting the transfer film having an electrical insulation to form a joined body of the transfer film and the lead frame over the range corresponding to the range to be resin sealing surface side, the semiconductor chip to the pad portion of the conjugate And electrically connecting the semiconductor chip and the conductor pattern portion, and sealing one side of the bonded body including the semiconductor chip including the semiconductor chip and the conductor pattern portion with the resin, after the peeled off film, the lead frame
Over a range of transfer films of beam has been adhered, the conductor
Protective coating is applied except for the part where the connection terminal of the pattern part is formed , and on the other side of the lead frame on which the protective coating is applied.
A portion of the conductor pattern portion that is exposed to form a connection terminal
The tip is electrically connected to the conductor pattern portion,
A method of manufacturing a semiconductor device, comprising forming a connection terminal projecting from a surface of a protective coating .
れたリードフレームの前記導体パターン部のアウターリ
ードにめっきを施し、 該リードフレームの 半導体チップが搭載されて樹脂封止
される片面側とは反対側の他面側に、少なくとも前記片
面側の樹脂封止される範囲と対応する範囲にわたり電気
的絶縁性を有する転写フィルムを貼着してリードフレー
ムと転写フィルムとの接合体を形成し、 該接合体の前記パッド部に半導体チップを搭載して該半
導体チップと前記導体パターン部とを電気的に接続し、 前記接合体の半導体チップを搭載した片面側を、樹脂封
止される範囲の外方に前記アウターリードを延出させて
前記半導体チップおよび前記導体パターン部を含めて樹
脂封止し、 前記転写フィルムを剥離除去した後、樹脂封止された範
囲と対応するリードフレームの他面側の範囲に保護コー
ティングを施すことを特徴とする半導体装置の製造方
法。7. An outer package of the conductor pattern portion of the lead frame provided with the pad portion and the conductor pattern portion.
The lead frame is plated, and the semiconductor chip of the lead frame is mounted and sealed with resin.
On the other side opposite to the one side of which Ru is, at least the piece
By wearing pasting the transfer film having an electrical insulation to form a joined body of the transfer film and the lead frame over the range corresponding to the range to be resin sealing surface side, the semiconductor chip to the pad portion of the conjugate the mounted and electrically connecting the conductor pattern portion and the semiconductor chip, the one side of mounting the semiconductor chip of the assembly, extending the outer leads outside the range that is tree Aburafutome is not sealed with resin, including the semiconductor chip and the conductive pattern section, after the transfer film was peeled off, it was sealed with a resin range
The method of manufacturing a semiconductor device characterized by applying a protection coating to a range of other surface side of the lead frame and the corresponding circumference.
れるとともに、前記導体パターン部の外部接続用の接続
端子を形成する部位にめっきが施されたリードフレーム
の、半導体チップが搭載されて樹脂封止される片面側と
は反対側の他面側に、少なくとも前記片面側の樹脂封止
される範囲と対応する範囲にわたり、前記導体パターン
部の接続端子を形成する部位が底面に露出する透孔が形
成された絶縁性フィルムが貼着されていることを特徴と
するリードフレームと絶縁性フィルムとの接合体。8. The pad section and the conductor pattern portion provided et <br/> Re Rutotomoni, connections for external connection of the conductive pattern portions
The other side of the lead frame in which the terminal is formed is plated with a lead frame , on the other side opposite to the one side on which the semiconductor chip is mounted and resin-sealed, and at least the one-side resin-sealed area . Bonding between the lead frame and the insulating film, wherein an insulating film formed with a through hole exposing a portion of the conductor pattern portion that forms a connection terminal is exposed on a bottom surface over a corresponding range. body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6398891A JP2962586B2 (en) | 1991-03-05 | 1991-03-05 | Semiconductor device, method of manufacturing the same, and joined body used therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6398891A JP2962586B2 (en) | 1991-03-05 | 1991-03-05 | Semiconductor device, method of manufacturing the same, and joined body used therefor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04277636A JPH04277636A (en) | 1992-10-02 |
| JP2962586B2 true JP2962586B2 (en) | 1999-10-12 |
Family
ID=13245176
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6398891A Expired - Lifetime JP2962586B2 (en) | 1991-03-05 | 1991-03-05 | Semiconductor device, method of manufacturing the same, and joined body used therefor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2962586B2 (en) |
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| JP3413413B2 (en) * | 1994-03-18 | 2003-06-03 | 日立化成工業株式会社 | Semiconductor element mounting substrate and method of manufacturing the same |
| JP3352084B2 (en) * | 1994-03-18 | 2002-12-03 | 日立化成工業株式会社 | Semiconductor element mounting substrate and semiconductor package |
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| JP3352083B2 (en) * | 1994-03-18 | 2002-12-03 | 日立化成工業株式会社 | Method for manufacturing semiconductor package and substrate for mounting semiconductor element |
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Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6278751U (en) * | 1985-11-06 | 1987-05-20 | ||
| JPS63146453A (en) * | 1986-12-10 | 1988-06-18 | Matsushita Electric Ind Co Ltd | Semiconductor package and manufacture of same |
| JP2784209B2 (en) * | 1989-06-08 | 1998-08-06 | 新光電気工業株式会社 | Semiconductor device |
| JP2781020B2 (en) * | 1989-09-06 | 1998-07-30 | モトローラ・インコーポレーテッド | Semiconductor device and manufacturing method thereof |
-
1991
- 1991-03-05 JP JP6398891A patent/JP2962586B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04277636A (en) | 1992-10-02 |
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