JP2953343B2 - Cache control system for distributed memory multiprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache control system for a distributed memory type multiprocessor, and more particularly, to a distributed memory type multiprocessor capable of executing another memory access process overlapping data transfer processing between element processors. The present invention relates to a cache control system for a multiprocessor.

[0002]

2. Description of the Related Art Cache coherence control is one of the important problems in multiprocessor system technology. As generally considered methods, a snoop cache method, a directory method, a software-based method, and the like have been proposed. Among them, the snoop cache method is adopted in many multiprocessor information processing apparatuses. The directory system is also adopted for SC1 (scalable coherent interface) and the like, and is considered to be widely used in the future. However, both methods have advantages and disadvantages, and there are problems in terms of performance or product cost for some application programs.

[0003] As for the software-based method,
Although there is a drawback that a limited-capacity cache cannot be used efficiently, there is little communication between element processors for cache matching control, which contributes to performance improvement, and there is no communication path and the directory Since an expensive storage element such as that described above is not required, it is very advantageous in terms of cost. However, this software-based cache coherence control method has a drawback that it is not possible to reliably determine whether data existing in the cache is valid.

On the other hand, a distributed memory type multiprocessor is
In recent years, due to its scalability and high peak performance, it has been attracting much attention because of its possibility of realizing 1TFLOPS (teraflops) performance, such as being partially commercialized. However, a major obstacle to achieving high performance in a distributed memory type multiprocessor is that the communication performance between element processors does not increase.

[0005] Further, among information processing apparatuses provided today, there are a large number of apparatuses equipped with an extended storage device, and the demand for a large-capacity memory is expected to increase in the future. However, with this, the frequency of data transfer to the extended storage device also increases, so that the influence on the system performance tends to be large, and an improvement in the speed is desired. However, in reality, sufficient consideration has not been given to the cache coherence control in the current multiprocessor. In this regard, for example, a method in which software distinguishes an area for moving read data from the extended storage device to the main storage device and a storage area used for other processing, or a data area written to the main storage device A method of invalidating cached data during data transfer is generally adopted.

[0006]

In the above-mentioned conventional distributed memory type multiprocessor, the inter-element processor
Low data transfer speed can improve performance
This is a major obstacle. In recent years, the aim of the processor
Although there is better performance,
The pursuit of higher performance is expected to continue in the future. Only
In contrast to the speed improvement of the CPU,
Communication performance is orders of magnitude slower.
When including data transfer between servers, no matter how fast the CPU is
Effective performance does not improve. This is a distributed memory type
This is a major factor that has hindered the spread of multiprocessors.

[0007]

In the conventional method, when data is transferred from the extended storage device to the main storage device, the storage area must be managed by software, and during the data transfer process, unrelated processing is performed. There is a problem that execution is not possible due to overlap, and this is a factor that reduces execution performance.

The present invention solves the above-mentioned drawbacks of the prior art, and makes it possible to view the transfer processing between element processors by executing another memory access overlapping with the transfer processing between element processors, which is the biggest factor hindering performance improvement. An object of the present invention is to provide a cache control system of a distributed memory type multiprocessor that can increase the number of times of elimination and can avoid useless cache invalidation which is a drawback of software-based cache control.

[0010]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention relates to a distributed memory type comprising a plurality of element processors each having a combination of a CPU and a memory connected to each other and having a data transfer function between the element processors. In a multiprocessor, the element processor includes a plurality of entries for storing fixed-length block data, and a cache memory including an attribute field for setting attribute information indicating an attribute of data for each entry; Inter-processor data transfer control means for performing an inter-processor data transfer and sending the written address to the cache memory when data is written to the memory provided in the element processor; and Writing from the inter-processor data transfer control means A cache control unit that sets the attribute information in the attribute field of the entry of the cache memory that matches the address, and executes an access instruction to the memory during a data transfer process between the element processors; After the data transfer processing, there is provided an instruction executing means for executing an invalidation instruction for invalidating an entry of the cache memory in which the attribute information is set in the attribute field.

In another aspect, the instruction execution means is executable during the data transfer between an instruction for instructing activation of data transfer between the element processors and an instruction for waiting for completion of the data transfer. It is configured to execute an access instruction.

In still another aspect, the instruction execution means is configured to postpone execution of the access instruction having a cache miss during the data transfer between the element processors until completion of the data transfer.

In another preferred aspect, the cache control means includes: an address comparison means for comparing the write address from the element processor data transfer control means with an address of the cache memory; Setting means for setting the attribute information in the attribute field of the entry of the cache memory based on an address match signal;

Further, in a preferred aspect, the instruction execution means notifies the cache control means that data transfer between the element processors is being performed, and the cache control means transmits the data transfer control information between the element processors. Address comparing means for comparing the write address with the address of the cache memory, and the attribute of the entry of the cache memory based on an address match signal from the address comparing means and a notification during data transfer from the instruction executing means. Setting means for setting the attribute information in a field; and means for invalidating an entry in the cache memory in which the attribute information is set in the attribute field based on an invalid instruction from the instruction executing means.

[0015]

According to the present invention, a mark is set for data that is updated during data transfer processing between element processors and is cached in the cache memory, and during data transfer between element processors, a mark is set. By making the cache memory accessible in the executed processing and invalidating only the cache data marked after the data transfer between the element processors, it is possible to prevent the performance degradation due to the data transfer processing between the element processors, Avoid cache invalidation. That is, the processing determined to be executed before the data transfer between the element processors is inserted between the data transfer start instruction between the element processors and the data transfer end wait instruction between the element processors, and the processing is inserted during the data transfer time between the element processors. By executing the processing, the idle time during which the element processors do nothing is reduced.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a first example of a distributed memory type multiprocessor to which a cache control method according to the present invention is applied.
FIG. 3 is a block diagram illustrating a configuration of an example.

FIG. 1 shows the configuration of one element processor among a plurality of element processors constituting a distributed memory multiprocessor. The other elements have the same configuration.

The element processor 10 of this embodiment includes an instruction control unit 11, a cache control unit 12, a memory access control unit 13, a local memory 14, and a data transfer control unit 15 between element processors. Here, the inter-element-processor data transfer control unit 15 controls data transfer between its own local memory 14 and the local memory 20 of another element processor as a data transfer partner.

A feature of this embodiment is that a mark is set for data that is updated during data transfer processing between element processors and that is cached in the cache memory, and that data is set during data transfer between element processors. By making the cache memory accessible in the executed processing and invalidating only the cache data marked after the data transfer between the element processors, it is possible to prevent the performance degradation due to the data transfer processing between the element processors, The purpose is to avoid cache invalidation.

To realize such characteristics, some degree of program tuning is required. However, the technology required here can be sufficiently achieved by the conventional optimizing compiler technology. In other words, in order to hide the performance degradation of the data transfer between the element processors by other processing, the data transfer processing between the element processors is activated in advance, and the instruction to start the data transfer between the element processors and the instruction to wait for the end of the data transfer between the element processors are issued. By interposing the processing determined to be executed before the data transfer between the element processors and executing the interposed processing during the data transfer time between the element processors, the idle processing in which the element processor does nothing is performed. It is configured to reduce the state time.

Unless a cache miss occurs in a processing block sandwiched between a data transfer start instruction between element processors and a data transfer end wait instruction between element processors, data transfer between element processors and access processing by the processing blocks are executed in parallel. can do. If a cache miss occurs in the processing in the above processing block, the access of the instruction is held by the memory access control unit 13.

During the data transfer processing between the element processors, a mark is set in the associated information in the entry of the cache memory in which the address to be written to the local memory 14 is registered. Only the memory access instruction during the data transfer processing between the element processors is usable data, and must be invalidated after the data transfer between the element processors is completed. Here, the instruction for waiting for the end of data transfer between element processors is an instruction for postponing a process whose operation is not guaranteed until the end of data transfer between element processors. This instruction guarantees the validity of the data transfer between the element processors and the processing after the parallel executable block.

In the embodiment shown in FIG.
Decodes the instruction and sends an access instruction to the cache control unit 12 via the signal line 102. When performing data transfer processing between the element processors, the memory control unit 11 sends the signal lines 103, 1 to the memory access control unit 13 and the data transfer control unit 15 between the element processors.
The transfer start is notified via the command line 05.

Further, the instruction control unit 11 is provided with a mechanism for recognizing a period from the start of the data transfer between the element processors to the end of the data transfer by the notification transmitted from the data transfer control unit 16 between the element processors via the signal line 112. , The instruction control unit 11 notifies the cache control unit 12 of the state via the signal line 104.

The cache control unit 12 processes the memory access instruction from the instruction execution control unit 11, and if a cache miss occurs, the memory access control unit 1
3 is indicated by a signal line 110. Also, during the data transfer processing between the element processors, the address at which the writing to the local memory 14 in the same element processor 10 is performed is notified from the data transfer control section 15 between the element processors to the cache control section 12 by the signal line 115. , If it is held in the cache memory, the entry is marked. Further, when a cache invalidation instruction is issued according to an instruction from the instruction control unit 11, a process of invalidating only the marked entry is performed.

The memory access control unit 13 is connected to the signal line 11
When a cache data request in the event of a cache miss is notified from the cache control unit 12 via the command line 0 to the local memory 14 in the same element processor, the signal line 1
11 to access the requested data. If the data transfer between the element processors is in progress,
The cache data request at the time of a cache miss is suspended until the data transfer processing between the element processors is completed. At this time, the start of the data transfer process between the element processors is performed on the signal line 1.
03, the end is notified to the memory access control unit 13 via the signal line 113.

Data transfer control unit 15 between element processors
Receives an activation instruction sent from the instruction control unit 11 via the signal line 105, and thereby, between the element processors via the signal lines 120 and 121, that is, between the local memory 15 of itself and the local memory 20 of another element processor. Of the data transfer in. At this time, when writing data to the local memory 14 in the same element processor, the inter-element processor data transfer control unit 15 sends the address of the data to be written to the cache control unit 12 via the signal line 115. . When the data transfer process between the element processors is completed, the signal line 11
2, 113, the command control unit 11 and the memory access control unit 13 are notified of the end of the transfer.

FIG. 2 is a block diagram showing a configuration example of the cache control unit 12, which is a feature of this embodiment. In FIG. 2, the cache control unit 12 is configured to control access to a 4-way cache memory. In FIG. 2, only one configuration of the four address arrays is shown, and details of the other address arrays are omitted because they have exactly the same configuration.

In FIG. 2, reference numeral 201 denotes a cache block address register in which an address sent by an access instruction from the instruction control unit 11 or an address 251 sent from the data transfer control unit 16 between the element processors via the signal line 115 is stored. Numeral 202 is a counter for incrementing the value of the upper address of the address stored in the cache block address register 201 every cycle.

Reference numeral 210 denotes an address array; 211, an attribute field for setting attribute information indicating whether an entry to which the address transmitted from the inter-processor data transfer control unit 16 belongs exists in the cache memory;
Is a valid bit indicating whether data in the cache memory is valid.

Reference numeral 213 denotes an inverter 215 of a data transfer instruction signal 260 sent in response to a data transfer start instruction between element processors executed by the instruction control unit 11 and a cache clear signal 261 sent in conjunction with a cache invalidation instruction. AND circuit that takes the logical product with the output of
Is the cache clear signal 261 and the attribute field 211
Is a NAND circuit that performs a NAND operation with the value of? In the attribute field 211, a logical value “1” or “0” output from the AND circuit 213 is set as attribute information. The valid bit 212 includes a NAND circuit 214
Is set as a logical value "1" or "0".
When the value of the attribute field 211 is “1”, it indicates that the object is to be invalidated. Also, the value of the valid bit 212 indicates that it is valid when it is "1".

Reference numeral 216 denotes the lower address 252 of the cache block address register 201 and the address array 2
An address comparator 217 for comparing the addresses of the ten addresses is an AND circuit for calculating the logical product of the output of the address comparator 216 and the valid bit 212, and 218 is a data transfer command signal 26.
An AND circuit for calculating the logical product of 0 and the output of the AND circuit 217, 219 is an AND circuit for calculating the logical product of the cache clear signal 261 and the value of the attribute field 211, and 220 is the logical sum of the outputs of the AND circuits 218 and 219. This is an OR circuit. The timing of the write instruction WE of the address array 210 is set by the output of the OR circuit 220.

Here, the operation at the time of data transfer between element processors and at the time of a cache invalidation instruction will be described with reference to FIG. First, the operation during data transfer between element processors will be described.

At the time of data transfer between the element processors, a data write address 251 for the local memory 15 is sent from the data transfer control section 16 between the element processors via the signal line 115, and a transfer instruction indicating the effective timing is transmitted from the instruction control section 11. A signal 260 is sent. The address 251 is stored in the cache block address register 201. The transfer command signal 260 is input to the AND circuit 213. At this time, at the time of data transfer between the element processors, the cache clear signal 261 has the logical value “0”.
Therefore, the output of the AND circuit 213 has the logical value “1”.

At this time, the lower address 252 of the cache block address register 201 and the address array 2
By comparing the ten addresses with the address comparator 216, it is determined whether the address of the data transferred by the data transfer processing between the element processors exists in the cache memory.

When the address of the data transferred by the data transfer processing between the element processors exists in the cache memory, “1” indicating the address match is output from the address comparator 216 to the AND circuit 217. here,
To the other input of the AND circuit 217, the valid bit 212 of the address array 210 corresponding to the address specified by the upper address 253 of the cache block address register 201 is input. Therefore, valid bit 2
If 12 is “1” indicating validity, the AND circuit 217 outputs a logical value “1”.

Then, the output of the AND circuit 218, which receives the transfer command signal 260 and the output of the AND circuit 217, becomes a logical value "1", so that the write instruction WE of the address array 210 is in a write enable state. As a result, the AND circuit 213 is added to the attribute field 211 of the address array 210 corresponding to the address specified by the upper address 253 of the cache block address register 201.
Is set as a mark indicating a cache invalidation target. Hereinafter, similarly, the above processing is performed for all the write addresses 251 of the data sent from the inter-element-processor data transfer control unit 16. As a result, the mark “1” is set in the attribute field 211 of the address array 210 for the data to be written in the local memory in the data transfer between the element processors and the cached data.

Next, the operation at the time of the cache invalidation instruction will be described with reference to the flowchart of FIG. First,
After the instruction control unit 11 executes the instruction for waiting for the end of the data transfer between the element processors, that is, after the data transfer between the element processors is completed, the instruction control unit 11 executes the cache invalidation instruction. Is sent. At this time, all “0” s are set to the upper address of the cache block address register 201 by the cache invalidation instruction.

When the cache invalidation instruction is executed, first, it is determined whether the valid bit 212 is valid "1" in order from the head address of the address array 210 (step 301). Here, if the valid bit 212 is not valid, the cache block address register 2
01 is stored in the counter 2022 every cycle.
(Step 305), and the processing from step 301 is repeated until all addresses of the address array 210 are accessed (step 306).

In step 301, if the validity bit 212 is valid, it is determined whether the attribute field 211 is to be invalidated, that is, whether the mark "1" is set (step 302). If so, the valid bit 212 of the address array 210 corresponding to the upper address 253 is reset (step 303). This determination is made by comparing the cache clear signal 261 and the attribute field 21 in FIG.
This is performed by the NAND circuit 214 that inputs a value of 1. That is, here, the cache clear signal 261
Is “1”, and if the value of the attribute field 211 is “1”, “0” is output from the NAND circuit 214 and similarly, an AND circuit that inputs the cache clear signal 261 and the value of the attribute field 211 “1” is output from 219 and the write instruction W of the address array 210 is output.
E becomes the write enable state. Therefore, “0” is set to the valid bit 212 of the address array 210 corresponding to the upper address 253, and the valid bit 212 is reset.

At the same time, since "0" of the transfer command signal 260 and the inverted value "0" of the cache clear signal 261 are input to the AND circuit 213, "0" is output from the AND circuit 213. “0” is set in the attribute field 211 of the address array 210 corresponding to the upper address 253 (step 304).

This operation is performed for all entries in the address array (step 306). As a result, the contents of the cache memory marked at the time of data transfer between element processors are invalidated. Therefore, for data written to the local memory 14 at the time of data transfer, the contents of the cache memory are invalidated, and the validity of the data is compensated.

FIG. 4 is a diagram for explaining an example of the contents of a program having an effect according to the present invention. In FIG.
First, an instruction for activating the data transfer processing between the element processors is executed, and the data transfer control section 15 between the element processors is executed.
Starts.

Next, there is a program processing block to be executed during execution of the data transfer processing between the element processors. Even if a load instruction for reading data from the local memory 14 exists in this program processing block,
If there is a hit in the cache, the caching process does not become illegal due to the data transfer process between the element processors being executed at that time. Thereafter, an instruction for waiting for data transfer processing between element processors and a cache invalidation instruction are executed.

In the cache invalidation instruction, when executing the program processing block, the above invalidation is performed only on the cache memory entry in which the local memory 14 is written by the data transfer processing between the element processors. By performing the conversion, the legitimacy of the processing can be compensated for the program processing block after the program processing block.

FIG. 5 is a diagram for explaining the operation sequence of the program in FIG. The execution of the data transfer start instruction between the element processors and the program processing block are executed smoothly, but when the data transfer waiting instruction between the element processors is executed, the execution instruction of the instruction is postponed until the data transfer processing between the element processors is completed. You. This makes it possible to overlap the inter-element processor data transfer start processing / transfer processing with the preceding program processing, so that inter-element processor element-to-element data transfer becomes a major obstacle to performance improvement in distributed memory type parallel processing. Processing can be concealed and processing efficiency can be improved.

FIG. 6 shows a process in the case where a memory access instruction causing a cache miss exists in a program processing unit executed in parallel with the data transfer process between element processors. This is the same as the program in FIG. 4 except that a data load instruction (LD instruction) -3 causing a cache miss exists.

FIG. 7 is a diagram for explaining the operation sequence of the program of FIG. With respect to the LD instruction-3 in which a cache miss has occurred, an access instruction to the local memory 14 is held by the memory access control unit 13 until the data transfer processing between the element processors is completed, thereby avoiding an illegal operation.

FIG. 8 is a block diagram showing the configuration of a second embodiment of the distributed memory type multiprocessor to which the cache control system according to the present invention is applied. In the second embodiment, a distributed memory type multiprocessor for transferring data between the main storage device 81 and the extended storage device 82 is shown. As can be seen from comparison with the first embodiment of FIG. 1, the transfer source memory is the local memory 20 of another element processor.
Or the expansion storage device 82, and the other configurations and operations are completely the same as those of the first embodiment. Therefore, the same reference numerals as those in FIG. Omitted. The configuration of the cache control unit 12 is the same as that of FIG. Although the present invention has been described with reference to the preferred embodiments, the present invention is not necessarily limited to the above embodiments.

[0050]

As described above, according to the cache control system of the distributed memory type multiprocessor of the present invention, another memory access is overlapped with the inter-element processor transfer processing which is the biggest factor preventing the performance improvement. Since the processing is executed, the data transfer processing between the element processors can be concealed, and useless cache invalidation which is a drawback of the conventional software-based cache control can be avoided. This makes it possible to improve the performance of the distributed memory multiprocessor.

After the data transfer between the element processors is completed, only the entry in the cache memory in which the attribute information is set is invalidated, so that the validity of the process can be compensated for in the process after the data transfer.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a distributed memory type multiprocessor to which a cache control system according to the present invention is applied.

FIG. 2 is a block diagram illustrating a configuration example of a cache control unit which is a feature of the present embodiment.

FIG. 3 is a flowchart illustrating an operation of the cache control unit when a cache invalidation instruction is issued.

FIG. 4 is a diagram illustrating an example of the contents of a program that has an effect according to the present invention.

FIG. 5 is a diagram illustrating an operation sequence of the program shown in FIG. 4;

FIG. 6 is a diagram illustrating an example of the contents of a program when a memory access instruction causing a cache miss exists in a program process executed in parallel with the data transfer process between element processors.

FIG. 7 is a diagram illustrating an operation sequence of the program shown in FIG. 6;

FIG. 8 is a block diagram showing a configuration of a second embodiment of the distributed memory type multiprocessor to which the cache control method according to the present invention is applied.

[Explanation of symbols]

 Reference Signs List 10 element processor 11 instruction control unit 12 cache control unit 13 memory access control unit 14, 20 local memory 15 data transfer control unit between element processors 201 cache block address register 202 counter 210 address array 211 attribute field 212 valid bits 213, 217, 218, 219 AND circuit 214 NAND circuit 215 Inverter 216 Address comparator 220 OR circuit

Claims (5)

(57) [Claims] 1. A distributed memory multiprocessor having a plurality of element processors each combining a CPU and a memory and having a data transfer function between the element processors, wherein the element processors store fixed-length block data. A cache memory comprising an attribute field for setting attribute information indicating an attribute of data for each entry, comprising: a plurality of entries to perform the data transfer between the element processors; The data transfer control means for sending the written address to the cache memory when the data is written in the cache memory; and the cache matching the write address from the data transfer control means between the element processors. Memory entry Cache control means for setting the attribute information in the attribute field; executing an access instruction to the memory during data transfer processing between the element processors; A cache control system for a distributed memory type multiprocessor, comprising: an instruction execution unit for executing an invalid instruction for invalidating an entry of the cache memory in which attribute information is set. 2. The method according to claim 1, wherein the instruction execution unit includes: an instruction for instructing activation of data transfer between the element processors; and an instruction for waiting for completion of the data transfer.
2. The cache control system for a distributed memory multiprocessor according to claim 1, wherein an executable access instruction is executed during the data transfer. 3. The instruction execution unit according to claim 1, wherein the instruction execution unit delays execution of the access instruction having caused a cache miss until the data transfer ends during data transfer between the element processors. A cache control system for a distributed memory multiprocessor. 4. The cache control unit includes: an address comparison unit that compares the write address from the element processor data transfer control unit with an address of the cache memory; and an address match signal from the address comparison unit. 2. The cache control system according to claim 1, further comprising a setting unit configured to set the attribute information in the attribute field of the entry of the cache memory. 5. The instruction execution unit notifies the cache control unit that data is being transferred between the element processors, and the cache control unit has the write address from the element processor data transfer control unit. Address comparing means for comparing the address of the cache memory with the address of the cache memory, and the attribute field of the entry of the cache memory based on the address match signal from the address comparing means and the notification during the data transfer from the instruction executing means. 2. The apparatus according to claim 1, further comprising: a setting unit configured to set information; and a unit configured to invalidate an entry of the cache memory in which the attribute information is set in the attribute field based on an invalid instruction from the instruction executing unit. A cache control system for a distributed memory type multiprocessor as described in the above.