JP2890725B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an insulated gate bipolar transistor (IGBT) or power MOSFET for controlling a main current flowing through a semiconductor substrate by a MOS structure provided on the substrate surface.
The present invention relates to a semiconductor device having such an overcurrent protection circuit for a power switching element built in the same semiconductor substrate.

[Conventional technology]

Conventionally, bipolar transistors and MOSFETs have been known as power switching elements, but in addition to this, many IGBTs that have the features of both and can be driven by voltage have come into the market. The IGBT has the advantages that it can be driven by voltage, has a low ON voltage, that is, a small voltage drop in the ON state, and has a relatively high switching speed. On the other hand, since a parasitic thyristor is built in due to its structure, a current control-impossible mode called latch-up has been problematic. Latch-up is described as the operation of a parasitic thyristor when a large amount of current flows. FIG. 2 schematically shows the structure of an IGBT and an equivalent circuit, and shows an n-base layer.
A p ⁺ collector layer 13 sandwiching an n-buffer layer 12 on one side of 11
Exists. A p-well 14 is formed on the surface on the other side of the n- base layer 11, and n ⁺ is added to the source region 15 on the surface.
Are formed. n ⁺ source region 15 of p well 14 and n−
In order to form a channel in a portion sandwiched between the base layers 11, a gate 17 is provided on the surface via an insulating film 16. The emitter electrode 18 is in common contact with the source region 15 and the p-well 14. As shown in the figure, the semiconductor substrate has a p ⁺ collector layer 13, an n- base layer
In addition to a PNP bipolar transistor 21 composed of a P-well 11 and a p-well 14, a parasitic NPN bipolar transistor 22 composed of an n ⁺ source region 15, a p-well 14 and an n- base layer 11 is formed.A parasitic thyristor composed of these two transistors is provided. Exists. Separately, on the surface and on the surface, an n-channel MOSFET 23 is constituted by an n ⁺ source region 15, a p-well 14, an n- base layer 11, an insulating film 16 and a gate 17, and supplies a base current of the transistor 21. Latch-up occurs when the current flowing through the resistor R is large or R is large.
The main cause is that the transistor 22 is turned on. In order to suppress this, it is important to reduce the resistance R, and various structural measures have been devised. As one of them, the depth of the p-well 14 may be increased. However, since the on-resistance of the MOSFET 23 is proportional to the depth of the p-well, this measure increases the element-on voltage.
All of the other measures for reducing the resistance R and other measures for preventing latch-up involve an increase in the on-voltage of the element. Therefore, it is important that the prevention of latch-up can be controlled separately from the ON voltage of the element. As a countermeasure, it is conceivable to incorporate a circuit for performing feedback such that the gate voltage is reduced to reduce the current when an overcurrent flows.
FIG. 3 shows an example of an equivalent circuit. That is, the main IGBT
Connect the current sensing IGBT32 with the current sensing resistor R ₂ in parallel between the emitter terminal E and the collector terminal C in addition to 31, further connects the gate control MOSFET33 between the gate and the emitter of the main IGBT 31, the gate The current sense for IGBT32
To the emitter of The operation of this circuit will be briefly described. When a large current flows through the main IGBT 31, a current I proportional to the large current flows through the IGBT 32 for current sensing. At this time, a voltage of V = R ₂ × I is applied to the gate of the gate control MOSFET 33 by the current sensing resistor R _2, and when this value exceeds the threshold voltage of the MOSFET 33, a current flows through the MOSFET 33 and the resistance is reduced. voltage applied to the gate terminal G by R ₁ and MOSFET33 is to be divided. In this way, the gate voltage of the IGBT 31 mainly decreases, and acts to reduce the current of the main IGBT.

This circuit can be mounted outside the main IGBT, but at the cost of increased costs. Therefore, it is better to form them on the same chip as the IGBT. FIG. 4 shows a part of the structure of a chip incorporating this overcurrent suppression circuit, and the same parts as those in FIGS. 2 and 3 are denoted by the same reference numerals. A current sensing IGBT 32 and a gate control MOSFET 33 having the same structure are formed on the periphery of the main IGBT chip. The gate control MOSFET 33 includes an n ⁺ source region 1 formed on the surface of the substrate.
And a p-well 3, n ⁺ drain region 2 surrounding it, a p-well 4 surrounding it, and a polycrystalline silicon gate 6 provided on the surface with a gate insulating film 5 interposed therebetween. Then, a source electrode commonly contacting the source region 1 and the p well 3
71 the emitter terminal E, the drain electrode 72 in contact with the drain region 2 is connected to the gate terminal G via a resistor R _1,
Also it gate 6 which is connected via a resistor R ₂ to the emitter terminal E is the same as in Figure 3.

[Problems to be solved by the invention]

The structure shown in FIG. 4 can be formed only by changing the pattern in the manufacturing process of the conventional IGBT. At this time, the biggest problem is the parasitic effect relating to the structure of the lateral MOSFET 33 for gate control. The structure shown in FIG.
When forming in the BT manufacturing process, the gate 6 of the lateral MOSFET 33 is used.
Is formed by patterning a polycrystalline silicon layer formed on the substrate surface via a gate insulating film, together with the main IGBT 31 and the gate 17 of the electrode sensing IGBT 3. Horizontal MOSFET33
The p-wells 3 and 4 are formed thereafter. FIG. 5 is an enlarged view of only the lateral MOSFET portion, and shows the p-well.
Reference numerals 3 and 4 denote the p of the IGBT portion by ion implantation and thermal diffusion using the polysilicon gate 6 and the oxide film 8 as a mask.
It is formed simultaneously with the well 14. Since ions are not implanted immediately below the gate 6, both p-wells 3, 3,
If the p-wells 3 and 4 extend laterally due to thermal diffusion and the diffusion depth of the p-wells 3 and 4 is not sufficiently large compared to the channel length, they may be connected to form a constricted shape as shown in the figure or may not be connected. Two separate p-wells. When the p-wells 3 and 4 have a shape as shown in FIG. 5, when the main IGBT 31 is turned off, a part of the hole h filling the n base layer 11 becomes:
Through the source side p-well 3, the source electrode 71 passes through the source terminal 71 to the emitter terminal E, and also enters the drain side p-well 4 and passes through the source electrode 71. At this time, p well
If 3 and 4 are shallow, a resistor 34 is generated between both wells, and the potential of the p-well on the drain side rises.
Injects electrons e into the p-well 4 from. This is n ⁺
Parasitic N composed of drain region 2, p well 4 and n− layer 11
This causes the PN transistor to operate, which is a kind of latch-up and causes element destruction. Further p-well 3,4
If they are shallow and are not connected, static breakdown voltage will be deteriorated.
If the diffusion depths of the p-wells 3 and 4 are made sufficiently large compared to the channel length, such problems of latch-up and breakdown voltage degradation of the lateral MOSFET can be avoided, but at the same time, the p-well 14 of the IGBT section becomes deeper. Therefore, the ON voltage of the main IGBT becomes high. As a result, the trade-off relationship between the prevention of latch-up and the on-state voltage still remains.

Such a problem is caused by the vertical type without the p ⁺ layer 13 shown in FIG.
The same applies to a phenomenon called latchback due to the operation of a parasitic bipolar transistor in a MOSFET.
The same applies to a p-channel IGBT or a p-channel MOSFET in which the conductivity type of each part is exchanged.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problem and to prevent the operation of the parasitic bipolar transistor from occurring even if the lateral diffusion depth of the lateral MOSFET of the overcurrent protection circuit is shallow, without increasing the on-voltage and deteriorating the breakdown voltage. It is an object of the present invention to provide a semiconductor device capable of protecting an IGBT or a MOSFET from an overcurrent.

[Means for solving the problem]

The present invention relates to a power supply switching element, wherein the first conductivity type source region and the drain region are selectively formed on the surface portions of the two second conductivity type regions formed on the surface portion of the first conductivity type layer of the semiconductor substrate of the power switching element. In a semiconductor device having a lateral MOSEFT for controlling a switching element gate voltage in which a region is formed and a gate is provided via an insulating film on the surface of the region sandwiched between the source region and the drain region, The second conductive type resistance region selectively formed on the surface portion where the wiring or the gate of the lateral MOSFET which does not contact the surface of both regions connecting the die regions is formed.

[Action]

By connecting the lateral MOSFET for gate voltage control and the wells of the second conductivity type surrounding the source and drain regions of the first conductivity type with low resistance, current flows in the well region when the power switching element is turned off. Even if this occurs, no large voltage drop occurs, and no potential difference occurs between the drain region and the well region surrounding the drain region. Therefore, the parasitic effect of the parasitic bipolar transistor including the drain region of the first conductivity type, the well region of the second conductivity type, and the layer of the first conductivity type does not occur.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings in which the same reference numerals are given to parts common to the above-described drawings. First
In the embodiment shown in FIGS. 7A and 7B, the source made of Al is drawn by oblique lines which are in common contact with the exposed surface of the opening 81 of the insulating film 8 in the p well 3 and the n ⁺ source region 1. The electrode 71 is extended and is in contact with the exposed surface of the opening 83 of the insulating film 8 of the p-well 4. This extension is indicated by line 70 in FIG.

In another embodiment shown in FIGS. 6A and 6B, a horizontal MO
Ion implantation is also performed outside the end of the gate 6 of the SFET, and p
A P region 9 connecting the well 3 and the p well 4 is formed. Since the gate 6 does not exist on the p region 9, ions are implanted uniformly and the diffusion depth is uniform, so that the p well 3 and the p well 4 are connected with low resistance. The source electrode 71 is also extended over the region 9 in the same manner as in the embodiment of FIG. 1, and the resistance is made lower by bringing the openings 84 and 83 of the insulating film 8 into contact with the p region 9 and the p well 4. This is to prevent a potential difference from occurring between the p-well 4 and the p-well 3.

FIG. 7 shows still another embodiment. In order to further reduce the resistance of the p-well as compared with the embodiment of FIG. 1 or FIG.
Contact portion of source electrode 71 with p-well 3 and source electrode
Highly doped p ⁺
An area 10 is provided.

In the above embodiment, the main switching element is an n-channel IG
In the case of BT, the conductivity type of the semiconductor is p-n inverted p
It is clear that the same can be implemented for channel IGBTs and power MOSFETs.

〔The invention's effect〕

According to the present invention, when the lateral MOSFET constituting the over-electrode protection circuit of the power switching element is incorporated in the same semiconductor substrate as the switching element, the resistance generated between the source side well region and the drain side well region of the lateral MOSFET By removing the influence of the two well regions by connecting them with low resistance, the parasitic effect of the lateral MOSFET could be prevented without increasing the well diffusion depth. As a result, device destruction due to the parasitic effect of the lateral MOSFET is eliminated,
A semiconductor device including a switching element which has a low on-voltage and is not likely to deteriorate in withstand voltage can be obtained.

[Brief description of the drawings]

FIG. 1 shows a lateral MOSFET of a semiconductor device according to one embodiment of the present invention, in which (a) is a plan view and (b) is an A-
FIG. 2 is a schematic cross-sectional view showing the structure and an equivalent circuit of the IGBT, FIG. 3 is a diagram of an overcurrent protection circuit of the IGBT, FIG. FIG. 5 is a cross-sectional view of the lateral MOSFET of FIG. 4, and FIG. 6 shows a lateral MOSFET of a semiconductor device according to another embodiment of the present invention, wherein (a) is a plan view and (b) is (a). 7 is a sectional view of a lateral MOSFET of a semiconductor device according to still another embodiment of the present invention. 1: source region, 2: drain region, 3, 4: p well, 6: gate, 71: source electrode, 72: drain electrode, 9: connection p region.

Claims (4)

(57) [Claims] 1. A source region of a first conductivity type is formed in one of two regions of a second conductivity type formed on a surface portion of a layer of a first conductivity type of a semiconductor substrate of a power switching element, and a source region is formed in the other. A switching element having a lateral MOSFET for controlling a switching element, wherein a drain region of a first conductivity type is formed, and a gate is provided on a surface of a region sandwiched between the source region and the drain region via an insulating film. A semiconductor device, comprising: a wiring that is in contact with both surface regions of two second conductivity type regions and connects the two second conductivity type regions. 2. A first conductivity type source region is formed on one of two second conductivity type regions formed on a surface portion of a first conductivity type layer of a semiconductor substrate of a power switching element, and the other is formed on the other. A switching element having a lateral MOSFET for controlling a switching element formed by forming a drain region of a first conductivity type and providing a gate via an insulating film on the surface of a region sandwiched between the source region and the drain region; Horizontal type of substrate
A semiconductor device having a second conductive type low resistance region selectively formed on a surface portion where a gate of a MOSFET does not exist above and connecting both of the two second conductive type regions. . 3. The semiconductor device according to claim 1, wherein the power switching element is an insulated gate bipolar transistor. 4. The semiconductor device according to claim 1, wherein the power switching element is a vertical MOSFET.