JP2876677B2 - How to check the wheel speed pulse - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of checking a wheel speed pulse for checking whether a signal obtained by converting a wheel speed signal of an automobile into a pulse signal is normal.

[Conventional technology]

As shown in FIG. 6, a vehicle-mounted electronic control device, particularly an anti-lock control device for a vehicle brake, generally converts a wheel speed signal of a wheel speed sensor S _{1 to} S ₄ into a pulse signal by a binarization circuit 01 as shown in FIG. The output value of the counter is latched in the register 03 between the signal whose rising (or falling) is detected by the input processing circuit 05 composed of the edge detecting circuit 02, the register 03 and the counter 04 and the next rising signal. Is read by a central processing unit (hereinafter referred to as a CPU) 06 of a microcomputer, and various predetermined calculations such as a wheel speed, a reference wheel speed (estimated vehicle speed), and a slip ratio are performed. When it is determined that the lock is restored, a pressure reducing signal is output for a short time, and when the lock is restored, a pressurizing signal is output again, and the corresponding solenoid valve 08 is transmitted via any one or some of the drive circuits 07 _{1 to} 07 _4. It is configured to control one or several _{1-08 4.}

[Problems to be solved by the invention]

By the way, in the antilock control device described above, the latch signal obtained by processing the pulse signal from the binarization circuit by the input processing circuit 05 has a timing error when reading the signal and a rise (or fall) signal disorder due to noise. Even if there is, it is read as it is by the CPU 06 as it is, and there is no function provided for checking for such error or deviation of the signal.

However, data reading errors due to irregular pulse signals and timing errors can cause serious accidents if they overlap with other parts such as the malfunction of the CPU itself. This is important for the correct operation of the control device.

The present invention has been made in view of the current state of the wheel speed pulse signal processing method and the monitoring method thereof in the above-described conventional anti-lock control device, and has an object of determining the number of rising and falling edges of the wheel speed pulse signal. The difference is checked at every predetermined measurement time, and if the difference is ± 1 or more, the pulse signal is determined to be abnormal and the rising from the wheel speed pulse signal,
Anti-lock by providing a method of comparing a latch signal at an arbitrary time latched by detecting and latching a falling edge signal and a latch signal immediately before the latch signal to determine whether a pulse signal is abnormal based on a match or mismatch between the two signals. The purpose is to enhance the monitoring function of the control device.

[Means for solving the problem]

Therefore, in the present invention, as means for solving the above-described problems, the rising and falling edges of a pulse signal obtained by converting a detection signal from a wheel speed sensor for each wheel by a binarization circuit are detected to detect the rising and falling edges. Counting and latching the number of falling edges at predetermined measurement times, comparing the sum output of the rising and falling edges and checking whether the difference in the number of edges is ± 1 or less for each wheel, If it exceeds this, a method of checking a wheel speed pulse that determines that the pulse signal is abnormal is adopted.

Further, in the present invention, as another solution, rising and falling edges of a pulse signal obtained by converting a detection signal from a wheel speed sensor for each wheel by a binarization circuit are detected, and rising and falling edges are detected alternately. Each of the falling edge signals is latched, and the latch signal at an arbitrary time is compared with the latch signal immediately before it to check whether or not both signals are different at a predetermined time interval. If they match, a wheel speed pulse checking method is used, which determines that the pulse signal is abnormal.

[Action]

According to the checking method of the first aspect, the difference between the number of rising edges and the number of falling edges of the pulse signal is checked, and the difference is ±
If it is 1 or more, it is determined that the pulse signal is abnormal.

According to the checking method of the second aspect, the rising and falling edge signals are latched from the pulse signal, and the coincidence / mismatch between the latch signal at an arbitrary time and the immediately preceding latch signal is continuously checked to determine whether the latch signal is normal, An abnormal state is determined.
Thus, the monitoring function of the antilock control device is enhanced.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

First Embodiment (FIGS. 1 to 3) FIG. 1 is a diagram showing an example of a circuit for implementing a method of checking a wheel speed pulse according to the first invention.

S _{1 to} S ₄ are wheel speed sensors attached to each wheel of the automobile, 1 is a binarization circuit for converting a signal detected by the sensor into a pulse signal, and 2 is a pulse edge generation circuit. Rising and falling pulse edge signals are generated.

Reference numeral 3 denotes a rising edge detection circuit, and 3 'denotes a falling edge detection circuit, which detects a rising edge and a falling edge from the generated pulse edge signal. Reference numeral 4 is a rising edge count latch, and 4 'is a falling edge count latch, which counts and latches the number of rising edges and falling edges, respectively.

5 is a timer, setting the time t ₁ to count in the count latch. 6 _{1 to} 6 ₄ are comparators for each wheel, respectively, of rising edges counted during time t ₁ . Falling edge Are compared for each wheel, and if the output signal | Δ1 | to | Δ4 | of the difference exceeds a predetermined value as a result of the comparison, the output signal | Δ1 | to | Δ4 | I do.

The output signals | Δ1 | to | Δ4 | are sent to the microcomputer 7,
The presence or absence of an abnormality in the pulse signal converted by the binarization circuit 1 is monitored.

In the circuit of this embodiment configured as described above, the wheel speed pulse is checked as follows.

FIG. 2A shows a waveform of a pulse signal obtained by converting the wheel speed signal detected by _one of the wheel speed sensors S _{1 to} S _{4 by} the binarizing circuit 1. (B) shows a pulse edge generated by the pulse edge generation circuit 2 from the pulse signal. The generated pulse edge corresponds to the rising edge and the falling edge of the rising edge detection circuit 3, respectively.
The number of rising edges and falling edges detected by the falling edge detection circuit 3 'are counted and latched by the rising edge count latch 4 and the falling edge edge count latch 4', respectively.

The sum output of the rising edge and the falling edge latched by the count becomes 8 when the measurement time by the timer 5 is set in the measurement section 1 as shown in FIG. 2C. When the rising number and the falling number are compared by any of the comparators 6 _{1 to} 6 ₄ , the difference output signal ΔN becomes 0, and no output signal is output from the comparator.

When the measurement time by the timer 5 is set in the measurement section 2 as shown in FIG. 2D, the sum output of the rising edge is 8 and the sum output of the falling edge is 7, and any _{one of} the comparators 6 _{1 to} 6 ₄ As a result of the comparison, the output signal ΔN of the difference becomes 1. Also in this case, the comparator is set so that the output signal from the comparator is not output. This is because there is no abnormality in the pulse signal and it is within an error range of the number of edges that can occur when the setting of the measurement section is different.

On the other hand, the measurement time is set to the measurement section 2 in FIG.
In the same way as in (f), measurement section 3 is set, and (e)
Assuming that noise enters at the stage of pulse edge generation as shown in FIG. 7, the sum output of the rising edge is 9 and the sum output of the falling edge is 7, and | ΔN | = 2
Becomes Therefore, when | ΔN | is 2 or more, it is determined that some abnormal state occurs in the pulse signal.

When this case is to detect the abnormal state in either of the comparators ₆₁ through 65 _4, the output signal of the comparator High
(Hereinafter referred to as H), which is sent to the control microcomputer 7 to monitor the abnormal state.

As another case where an abnormal state may occur in the pulse signal, there is a case where an edge disappears due to an edge signal detection failure as shown in FIGS. 2 (g) and 2 (h). As a cause of the edge disappearance, the waveform is distorted due to the noise as shown in FIG. 3A, or the adjacent pulses are closer than the temporal resolution of the detector as shown in FIG. 3B. There are cases.

Second Embodiment (FIGS. 4 and 5) FIG. 4 is a circuit for implementing the method for checking a wheel speed pulse according to the second invention.

S is a wheel speed sensor, 10 is a binarization circuit that converts a signal detected by the wheel sensor into a pulse signal, and 30 is a pulse edge detection circuit, which generates rising and falling pulse edge signals from the pulse signal. I do. U _E represents a rising pulse edge signal, and D _E represents a falling pulse edge signal.

In this embodiment, only one wheel speed sensor S is shown, but actually, a wheel speed sensor S provided for each of four wheels of a vehicle is shown as a representative.

41 is an inverter, 42 and 43 are OR gates, and 50 is a latch circuit. An A input and a T input are input to the latch circuit 50 as shown. When the rising pulse edge signal U _E is detected as the A input, a High (hereinafter referred to as H) signal is latched in Flag 1 and the falling pulse edge signal D _E is latched.
Is detected, a Low (hereinafter referred to as L) signal is latched in Flag1. When the T input is H, the content of Flag1 is F
It is sent to lag2 and at the same time the A input is input to Flag1. This T input is obtained every time the pulse edge signals U _E and D _E are detected.

51 is an Exclusive OR gate, Fl
When both of the output terminals of ag1 and Flag2 are H or L, a signal of L is output. When one of the output terminals is H, and when the other is L, H is output. 52 is an inverter and 60 is a control microcomputer.

In the circuit of this embodiment configured as described above, the wheel speed pulse is checked as follows.

The wheel speed signal from the wheel speed sensor S is detected as a waveform as shown in FIG. 5 (a), and the waveform converted into a pulse signal by the binarization circuit 10 is shown in FIG. 5 (b). A pulse edge signal shown in FIG. 5 (c) is generated from the pulse signal in the pulse edge generation circuit 20, and a rising edge signal U _E and a falling edge signal D _E are generated in the edge detection circuit 30 in FIG. 5 (d). , (E).

The rising, falling signals U _E, if there is erroneous detection by any noise or the like while detecting the D _E, U _E, signal D _E is detected alternately. Since the inverter 41 is inserted in the D _E signal path, the A input of the latch circuit 50 becomes H only when the U _E signal is detected, and becomes L when the D _E signal is detected.

On the other hand, the T input is in the H state in both cases of the rising edge signal and the falling edge signal, and the H input latches the A input to Flag1 of the latch circuit. And T input is H
Each time becomes, the contents of Flag1 are sent to Flag2. For this reason,
The output signals of Flag1 and Flag2 are Low for Flag2 while Flag1 is H, and High for Flag2 while Flag1 is L. in this way
The fact that the latch signals of Flag1 and Flag2 alternately changes
When a latch signal at an arbitrary time is input to ag1, this means that the immediately preceding latch signal is input to Flag2.

Therefore, the above-mentioned latch signals of Flag1 and Flag2 are output and compared by the Exclusive OR gate 51. When one of them is L and the other is H, the output of the OR gate 51 becomes H and is inverted by the inverter 52. Output signal is control microcomputer
Not sent to 60. That is, there is no abnormality in the pulse signal.

However, considering the case where noise enters at the time of detecting a rising edge as shown in FIG. 5 (d), this noise is detected as a rising edge signal, and accordingly, the latch circuit 50
(FIG. 5 (f)).
(G)).

For this reason, as shown in FIG. 5 (h), the A input is kept at H by the T input due to the noise, so that Flag1
Are not at L and remain at H. Also, Flag
Since the latch signal of the previous latch 1 of the second latch signal is also H, the H signal is latched by the T input due to noise as shown in FIG. 5 (i). Then, H is held in the latch signals of Flag1 and Flag2 until the T input by the next falling edge signal is input.

Therefore, the output signals of Flag1 and Flag2 of the latch circuit 50 are changed to Ex.
The exclusive OR gate 51 makes a comparison, and since both output signals are H, the output signal of the Exclusive OR gate 51 becomes L, which is inverted by the inverter 52 and the abnormality detection signal is sent to the control microcomputer 60 (fifth embodiment). Figure (j).

Thus, in this embodiment, in order to check the continuity of the wheel speed pulse, it is checked whether or not the rising and falling edge signals are alternately continuous. If the continuity is abnormal, the pulse signal is abnormal. It is judged as having been done.

〔effect〕

As described above in detail, in the first invention of this application, the rising and falling of the wheel speed pulse signal are detected, and the sum of the rising and falling edges counted and latched at predetermined measurement times is calculated. It is checked whether the difference is less than ± 1. If the difference is more than ± 1, the pulse signal is determined to be abnormal. In the second invention, the rising and falling edge signals of the wheel speed pulse signal detected alternately are respectively detected. By latching and comparing the latch signal at an arbitrary time with the latch signal immediately before it, the two signals are continuously examined, and when both signals match, the pulse signal is determined to be abnormal. Therefore, in any case, the abnormality that the pulse signal is abnormally checked and the function of monitoring the operation of the electronic control unit can be enhanced can be obtained.

[Brief description of the drawings]

FIG. 1 is an overall schematic block diagram of a circuit for implementing a wheel speed pulse checking method according to the first invention, FIG.
FIG. 3 is a diagram for explaining the operation, FIG. 4 is an overall schematic block diagram of a circuit for implementing the method of checking a wheel speed pulse according to the second invention, FIG. 5 is a diagram for explaining the operation, FIG. 6 is an overall schematic block diagram of a conventional on-vehicle electronic control device. 1, 10 binarization circuit, 2, 20 pulse edge generation circuit, 3 rising edge detection circuit, 3 'falling edge detection circuit, 4 rising edge count latch, 4'
…… falling edge count latch, 5 …… timer,
6 ₁ , 6 ₄ … Comparator, 7, 60… Control microcomputer, 30…
Edge detection circuit, 41, 52 …… Inverter, 42, 43 …… OR
Gate, 50 ... Latch circuit, 51 ... Exclusive OR gate.

Continuation of the front page (56) References JP-A-63-89917 (JP, A) JP-A-63-187913 (JP, A) Japanese Utility Model Application No. 63-183556 (JP, U) Japanese Utility Model Application Utility Model No. 64-15115 (JP , U) JP 48-28271 (JP, B1) (58) Fields investigated (Int. Cl. ⁶ , DB name) G01P 3/00-3/80 G01D 5/245 H03K 5/19 G01R 31/02

Claims (2)

(57) [Claims] 1. A rising / falling edge of a pulse signal obtained by converting a detection signal from a wheel speed sensor for each wheel by a binarization circuit, and detecting the number of rising / falling edges for a predetermined measurement time. Count and latch each time, compare the sum output of the rising and falling edges and check if the difference of the number of edges is ± 1 or less for each wheel. If it exceeds this, pulse signal A method for checking wheel speed pulses, wherein it is determined that the vehicle speed is abnormal. 2. A rising and falling edge of a pulse signal obtained by converting a detection signal from a wheel speed sensor for each wheel by a binarizing circuit is detected, and a rising and falling edge signal detected alternately is detected. Each of them is latched, and the latch signal at an arbitrary time and the previous latch signal are compared to continuously check whether or not the two signals are different at a predetermined time interval. A method for checking a wheel speed pulse, comprising determining that a pulse signal is abnormal.