JP2865115B2 - Destuff circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a backbone transmission system, a public network,
The present invention relates to a destuff circuit of a receiving device used in a digital transmission / switching system used for a transmission system such as a subscriber system.

[0002]

2. Description of the Related Art In a digital transmission system, there is a stuff multiplex system as a system for performing synchronous transmission. For example, SO
In NET (Synchronous Optical NETwork),
Synchronous transmission is enabled by stuffing in units of bytes.

FIG. 3 shows a destuff circuit of a receiving apparatus in a conventional stuff multiplexing apparatus. The destuff circuit receives the stuff-multiplexed reception data RD and the reception clock signal R
It receives C and the destuff control signal DC, performs destuff processing on the received data RD using the received clock signal RC and the destuff control signal DC, and outputs output data OD.

Here, the received data RD and the received clock signal RC are frequency- and phase-synchronized signals, and the destuff control signal DC is a stuff information inserted into the received data RD at the time of stuffing by a transmitting unit (not shown). Is a logical "1" level when receiving on the receiving side, and a logical "0" level when there is no stuff information.

As the stuffing method, there are a positive stuffing (P stuff) method in which dummy data is inserted into transmission data and a data signal is transmitted, and a negative stuffing (N stuff) method in which transmission data is advanced. Here, the P-stuff method in units of bytes will be described as an example. Therefore, P-stuff processing is performed on the transmission side, and P destuff processing is performed on the reception side.

The conventional destuff circuit has a write address generation circuit 11, a buffer memory 12, an address phase comparison circuit 13, a low-pass filter 14, a voltage controlled oscillator 15, and a read address generation circuit 16.

In the P destuffing process on the receiving side, the received data RD from which the dummy data inserted by the P stuffing process on the transmitting side is removed is written into the buffer memory 12,
This is achieved by reading the output data OD from the buffer memory 12 at the correct data frequency defined by the received data RD.

More specifically, when the destuff control signal DC is at the logic “0” level, the received data RD is sequentially written to the buffer memory 12 according to the write address generated from the write address generation circuit 11. On the other hand, when the destuff control signal DC is at the logic "1" level, the one-byte dummy data inserted in one P-stuffing process must be deleted. Therefore, the reception clock signal RC is skipped for eight consecutive clocks, and writing of dummy data to the buffer memory 12 is prohibited. Accordingly, it can be seen that the write address generated from the write address generation circuit 11 includes an eight-clock continuous missing component during the P stuff processing. The write address has a write frequency.

The voltage controlled oscillator 15 is an oscillator for generating an oscillating clock signal having an accurate data frequency for defining the received data RD. Read address generation circuit 1
6 generates a read address for reading output data OD from the buffer memory 12 based on the oscillation clock signal. Address phase comparator circuit 13 performs an address phase comparison between the write address and the read address, A
A dress phase difference signal is output. Low-pass filter 14
Cuts the high frequency components of the address phase difference signal,
Outputs control voltage signal. That is, the low-pass filter 14 supplies the address phase difference signal to the voltage controlled oscillator 15 as a control voltage signal. The oscillation frequency of the voltage controlled oscillator 15 is controlled by the control voltage signal. As a result, the oscillation frequency of the voltage controlled oscillator 15 is
Lock to the correct data frequency of D. The read address has a read frequency equal to the oscillation frequency.

With such control, the buffer memory 1
Since the writing frequency and the reading frequency for 2 are equal, destuffing processing in byte units is realized. It is assumed that the destuffing occurs continuously, for example, the destuffing signal DC becomes the logic “1” level for N consecutive times. In this case, N ×
Destuffing processing can be performed by continuously skipping eight clocks.

[0011]

In the destuffing circuit shown in FIG. 3, in order to delete dummy data inserted by the stuffing process, the reception clock signal RC is used.
The frequency of the read clock signal is controlled based on the phase comparison between the continuous clock signal and the oscillation clock signal of the voltage controlled oscillator 15. For this reason, at the time of such continuous omission of the reception clock signal RC, the oscillation frequency of the oscillation clock signal output from the voltage controlled oscillator 15 fluctuates greatly. As a result, there is a problem that the temporal variation of the output data OD, that is, the jitter increases rapidly.

It is an object of the present invention to provide a destuff circuit which suppresses the occurrence of jitter in output data even during continuous omission (byte destuffing) and enables a destuffing process to be continuously generated. It is in.

[0013]

A destuffing circuit to which the present invention is applied is a destuffing circuit for performing a destuffing process on stuff-multiplexed received data, wherein destuffing information inserted into the received data is provided. A memory for storing the received data according to the write address; a voltage controlled oscillator for outputting an oscillation clock signal in response to a voltage control signal; and a memory for generating the write address based on the oscillation clock signal. Means for generating a read address for reading output data from the memory, an address phase comparison between the write address and the read address, and an address representing the address phase difference.
Means for outputting a dress phase difference signal;
Control signal output means for outputting the voltage control signal based on the difference signal .

According to a first aspect of the present invention, the control signal output means includes the destuff information and the address phase.
Means for outputting a dispersed missing clock signal in which the missing of the received clock signal synchronized with the received data is dispersed based on the difference signal, and comparing a clock phase of the dispersed missing clock signal with the oscillation clock signal. to, clock
It has a means for outputting a click phase difference signal, and means for supplying to said voltage controlled oscillator means the clock phase difference signal as the voltage control signal.

According to a second aspect of the present invention, the control signal output means, before Symbol destuffing amount controlled to disperse the toothless density of the received clock signal synchronized with the received data in response to information And the address phase difference signal
Means for controlling the amount of omission by means of control, and performing omission of the reception clock signal under the control of the control means to generate a dispersed omission clock signal; and a means for generating the omission clock signal and the oscillation clock signal. comparing the clock phase, and means for outputting a clock phase difference signal, the click
Means for supplying a lock phase difference signal as the voltage control signal to the voltage controlled oscillation means.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a destuffing circuit of a receiving apparatus in a stuff multiplexing apparatus according to an embodiment of the present invention. The illustrated destuff circuit has the same configuration as that shown in FIG. 3 except that a distributed missing density control circuit 17, a missing tooth generating circuit 18, and a phase comparator 19 are added. Therefore, components having the same function are denoted by the same reference numerals, and their description is omitted.

In this embodiment, the generation of the read clock signal for reading the output data OD from the buffer memory 12 is performed separately from the write clock signal for the buffer memory 12 which is continuously missing, as will be described later. This is achieved by using a dispersed missing clock signal generated by a missing tooth generation circuit 18 which will be described later based on a dispersed missing control signal supplied from the density control circuit 17. This dispersed missing clock signal is a clock signal in which missing writing clock signals are dispersed.

First, the operation of the dispersion missing density control circuit 17 will be described. The destuff control signal DC includes destuff information. Based on the destuffing information included in the destuffing control signal DC and the internal state of the dispersion missing density control circuit 17, the dispersion missing density control circuit 17 adaptively adjusts the dispersion missing density as described below. Change to
The toothless generation circuit 18 is controlled.

It is assumed that N times of destuff information (a destuff control signal DC of logic "1" level) occurs during M frames. In this case, the dispersion tooth omission density control circuit 17
A dispersion omission control signal instructing to omit a clock from the reception clock signal RC at a rate of one clock per (M / 8N) frame is sent to the omission generation circuit 18.

For example, assume that a single P destuffing process occurs during M frames. In this case, the dispersion missing density control circuit 17 outputs eight dispersion missing control signals to (M /
8) It occurs periodically at the frame period. Also, assume that two or two consecutive P destuffing processes occur during M frames. In this case, the dispersion tooth omission density control circuit 17
Generates 16 distributed missing control signals periodically every (M / 16) frame.

The omission generation circuit 18 to which the omission control signal is supplied performs omission of the reception clock signal RC based on the omission control signal. As a result, the dispersed missing clock signal output from the missing tooth generation circuit 18 becomes a clock signal that is frequency-synchronized with the data signal obtained by removing the dummy data from the received data RD.

The phase comparator 19 compares the phase of the dispersion toothless clock signal supplied from the oscillation clock signal and the canceling generation circuit 18 supplied from the voltage controlled oscillator 15, a phase difference signal a low-pass filter 14 The signal is sent to the voltage control oscillator 15 as a voltage control signal via the control circuit. This locks the oscillation frequency of the oscillation clock signal output from the voltage controlled oscillator 15 to the correct data frequency of the received data RD. The read address generation circuit 16 receives this oscillation clock signal as a read clock signal, generates a read address in the buffer memory 12, and reads output data OD from the buffer memory 12.

The operation of the destuff circuit based on the frequency control has been described above. A control system based on such frequency control by the dispersion tooth omission density control circuit 17 is called a frequency control system. With this frequency control, it is possible to suppress the amount of jitter generated by the stuff generated in bursts and the stuff in bytes.

Next, the relationship between the write / read timing control of the buffer memory 12 and the jitter suppression control system will be described.

When a memory stop occurs in the buffer memory 12, the reception data RD cannot be normally received. For this reason, it is necessary to control the write / read timing of the buffer memory 12.

The address phase comparison circuit 13 compares the address phase of the write address generated by the write address generation circuit 11 with the read address generated by the read address generation circuit 16, and determines the address phase difference representing the address phase difference. Output a signal. The address phase difference signal controls the amount of tooth loss of the tooth loss generation circuit 18 so that the address phase difference between the write address and the read address becomes の of the memory size X of the buffer memory 12 of the buffer memory 12. . This prevents a memory stop in the buffer memory 12. A control system based on such phase control by the address phase comparison circuit 13 is called a phase control system.

However, when the destuff circuit is operated by the phase control system, the amount of jitter increases as described in the prior art. Therefore, when suppressing the amount of jitter generation, it is desirable to operate the destuff circuit with a frequency control system.

Therefore, in this embodiment, based on the address phase difference detected by the address phase comparing circuit 13,
As described later, switching between the phase control system and the frequency control system is performed.

FIG. 2 shows the relationship between the address phase difference and the phase control system / frequency control system.

Based on the address phase difference X / 2, the address phase difference detected by the address phase comparator 13 is ±
If it is within the address difference range of Y, the frequency control by the dispersion tooth omission density control circuit 17 is dominant. Otherwise, the phase control by the address phase comparison circuit 13 is dominant. The address difference Y, which is a switching condition between the phase control system and the frequency control system, is a setting parameter.

By adopting the above configuration, if the learning of the dispersion missing density control circuit 17 has been correctly performed, the destuff circuit operates as a frequency control system, so that the jitter can be suppressed. . Further, when the line clock of the reception data RD is switched and the stuff rate changes suddenly, or when the power is turned on, the dispersion omission density control circuit 1
If the learning of 7 is not completed, the destuff circuit operates as a phase control system, so that a memory slip can be prevented.

[0033]

As described above, according to the present invention, it is possible to suppress the amount of jitter generated by the destuffing process in byte units with a simple circuit configuration. In addition, there is an advantage that it is possible to cope with a continuously generated destuffing process. Furthermore, even when the learning of the dispersion tooth omission density control circuit is not completed or when the stuff ratio changes suddenly, it is possible to prevent the occurrence of memory slip.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a destuff circuit according to one embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between an address phase difference and a phase control system / frequency control system.

FIG. 3 is a block diagram showing a conventional destuff circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Write address generation circuit 12 Buffer memory 13 Address phase comparison circuit 14 Low-pass filter 15 Voltage controlled oscillator 16 Read address generation circuit 17 Dispersion missing density control circuit 18 Missing tooth generation circuit 19 Phase comparator

Claims (2)

(57) [Claims] 1. A destuffing circuit for performing a destuffing process on stuff-multiplexed received data, comprising: means for generating a write address based on destuff information inserted into the received data; A memory for storing the received data, voltage-controlled oscillating means for outputting an oscillation clock signal in response to a voltage control signal, and means for generating a read address for reading output data from the memory based on the oscillation clock signal And an address phase comparison between the write address and the read address, and an address representing the address phase difference.
Means for outputting a dress phase difference signal;
Control signal output means for outputting the voltage control signal based on the difference signal , wherein the control signal output means outputs the received data based on the destuff information and the address phase difference signal. Means for outputting a dispersed missing clock signal in which the missing synchronous clock signal is dispersed; comparing the clock phases of the dispersed missing clock signal and the oscillation clock signal to output a clock phase difference signal; And a means for supplying the clock phase difference signal as the voltage control signal to the voltage controlled oscillating means. 2. A destuffing circuit for performing destuffing processing of stuff-multiplexed received data, comprising: means for generating a write address based on destuff information inserted into the received data; A memory for storing the received data, voltage-controlled oscillating means for outputting an oscillation clock signal in response to a voltage control signal, and means for generating a read address for reading output data from the memory based on the oscillation clock signal And an address phase comparison between the write address and the read address, and an address representing the address phase difference.
And means for outputting a de-less phase difference signal, the address phase
In destuffing circuit and a control signal output means for outputting the voltage control signal based on the difference signal, said control signal output means, receiving clock synchronized with the received data in accordance with the amount of prior SL destuffing information Means for controlling so as to disperse the omission density of the signal; and controlling the omission amount by the address phase difference signal.
In both cases , the reception clock signal is controlled under the control of the control means.
Performs omission distributed teeth, means for generating a dispersion-canceling clock signal, the dispersion canceling clock signal and the comparing the oscillation clock signal and the clock phase, and means for outputting a clock phase difference signal, the clock position And a means for supplying a phase difference signal as the voltage control signal to the voltage control oscillating means.